ColdFire: Added MCF5275 cpu support.

PATCH New Matthew Fettke 1 participant 1 message Jan 21, 2008

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Matthew Fettke

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2008-01-21 20:23 UTC #0 lore raw

PATCH 1/1 ColdFire: Added MCF5275 cpu support.

Signed-off-by Matthew Fettke <[email protected]>

---
 CREDITS                       |    1 +
 cpu/mcf52x2/config.mk         |    4 +
 cpu/mcf52x2/cpu.c             |   70 ++++++
 cpu/mcf52x2/cpu_init.c        |  122 ++++++++++
 cpu/mcf52x2/interrupts.c      |    4 +-
 cpu/mcf52x2/speed.c           |    2 +-
 cpu/mcf52x2/start.S           |   30 +++
 include/asm-m68k/immap.h      |   24 ++
 include/asm-m68k/immap_5275.h |  490 +++++++++++++++++++++++++++++++++++++++++
 include/asm-m68k/m5275.h      |  235 ++++++++++++++++++++
 10 files changed, 979 insertions(+), 3 deletions(-)
 create mode 100644 include/asm-m68k/immap_5275.h
 create mode 100644 include/asm-m68k/m5275.h

CREDITS +1 -0

index edf825c..3c19b49 100644
@@ -427,6 +427,7 @@ D: Support for EP82xxM
 N: Art Shipkowski
 E: art at videon-central.com
 D: Support for NetSilicon NS7520
+D: Support for ColdFire MCF5275
 
 N: Michal Simek
 E: monstr at monstr.eu

cpu/mcf52x2/config.mk +4 -0

index f97157d..83888f6 100644
@@ -30,6 +30,7 @@ is5249=$(shell grep CONFIG_M5249 $(TOPDIR)/include/$(cfg))
 is5253=$(shell grep CONFIG_M5253 $(TOPDIR)/include/$(cfg))
 is5271=$(shell grep CONFIG_M5271 $(TOPDIR)/include/$(cfg))
 is5272=$(shell grep CONFIG_M5272 $(TOPDIR)/include/$(cfg))
+is5275=$(shell grep CONFIG_M5275 $(TOPDIR)/include/$(cfg))
 is5282=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg))

@@ -47,6 +48,9 @@ endif
 ifneq (,$(findstring CONFIG_M5272,$(is5272)))
 PLATFORM_CPPFLAGS += -mcpu=5272
 endif
+ifneq (,$(findstring CONFIG_M5275,$(is5275)))
+PLATFORM_CPPFLAGS += -mcpu=5275
+endif
 ifneq (,$(findstring CONFIG_M5282,$(is5282)))
 PLATFORM_CPPFLAGS += -mcpu=5282
 endif

cpu/mcf52x2/cpu.c +70 -0

82 lines not on this page · raw message

cpu/mcf52x2/cpu_init.c +122 -0

134 lines not on this page · raw message

cpu/mcf52x2/interrupts.c +2 -2

index 2ccbde5..805d099 100644
@@ -59,7 +59,7 @@ void dtimer_intr_setup(void)
 #endif				/* CONFIG_MCFTMR */
 #endif				/* CONFIG_M5272 */
 
-#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
+#if defined(CONFIG_M5282) || defined(CONFIG_M5271) || defined(CONFIG_M5275)
 int interrupt_init(void)
 {
 	volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);

@@ -81,7 +81,7 @@ void dtimer_intr_setup(void)
 	intp->imrl0 &= ~CFG_TMRINTR_MASK;
 }
 #endif				/* CONFIG_MCFTMR */
-#endif				/* CONFIG_M5282 | CONFIG_M5271 */
+#endif				/* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
 
 #if defined(CONFIG_M5249) || defined(CONFIG_M5253)
 int interrupt_init(void)

cpu/mcf52x2/speed.c +1 -1

index bc1e200..0ccd048 100644
@@ -65,7 +65,7 @@ int get_clocks (void)
 #endif				/* CONFIG_M5249 || CONFIG_M5253 */
 
 	gd->cpu_clk = CFG_CLK;
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275)
 	gd->bus_clk = gd->cpu_clk / 2;
 #else
 	gd->bus_clk = gd->cpu_clk;

cpu/mcf52x2/start.S +30 -0

index 260a09a..7146e1c 100644
@@ -197,6 +197,17 @@ _copy_flash:
 _after_flash_copy:
 #endif
 
+#ifdef CONFIG_M5275
+	/* Initialize IPSBAR */
+	move.l	#(CFG_MBAR + 1), %d0		/* set IPSBAR address + valid flag */
+	move.l	%d0, 0x40000000
+/*	movec	%d0, %MBAR */
+
+	/* Initialize RAMBAR: locate SRAM and validate it */
+	move.l	#(CFG_INIT_RAM_ADDR + 0x21), %d0
+	movec	%d0, %RAMBAR1
+#endif
+
 #if 0
 	/* invalidate and disable cache */
 	move.l	#0x01000000, %d0		/* Invalidate cache cmd */

@@ -394,6 +405,25 @@ icache_enable:
 	rts
 #endif
 
+#if  defined(CONFIG_M5275)
+/*
+ * Instruction cache only
+ */
+	.globl	icache_enable
+icache_enable:
+	move.l	#0x01400000, %d0		/* Invalidate cache cmd */
+	movec	%d0, %CACR			/* Invalidate cache */
+	move.l	#0x0000c000, %d0		/* Setup SDRAM caching */
+	movec	%d0, %ACR0			/* Enable cache */
+	move.l	#0x00000000, %d0		/* No other caching */
+	movec	%d0, %ACR1			/* Enable cache */
+	move.l	#0x80400100, %d0		/* Setup cache mask */
+	movec	%d0, %CACR			/* Enable cache */
+	moveq	#1, %d0
+	move.l	%d0, icache_state
+	rts
+#endif
+
 #ifdef CONFIG_M5282
 	.globl	icache_enable
 icache_enable:

include/asm-m68k/immap.h +24 -0

index ffb9a37..3aadfc8 100644
@@ -146,6 +146,30 @@
 #endif
 #endif				/* CONFIG_M5272 */
 
+#ifdef CONFIG_M5275
+#include <asm/immap_5275.h>
+#include <asm/m5275.h>
+
+#define CFG_FEC0_IOBASE		(MMAP_FEC0)
+#define CFG_FEC1_IOBASE		(MMAP_FEC1)
+#define CFG_UART_BASE		(MMAP_UART0 + (CFG_UART_PORT * 0x40))
+
+#define CFG_INTR_BASE		(MMAP_INTC0)
+#define CFG_NUM_IRQS		(192)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_TMR_BASE		(MMAP_DTMR3)
+#define CFG_TMRPND_REG		(((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
+#define CFG_TMRINTR_NO		(INT0_LO_DTMR3)
+#define CFG_TMRINTR_MASK	(INTC_IPRL_INT22)
+#define CFG_TMRINTR_PEND	(CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI		(0)
+#define CFG_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+#endif				/* CONFIG_M5275 */
+
 #ifdef CONFIG_M5282
 #include <asm/immap_5282.h>
 #include <asm/m5282.h>

include/asm-m68k/immap_5275.h new file +490 -0

490 lines not on this page · raw message

include/asm-m68k/m5275.h new file +235 -0

235 lines not on this page · raw message

Signature · 1 line

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