86xx: New law setup and updated reginfo patchset

64 lines not on this page · raw message

index 4f8956e..ab5906d 100644
@@ -49,6 +49,10 @@ void cpu_init_f(void)
 	/* Clear initial global data */
 	memset ((void *) gd, 0, sizeof (gd_t));
 
+#ifdef CONFIG_FSL_LAW
+	init_laws();
+#endif
+
 	/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
 	 * addresses - these have to be modified later when FLASH size
 	 * has been determined

@@ -114,5 +118,8 @@ void cpu_init_f(void)
  */
 int cpu_init_r(void)
 {
+#ifdef CONFIG_FSL_LAW
+	disable_law(0);
+#endif
 	return 0;
 }

index 54e40f1..bfea4b3 100644
@@ -27,7 +27,7 @@
 #include <i2c.h>
 #include <spd.h>
 #include <asm/mmu.h>
-
+#include <asm/fsl_law.h>
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void dma_init(void);

@@ -1179,12 +1179,16 @@ spd_sdram(void)
 		/*
 		 * Set up LAWBAR for DDR 1 space.
 		 */
+#ifdef CONFIG_FSL_LAW
+		set_law(1, CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV);
+#else
 		mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
 		mcm->lawar1 = (LAWAR_EN
 			       | LAWAR_TRGT_IF_DDR_INTERLEAVED
 			       | (LAWAR_SIZE & law_size_interleaved));
 		debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
 		debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
+#endif
 		debug("Interleaved memory size is 0x%08lx\n", memsize_total);
 
 #ifdef	CONFIG_DDR_INTERLEAVE

@@ -1239,12 +1243,16 @@ spd_sdram(void)
 		/*
 		 * Set up LAWBAR for DDR 1 space.
 		 */
+#ifdef CONFIG_FSL_LAW
+		set_law(1, CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1);
+#else
 		mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
 		mcm->lawar1 = (LAWAR_EN
 			       | LAWAR_TRGT_IF_DDR1
 			       | (LAWAR_SIZE & law_size_ddr1));
 		debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
 		debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
+#endif
 	}
 
 #if  (CONFIG_NUM_DDR_CONTROLLERS > 1)

@@ -1269,6 +1277,11 @@ spd_sdram(void)
 		/*
 		 * Set up LAWBAR for DDR 2 space.
 		 */
+#ifdef CONFIG_FSL_LAW
+		set_law(8,
+			(ddr1_enabled ? (memsize_ddr1 * 1024 * 1024) : CFG_DDR_SDRAM_BASE),
+			law_size_ddr2, LAW_TRGT_IF_DDR_2);
+#else
 		if (ddr1_enabled)
 			mcm->lawbar8 = (((memsize_ddr1 * 1024 * 1024) >> 12)
 					& 0xfffff);

@@ -1280,6 +1293,7 @@ spd_sdram(void)
 			       | (LAWAR_SIZE & law_size_ddr2));
 		debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8);
 		debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8);
+#endif
 	}
 
 	debug("\nMemory size of DDR2 = 0x%08lx\n", memsize_ddr2);

index 985182f..55ed9a6 100644
@@ -49,6 +49,7 @@
 #define CONFIG_PCI1		1	/* PCIE controler 1 (ULI bridge) */
 #define CONFIG_PCI2		1	/* PCIE controler 2 (slot) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_FSL_LAW		1	/* Use common FSL law init code */
 
 #define CONFIG_TSEC_ENET 		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE

44 lines not on this page · raw message

index a53953c..92b4e7b 100644
@@ -42,6 +42,7 @@
 #define CONFIG_PCIE1		1	/* PCIe 1 connected to ULI bridge */
 #define CONFIG_PCIE2		1	/* PCIe 2 connected to slot */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
 #define CONFIG_ENV_OVERWRITE
 

58 lines not on this page · raw message

index 54eac38..1c1e826 100644
@@ -53,6 +53,7 @@
 #define CONFIG_PCI1		1	/* PCIE controler 1 (slot 1) */
 #define CONFIG_PCI2		1	/* PCIE controler 2 (slot 2) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
 #define CONFIG_TSEC_ENET 		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE

index bfea4b3..e501caf 100644
@@ -1123,7 +1123,6 @@ spd_sdram(void)
 	int memsize_ddr1 = 0;
 	unsigned int law_size_ddr1;
 	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
 #ifdef CONFIG_DDR_INTERLEAVE
 	volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
 #endif

@@ -1181,13 +1180,6 @@ spd_sdram(void)
 		 */
 #ifdef CONFIG_FSL_LAW
 		set_law(1, CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV);
-#else
-		mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
-		mcm->lawar1 = (LAWAR_EN
-			       | LAWAR_TRGT_IF_DDR_INTERLEAVED
-			       | (LAWAR_SIZE & law_size_interleaved));
-		debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
-		debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
 #endif
 		debug("Interleaved memory size is 0x%08lx\n", memsize_total);
 

@@ -1245,13 +1237,6 @@ spd_sdram(void)
 		 */
 #ifdef CONFIG_FSL_LAW
 		set_law(1, CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1);
-#else
-		mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
-		mcm->lawar1 = (LAWAR_EN
-			       | LAWAR_TRGT_IF_DDR1
-			       | (LAWAR_SIZE & law_size_ddr1));
-		debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
-		debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
 #endif
 	}
 

@@ -1281,18 +1266,6 @@ spd_sdram(void)
 		set_law(8,
 			(ddr1_enabled ? (memsize_ddr1 * 1024 * 1024) : CFG_DDR_SDRAM_BASE),
 			law_size_ddr2, LAW_TRGT_IF_DDR_2);
-#else
-		if (ddr1_enabled)
-			mcm->lawbar8 = (((memsize_ddr1 * 1024 * 1024) >> 12)
-					& 0xfffff);
-		else
-			mcm->lawbar8 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
-
-		mcm->lawar8 = (LAWAR_EN
-			       | LAWAR_TRGT_IF_DDR2
-			       | (LAWAR_SIZE & law_size_ddr2));
-		debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8);
-		debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8);
 #endif
 	}
 

index 8bdf5a7..dca6a4d 100644
@@ -28,6 +28,7 @@
 #include <asm/io.h>
 
 #define LAWAR_EN	0x80000000
+#define FSL_HW_NUM_LAWS 10	/* number of LAWs in the hw implementation */
 
 void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
 {

@@ -53,6 +54,24 @@ void disable_law(u8 idx)
 	return;
 }
 
+void print_laws(void)
+{
+	volatile u32 *base = (volatile u32 *)(CFG_IMMR + 0xc08);
+	volatile u32 *lawbar = base;
+	volatile u32 *lawar = base + 2;
+	int i;
+
+	printf("\nLocal Access Window Configuration\n");
+	for(i = 0; i < FSL_HW_NUM_LAWS; i++) {
+		printf("\tLAWBAR%d : 0x%08x, LAWAR%d : 0x%08x\n",
+		       i, in_be32(lawbar), i, in_be32(lawar));
+		lawbar += 8;
+		lawar += 8;
+	}
+
+	return;
+}
+
 void init_laws(void)
 {
 	int i;

index 7cb8840..23bd505 100644
@@ -73,6 +73,7 @@ struct law_entry {
 extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
 extern void disable_law(u8 idx);
 extern void init_laws(void);
+extern void print_laws(void);
 
 /* define in board code */
 extern struct law_entry law_table[];

index bb6aa30..11af22b 100644
@@ -31,6 +31,8 @@
 #include <mpc5xx.h>
 #elif defined (CONFIG_MPC5200)
 #include <mpc5xxx.h>
+#elif defined (CONFIG_MPC86xx)
+extern void mpc86xx_reginfo(void);
 #endif
 
 int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])

@@ -329,14 +331,18 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		*(volatile ulong*)MPC5XXX_SDRAM_CS0CFG);
 	printf ("\tSDRAMCS1: %08X\n",
 		*(volatile ulong*)MPC5XXX_SDRAM_CS1CFG);
-#endif /* CONFIG_MPC5200 */
+#elif defined(CONFIG_MPC86xx)
+	mpc86xx_reginfo();
+#endif /* CONFIG_MPC86xx */
+
 	return 0;
 }
 
  /**************************************************/
 
 #if ( defined(CONFIG_8xx)   || defined(CONFIG_405GP) || \
-      defined(CONFIG_405EP) || defined(CONFIG_MPC5200)  ) && \
+      defined(CONFIG_405EP) || defined(CONFIG_MPC5200) || \
+      defined(CONFIG_MPC86xx)) && \
     defined(CONFIG_CMD_REGINFO)
 
 U_BOOT_CMD(

index 11354d3..e1b3c52 100644
@@ -27,6 +27,7 @@
 #include <command.h>
 #include <asm/cache.h>
 #include <mpc86xx.h>
+#include <asm/fsl_law.h>
 
 #if defined(CONFIG_OF_FLAT_TREE)
 #include <ft_build.h>

@@ -324,6 +325,27 @@ ft_cpu_setup(void *blob, bd_t *bd)
 	if (p != NULL)
 		memcpy(p, bd->bi_enet3addr, 6);
 #endif
+#endif /* CONFIG_OF_FLAT_TREE */
+
+/*
+ * Print out the state of various machine registers.
+ * Currently prints out LAWs and BR0/OR0
+ */
+void mpc86xx_reginfo(void)
+{
+	immap_t *immap = (immap_t *)CFG_IMMR;
+	ccsr_lbc_t *lbc = &immap->im_lbc;
+
+	print_laws();
+
+	printf ("Local Bus Controller Registers\n"
+		"\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0));
+	printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1));
+	printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2));
+	printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3));
+	printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4));
+	printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5));
+	printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6));
+	printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7));
 
 }
-#endif

index 92b4e7b..3920147 100644
@@ -315,6 +315,7 @@
 #define CONFIG_NET_MULTI
 #define CONFIG_CMD_NET
 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
+#define CONFIG_CMD_REGINFO
 
 #define CONFIG_ULI526X
 #ifdef CONFIG_ULI526X

index 55ed9a6..a8d0077 100644
@@ -537,6 +537,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_I2C
+#define CONFIG_CMD_REGINFO
 
 #if defined(CFG_RAMBOOT)
     #undef CONFIG_CMD_ENV

index 1c1e826..1991a8c 100644
@@ -480,6 +480,7 @@
 #include <config_cmd_default.h>
     #define CONFIG_CMD_PING
     #define CONFIG_CMD_I2C
+    #define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI