Support for Artila M-501 starter kit

Hi,

This series of patches adds support for Artila M-501 starter kit:

    http://www.artila.com/p_matrix.html#m_501

The supported features include:
- Atmel AT91RM9200
- SDRAM (32MB on the V02 processor card)
- Serial port DBGU
- LEDs
- Buzzer
- NOR Flash
- Ethernet
- I2C
- RTC

This patch is to be applied on top of the current U-Boot git tree.

Some modifications are based on work done by Alan Lu from Artila.

Kimmo Leppala / Sysart and
Timo Tuunainen / Sysart

Whole patch serie was trashed by your mailer (line wrapped). You didn't follow coding style - http://www.denx.de/wiki/UBoot/CodingStyle
Please make sure you understand what you are copying from other boards source files. struct bd_info_ext is not needed, please remove:
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/33936/
CONFIG_BOOTBINFUNC is obsolete, use CONFIG_SKIP_LOWLEVEL_INIT instead. Btw, do you need this configuration at all? It obviously cannot work.
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/33935/

Best regards,
ladis

---
MAKEALL | 1 +
Makefile | 2 ++
lib_arm/armlinux.c | 2 +-

3 files changed, 4 insertions(+), 1 deletions(-)

index d66a5fa..655e100 100755
@@ -459,6 +459,7 @@ LIST_ARM9=" \

cp946es \
cp966 \
lpd7a400 \
+ m501sk \
mp2usb \
mx1ads \
mx1fs2 \

index 0f6cc59..9200d17 100644
@@ -2313,6 +2313,8 @@ csb637_config : unconfig

mp2usb_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t mp2usb NULL at91rm9200

+m501sk_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm920t m501sk NULL at91rm9200

########################################################################
## ARM Integrator boards - see doc/README-integrator for more info.

index 6d32a41..f12f33c 100644
@@ -160,7 +160,7 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int 

argc, char *argv[],
do_reset (cmdtp, flag, argc, argv);
}

-#if defined(CONFIG_B2) || defined(CONFIG_EVB4510) || defined(CONFIG_ARMADILLO)
+#if defined(CONFIG_B2) || defined(CONFIG_EVB4510) || defined(CONFIG_ARMADILLO) || defined(CONFIG_M501SK) /*
*we need to copy the ramdisk to SRAM to let Linux boot */

1.5.2.5

---
include/configs/m501sk.h | 220
++++++++++++++++++++++++++++++++++++++++++++++

1 files changed, 220 insertions(+), 0 deletions(-)

create mode 100644 include/configs/m501sk.h

new file mode 100644
index 0000000..aad99fd
@@ -0,0 +1,220 @@
+/*
+ * Based on Modifications by Alan Lu / Artila and
+ * Rick Bronson <[email protected]>
+ *
+ * Configuation settings for the Artila M-501 starter kit with V02 

processor card.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000
/ 4 * 39) */
+#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock
(AT91C_MASTER_CLOCK / 3) */
+#define AT91_SLOW_CLOCK 32768 /* slow clock */
+
+#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/* define this to include the functionality of boot.bin in u-boot */
+#undef CONFIG_BOOTBINFUNC
+#undef CONFIG_AUTOBOOT_PROMPT
+#define CONFIG_MENUPROMPT "."
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CFG_AT91C_BRGR_DIVISOR 33 /* hardcode so no __divsi3 :
AT91C_MASTER_CLOCK / baudrate / 16 */
+
+/*
+ * Hardware drivers
+ */
+#define CFG_FLASH_CFI 1
+#define CFG_FLASH_CFI_DRIVER 1
+#define CFG_ENV_SECT_SIZE 0x20000
+#define CFG_FLASH_USE_BUFFER_WRITE
+#define CFG_FLASH_PROTECTION /*for Intel P30 Flash*/
+#define CONFIG_HARD_I2C
+#define CFG_I2C_SPEED 100
+#define CFG_I2C_SLAVE 0
+#define CFG_CONSOLE_INFO_QUIET
+#undef CFG_ENV_IS_IN_EEPROM
+#define CFG_I2C_EEPROM_ADDR 0x50
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_AT24C16
+#define CFG_I2C_RTC_ADDR 0x32
+#undef CONFIG_RTC_DS1338
+#define CONFIG_RTC_RS5C372A
+#undef CONFIG_POST
+#define CONFIG_M501SK
+#define CONFIG_CMC_PU2
+
+/* define one of these to choose the DBGU, USART0 or USART1 as console */
+#define CONFIG_DBGU
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+
+#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
+#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
+
+#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200
initrd=0x20800000,8192000 ramdisk_size=15360 root=/dev/ram0 rw mtdparts=phys_mapped_flash:128k(loader)ro,128k(reserved)ro,1408k(linux)ro,2560k(ramdisk)ro,-(userdisk)" +#define CONFIG_BOOTCOMMAND "bootm 10040000 101a0000"
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_IPADDR 192.168.1.100
+#define CONFIG_SERVERIP 192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.254
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_BOOTFILE uImage
+#define CONFIG_ETHADDR 00:13:48:aa:bb:cc
+#define CONFIG_ENV_OVERWRITE 1
+#define BOARD_LATE_INIT
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "unlock=yes\0"
+
+#define CFG_CMD_JFFS2
+#undef CONFIG_CMD_EEPROM
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_POST
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_ENV
+
+#define CFG_HUSH_PARSER
+#define CONFIG_AUTO_COMPLETE
+#define CFG_PROMPT_HUSH_PS2 ">>"
+
+#define CFG_MAX_NAND_DEVICE 0 /* Max number of NAND devices */
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x20000000
+#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */
+
+#define CFG_MEMTEST_START 0x21000000 /* PHYS_SDRAM */
+#define CFG_MEMTEST_END 0x00100000 /* CFG_MEMTEST_START +
PHYS_SDRAM_SIZE - 262144 */
+
+#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_AT91C_USE_RMII
+
+#define PHYS_FLASH_1 0x10000000
+#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
+#define CFG_FLASH_BASE PHYS_FLASH_1
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_MAX_FLASH_SECT 256
+#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
+
+#ifdef CFG_ENV_IS_IN_DATAFLASH
+#define CFG_ENV_OFFSET 0x20000
+#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
+#define CFG_ENV_SIZE 0x2000
+#else
+#define CFG_ENV_IS_IN_FLASH
+#ifdef CONFIG_BOOTBINFUNC
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x60000)
+#define CFG_ENV_SIZE 0x10000
+#else
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x00020000)
+#define CFG_ENV_SIZE 2048
+#endif
+#endif
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_OFFSET 1024
+#define CFG_ENV_SIZE 1024
+#endif
+
+#define CFG_LOAD_ADDR 0x21000000 /* default load address */
+
+/* use for protect flash sectors */
+#ifdef CONFIG_BOOTBINFUNC
+#define CFG_BOOT_SIZE 0x00 /* 0 KBytes */
+#define CFG_U_BOOT_BASE PHYS_FLASH_1
+#define CFG_U_BOOT_SIZE 0x60000 /* 384 KBytes */
+#else
+#define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */
+#define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)
+#define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */
+#endif
+
+#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
+
+#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 512 /* Console I/O Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer
Size */
+
+#ifndef __ASSEMBLY__ +/*-----------------------------------------------------------------------
+ * Board specific extension for bd_info
+ *
+ * This structure is embedded in the global bd_info (bd_t) structure
+ * and can be used by the board specific code (eg board/...)
+ */
+
+struct bd_info_ext {
+ /* helper variable for board environment handling
+ *
+ * env_crc_valid == 0 => uninitialised
+ * env_crc_valid > 0 => environment crc in flash is valid
+ * env_crc_valid < 0 => environment crc in flash is invalid
+ */
+ int env_crc_valid;
+};
+#endif
+
+#define CFG_HZ 1000
+#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2
+ /* AT91C_TC0_CMR is implicitly set to AT91C_TC_TIMER_DIV1_CLOCK */
+
+#define CONFIG_STACKSIZE (32*1024) /* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif

1.5.2.5

---
board/m501sk/Makefile | 48 +++++++++++
board/m501sk/config.mk | 1 +

board/m501sk/eeprom.c | 88 +++++++++++++++++++++
board/m501sk/m501sk.c | 189 ++++++++++++++++++++++++++++++++++++++++++++
board/m501sk/m501sk.h | 168 +++++++++++++++++++++++++++++++++++++++
board/m501sk/memsetup.S | 200 
+++++++++++++++++++++++++++++++++++++++++++++++
board/m501sk/u-boot.lds | 56 +++++++++++++
7 files changed, 750 insertions(+), 0 deletions(-)

create mode 100644 board/m501sk/Makefile
create mode 100644 board/m501sk/config.mk
create mode 100644 board/m501sk/eeprom.c
create mode 100644 board/m501sk/m501sk.c
create mode 100644 board/m501sk/m501sk.h
create mode 100644 board/m501sk/memsetup.S
create mode 100644 board/m501sk/u-boot.lds

new file mode 100644
index 0000000..5756ea0
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := m501sk.o eeprom.o
+
+SOBJS := memsetup.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

new file mode 100644
index 0000000..9ce161e
@@ -0,0 +1 @@
+TEXT_BASE = 0x21f00000

new file mode 100644
index 0000000..0c6fe0b
@@ -0,0 +1,88 @@
+/*
+ Add by Alan , 07-29-2005
+ For ATMEL AT24C16 EEPROM
+*/
+
+#include <common.h>
+#include <i2c.h>
+#ifdef CFG_EEPROM_AT24C16
+#undef DEBUG
+
+void eeprom_init (void)
+{
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+ i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+#endif
+ /*if(eeprom_probe(0x50, 0)==0)
+ printf("EEPROM Found!\n");*/
+}
+
+int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, 

unsigned cnt)
+{
+ int page,count=0,i=0;
+
+ page = offset / 0x100;
+ i = offset % 0x100;
+
+ while(count < cnt){
+ if (i2c_read (dev_addr|page, i++, 1, buffer+count++, 1) != 0)
+ return 1;
+ if(i > 0xff) {
+ page++;
+ i = 0;
+ }
+ }
+
+ return 0;
+}
+ +/*-----------------------------------------------------------------------
+ *
+ * for CFG_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
+ * 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
+ *
+ * for CFG_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
+ * 0x00000nxx for EEPROM address selectors and page number at n.
+ */
+int eeprom_write (unsigned dev_addr,unsigned offset, uchar *buffer, unsigned cnt)
+{
+ int page,i=0,count=0;
+
+ page = offset / 0x100;
+ i = offset % 0x100;
+
+ while(count < cnt){
+ if (i2c_write (dev_addr|page, i++, 1, buffer+count++, 1) != 0)
+ return 1;
+ if(i > 0xff) {
+ page++;
+ i =0;
+ }
+ }
+
+#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
+ udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#endif
+
+ return 0;
+}
+
+#ifndef CONFIG_SPI
+int eeprom_probe (unsigned dev_addr, unsigned offset)
+{
+ unsigned char chip;
+
+ /* Probe the chip address */
+#if CFG_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
+ chip = offset >> 8; /* block number */
+#else
+ chip = offset >> 16; /* block number */
+#endif /* CFG_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
+
+ chip |= dev_addr; /* insert device address */
+/* printf("i2c_chip:%x\n", chip); */
+ return (i2c_probe (chip));
+}
+#endif
+#endif
+

new file mode 100644
index 0000000..9f71426
@@ -0,0 +1,168 @@
+/*
+ * linux/include/asm-arm/arch-at91/hardware.h
+ *
+ * Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __M501SK_H
+#define __M501SK_H
+
+#ifndef __ASSEMBLY__
+#include <asm-arm/arch-at91rm9200/AT91RM9200.h>
+#else
+#include <asm-arm/arch-at91rm9200/AT91RM9200_inc.h>
+#endif
+
+#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) /* Pin Controlled by 

PA22 */
+#define AT91C_PA22_RXD2 ((unsigned int) AT91C_PIO_PA22) /* USART 2 Receive Data */
+#define AT91C_PA5_TXD3 ((unsigned int) 1 << 5) /* USART 3 Transmit Data */ +#define AT91C_PA6_RXD3 ((unsigned int) 1 << 6) /* USART 3 Receive Data */ +
+/* ========== Register definition for PIOD peripheral ========== */ +#define AT91C_PIOD_PDSR ((AT91_REG *) 0xFFFFFA3C) /* (PIOD) Pin Data Status Register */
+#define AT91C_PIOD_CODR ((AT91_REG *) 0xFFFFFA34) /* (PIOD) Clear Output Data Register */
+#define AT91C_PIOD_OWER ((AT91_REG *) 0xFFFFFAA0) /* (PIOD) Output Write Enable Register */
+#define AT91C_PIOD_MDER ((AT91_REG *) 0xFFFFFA50) /* (PIOD) Multi-driver Enable Register */
+#define AT91C_PIOD_IMR ((AT91_REG *) 0xFFFFFA48) /* (PIOD) Interrupt Mask Register */
+#define AT91C_PIOD_IER ((AT91_REG *) 0xFFFFFA40) /* (PIOD) Interrupt Enable Register */
+#define AT91C_PIOD_ODSR ((AT91_REG *) 0xFFFFFA38) /* (PIOD) Output Data Status Register */
+#define AT91C_PIOD_SODR ((AT91_REG *) 0xFFFFFA30) /* (PIOD) Set Output Data Register */
+#define AT91C_PIOD_PER ((AT91_REG *) 0xFFFFFA00) /* (PIOD) PIO Enable Register */
+#define AT91C_PIOD_OWDR ((AT91_REG *) 0xFFFFFAA4) /* (PIOD) Output Write Disable Register */
+#define AT91C_PIOD_PPUER ((AT91_REG *) 0xFFFFFA64) /* (PIOD) Pull-up Enable Register */
+#define AT91C_PIOD_MDDR ((AT91_REG *) 0xFFFFFA54) /* (PIOD) Multi-driver Disable Register */
+#define AT91C_PIOD_ISR ((AT91_REG *) 0xFFFFFA4C) /* (PIOD) Interrupt Status Register */
+#define AT91C_PIOD_IDR ((AT91_REG *) 0xFFFFFA44) /* (PIOD) Interrupt Disable Register */
+#define AT91C_PIOD_PDR ((AT91_REG *) 0xFFFFFA04) /* (PIOD) PIO Disable Register */
+#define AT91C_PIOD_ODR ((AT91_REG *) 0xFFFFFA14) /* (PIOD) Output Disable Registerr */
+#define AT91C_PIOD_OWSR ((AT91_REG *) 0xFFFFFAA8) /* (PIOD) Output Write Status Register */
+#define AT91C_PIOD_ABSR ((AT91_REG *) 0xFFFFFA78) /* (PIOD) AB Select Status Register */
+#define AT91C_PIOD_ASR ((AT91_REG *) 0xFFFFFA70) /* (PIOD) Select A Register */
+#define AT91C_PIOD_PPUSR ((AT91_REG *) 0xFFFFFA68) /* (PIOD) Pad Pull-up Status Register */
+#define AT91C_PIOD_PPUDR ((AT91_REG *) 0xFFFFFA60) /* (PIOD) Pull-up Disable Register */
+#define AT91C_PIOD_MDSR ((AT91_REG *) 0xFFFFFA58) /* (PIOD) Multi-driver Status Register */
+#define AT91C_PIOD_PSR ((AT91_REG *) 0xFFFFFA08) /* (PIOD) PIO Status Register */
+#define AT91C_PIOD_OER ((AT91_REG *) 0xFFFFFA10) /* (PIOD) Output Enable Register */
+#define AT91C_PIOD_OSR ((AT91_REG *) 0xFFFFFA18) /* (PIOD) Output Status Register */
+#define AT91C_PIOD_IFER ((AT91_REG *) 0xFFFFFA20) /* (PIOD) Input Filter Enable Register */
+#define AT91C_PIOD_BSR ((AT91_REG *) 0xFFFFFA74) /* (PIOD) Select B Register */
+#define AT91C_PIOD_IFDR ((AT91_REG *) 0xFFFFFA24) /* (PIOD) Input Filter Disable Register */
+#define AT91C_PIOD_IFSR ((AT91_REG *) 0xFFFFFA28) /* (PIOD) Input Filter Status Register */
+
+#define AT91C_PIO_PD0 ((unsigned int) 1 << 0) /* Pin Controlled by PD0 */ +#define AT91C_PD0_ETX0 ((unsigned int) AT91C_PIO_PD0) /* Ethernet MAC Transmit Data 0 */
+#define AT91C_PIO_PD1 ((unsigned int) 1 << 1) /* Pin Controlled by PD1 */ +#define AT91C_PD1_ETX1 ((unsigned int) AT91C_PIO_PD1) /* Ethernet MAC Transmit Data 1 */
+#define AT91C_PIO_PD10 ((unsigned int) 1 << 10) /* Pin Controlled by PD10 */
+#define AT91C_PD10_PCK3 ((unsigned int) AT91C_PIO_PD10) /* PMC Programmable Clock Output 3 */
+#define AT91C_PD10_TPS1 ((unsigned int) AT91C_PIO_PD10) /* ETM ARM9 pipeline status 1 */
+#define AT91C_PIO_PD11 ((unsigned int) 1 << 11) /* Pin Controlled by PD11 */
+#define AT91C_PD11_ ((unsigned int) AT91C_PIO_PD11) /* */ +#define AT91C_PD11_TPS2 ((unsigned int) AT91C_PIO_PD11) /* ETM ARM9 pipeline status 2 */
+#define AT91C_PIO_PD12 ((unsigned int) 1 << 12) /* Pin Controlled by PD12 */
+#define AT91C_PD12_ ((unsigned int) AT91C_PIO_PD12) /* */ +#define AT91C_PD12_TPK0 ((unsigned int) AT91C_PIO_PD12) /* ETM Trace Packet 0 */
+#define AT91C_PIO_PD13 ((unsigned int) 1 << 13) /* Pin Controlled by PD13 */
+#define AT91C_PD13_ ((unsigned int) AT91C_PIO_PD13) /* */ +#define AT91C_PD13_TPK1 ((unsigned int) AT91C_PIO_PD13) /* ETM Trace Packet 1 */
+#define AT91C_PIO_PD14 ((unsigned int) 1 << 14) /* Pin Controlled by PD14 */
+#define AT91C_PD14_ ((unsigned int) AT91C_PIO_PD14) /* */ +#define AT91C_PD14_TPK2 ((unsigned int) AT91C_PIO_PD14) /* ETM Trace Packet 2 */
+#define AT91C_PIO_PD15 ((unsigned int) 1 << 15) /* Pin Controlled by PD15 */
+#define AT91C_PD15_TD0 ((unsigned int) AT91C_PIO_PD15) /* SSC Transmit data */
+#define AT91C_PD15_TPK3 ((unsigned int) AT91C_PIO_PD15) /* ETM Trace Packet 3 */
+#define AT91C_PIO_PD16 ((unsigned int) 1 << 16) /* Pin Controlled by PD16 */
+#define AT91C_PD16_TD1 ((unsigned int) AT91C_PIO_PD16) /* SSC Transmit Data 1 */
+#define AT91C_PD16_TPK4 ((unsigned int) AT91C_PIO_PD16) /* ETM Trace Packet 4 */
+#define AT91C_PIO_PD17 ((unsigned int) 1 << 17) /* Pin Controlled by PD17 */
+#define AT91C_PD17_TD2 ((unsigned int) AT91C_PIO_PD17) /* SSC Transmit Data 2 */
+#define AT91C_PD17_TPK5 ((unsigned int) AT91C_PIO_PD17) /* ETM Trace Packet 5 */
+#define AT91C_PIO_PD18 ((unsigned int) 1 << 18) /* Pin Controlled by PD18 */
+#define AT91C_PD18_NPCS1 ((unsigned int) AT91C_PIO_PD18) /* SPI Peripheral Chip Select 1 */
+#define AT91C_PD18_TPK6 ((unsigned int) AT91C_PIO_PD18) /* ETM Trace Packet 6 */
+#define AT91C_PIO_PD19 ((unsigned int) 1 << 19) /* Pin Controlled by PD19 */
+#define AT91C_PD19_NPCS2 ((unsigned int) AT91C_PIO_PD19) /* SPI Peripheral Chip Select 2 */
+#define AT91C_PD19_TPK7 ((unsigned int) AT91C_PIO_PD19) /* ETM Trace Packet 7 */
+#define AT91C_PIO_PD2 ((unsigned int) 1 << 2) /* Pin Controlled by PD2 */ +#define AT91C_PD2_ETX2 ((unsigned int) AT91C_PIO_PD2) /* Ethernet MAC Transmit Data 2 */
+#define AT91C_PIO_PD20 ((unsigned int) 1 << 20) /* Pin Controlled by PD20 */
+#define AT91C_PD20_NPCS3 ((unsigned int) AT91C_PIO_PD20) /* SPI Peripheral Chip Select 3 */
+#define AT91C_PD20_TPK8 ((unsigned int) AT91C_PIO_PD20) /* ETM Trace Packet 8 */
+#define AT91C_PIO_PD21 ((unsigned int) 1 << 21) /* Pin Controlled by PD21 */
+#define AT91C_PD21_RTS0 ((unsigned int) AT91C_PIO_PD21) /* Usart 0 Ready To Send */
+#define AT91C_PD21_TPK9 ((unsigned int) AT91C_PIO_PD21) /* ETM Trace Packet 9 */
+#define AT91C_PIO_PD22 ((unsigned int) 1 << 22) /* Pin Controlled by PD22 */
+#define AT91C_PD22_RTS1 ((unsigned int) AT91C_PIO_PD22) /* Usart 0 Ready To Send */
+#define AT91C_PD22_TPK10 ((unsigned int) AT91C_PIO_PD22) /* ETM Trace Packet 10 */
+#define AT91C_PIO_PD23 ((unsigned int) 1 << 23) /* Pin Controlled by PD23 */
+#define AT91C_PD23_RTS2 ((unsigned int) AT91C_PIO_PD23) /* USART 2 Ready To Send */
+#define AT91C_PD23_TPK11 ((unsigned int) AT91C_PIO_PD23) /* ETM Trace Packet 11 */
+#define AT91C_PIO_PD24 ((unsigned int) 1 << 24) /* Pin Controlled by PD24 */
+#define AT91C_PD24_RTS3 ((unsigned int) AT91C_PIO_PD24) /* USART 3 Ready To Send */
+#define AT91C_PD24_TPK12 ((unsigned int) AT91C_PIO_PD24) /* ETM Trace Packet 12 */
+#define AT91C_PIO_PD25 ((unsigned int) 1 << 25) /* Pin Controlled by PD25 */
+#define AT91C_PD25_DTR1 ((unsigned int) AT91C_PIO_PD25) /* USART 1 Data Terminal ready */
+#define AT91C_PD25_TPK13 ((unsigned int) AT91C_PIO_PD25) /* ETM Trace Packet 13 */
+#define AT91C_PIO_PD26 ((unsigned int) 1 << 26) /* Pin Controlled by PD26 */
+#define AT91C_PD26_TPK14 ((unsigned int) AT91C_PIO_PD26) /* ETM Trace Packet 14 */
+#define AT91C_PIO_PD27 ((unsigned int) 1 << 27) /* Pin Controlled by PD27 */
+#define AT91C_PD27_TPK15 ((unsigned int) AT91C_PIO_PD27) /* ETM Trace Packet 15 */
+#define AT91C_PIO_PD3 ((unsigned int) 1 << 3) /* Pin Controlled by PD3 */ +#define AT91C_PD3_ETX3 ((unsigned int) AT91C_PIO_PD3) /* Ethernet MAC Transmit Data 3 */
+#define AT91C_PIO_PD4 ((unsigned int) 1 << 4) /* Pin Controlled by PD4 */ +#define AT91C_PD4_ETXEN ((unsigned int) AT91C_PIO_PD4) /* Ethernet MAC Transmit Enable */
+#define AT91C_PIO_PD5 ((unsigned int) 1 << 5) /* Pin Controlled by PD5 */ +#define AT91C_PD5_ETXER ((unsigned int) AT91C_PIO_PD5) /* Ethernet MAC Transmikt Coding Error */
+#define AT91C_PIO_PD6 ((unsigned int) 1 << 6) /* Pin Controlled by PD6 */ +#define AT91C_PD6_DTXD ((unsigned int) AT91C_PIO_PD6) /* DBGU Debug Transmit Data */
+#define AT91C_PIO_PD7 ((unsigned int) 1 << 7) /* Pin Controlled by PD7 */ +#define AT91C_PD7_PCK0 ((unsigned int) AT91C_PIO_PD7) /* PMC Programmable Clock Output 0 */
+#define AT91C_PD7_TSYNC ((unsigned int) AT91C_PIO_PD7) /* ETM Synchronization signal */
+#define AT91C_PIO_PD8 ((unsigned int) 1 << 8) /* Pin Controlled by PD8 */ +#define AT91C_PD8_PCK1 ((unsigned int) AT91C_PIO_PD8) /* PMC Programmable Clock Output 1 */
+#define AT91C_PD8_TCLK ((unsigned int) AT91C_PIO_PD8) /* ETM Trace Clock signal */
+#define AT91C_PIO_PD9 ((unsigned int) 1 << 9) /* Pin Controlled by PD9 */ +#define AT91C_PD9_PCK2 ((unsigned int) AT91C_PIO_PD9) /* PMC Programmable Clock 2 */
+#define AT91C_PD9_TPS0 ((unsigned int) AT91C_PIO_PD9) /* ETM ARM9 pipeline status 0 */
+#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */ +#define AT91C_PIO_PC5 ((unsigned int) 1 << 5)
+#define AT91C_PIO_PC14 ((unsigned int) 1 << 14) /* Pin Controlled by PC1 */ +#define AT91C_PIO_PC15 ((unsigned int) 1 << 15) /* Pin Controlled by PC1 */ +#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) /* Pin Controlled by PC1 */ +#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) /* Pin Controlled by PC1 */ +#define AT91C_PIO_PB8 ((unsigned int) 1 << 8)
+#define AT91C_PIO_PB9 ((unsigned int) 1 << 9)
+#define AT91C_PIO_PB10 ((unsigned int) 1 << 10)
+#define AT91C_PIO_PB11 ((unsigned int) 1 << 11)
+#define AT91C_PIO_PB17 ((unsigned int) 1 << 17)
+#define AT91C_PIO_PB28 ((unsigned int) 1 << 28)
+#define AT91C_PIO_PB29 ((unsigned int) 1 << 29)
+
+typedef enum {
+ M501SK_BUZZER=38,
+ M501SK_DEBUG_LED1=96,
+ M501SK_DEBUG_LED2,
+ M501SK_DEBUG_LED3,
+ M501SK_DEBUG_LED4,
+ M501SK_READY_LED=102,
+
+} M501SK_PIO;
+
+void m501sk_gpio_init(void);
+uchar m501sk_gpio_set(M501SK_PIO io);
+uchar m501sk_gpio_clear(M501SK_PIO io);
+
+#endif

from PLLA */
+
+/* sdram */
+#define PIOC_ASR 0xFFFFF870
+#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define PIOC_BSR 0xFFFFF874
+#define PIOC_BSR_VAL 0x00000000
+#define PIOC_PDR 0xFFFFF804
+#define PIOC_PDR_VAL 0xFFFF0000
+#define EBI_CSA 0xFFFFFF60
+#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ +#define SDRC_CR 0xFFFFFF98
+#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */ +#define SDRAM 0x20000000 /* address of the SDRAM */ +#define SDRAM1 0x20000080 /* address of the SDRAM */ +#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ +#define SDRC_MR 0xFFFFFF90
+#define SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define SDRC_MR_VAL1 0x00000004 /* refresh */ +#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define SDRC_TR 0xFFFFFF94
+#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+.globl lowlevelinit
+lowlevelinit:
+ /* memory control configuration */
+ /* this isn't very elegant, but what the heck */
+ ldr r0, =SMRDATA
+ ldr r1, _TEXT_BASE
+ sub r0, r0, r1
+ add r2, r0, #80
+0:
+ /* the address */
+ ldr r1, [r0], #4
+ /* the value */
+ ldr r3, [r0], #4
+ str r3, [r1]
+ cmp r2, r0
+ bne 0b
+ /* delay - this is all done by guess */
+ ldr r0, =0x00010000
+1:
+ subs r0, r0, #1
+ bhi 1b
+ ldr r0, =SMRDATA1
+ ldr r1, _TEXT_BASE
+ sub r0, r0, r1
+ add r2, r0, #176
+2:
+ /* the address */
+ ldr r1, [r0], #4
+ /* the value */
+ ldr r3, [r0], #4
+ str r3, [r1]
+ cmp r2, r0
+ bne 2b
+
+ /* everything is fine now */
+ mov pc, lr
+
+ .ltorg
+
+SMRDATA:
+ .word MC_PUIA
+ .word MC_PUIA_VAL
+ .word MC_PUP
+ .word MC_PUP_VAL
+ .word MC_PUER
+ .word MC_PUER_VAL
+ .word MC_ASR
+ .word MC_ASR_VAL
+ .word MC_AASR
+ .word MC_AASR_VAL
+ .word EBI_CFGR
+ .word EBI_CFGR_VAL
+ .word SMC2_CSR
+ .word SMC2_CSR_VAL
+ .word PLLAR
+ .word PLLAR_VAL
+ .word PLLBR
+ .word PLLBR_VAL
+ .word MCKR
+ .word MCKR_VAL
+ /* SMRDATA is 80 bytes long */
+ /* here there's a delay of 100 */
+SMRDATA1:
+ .word PIOC_ASR
+ .word PIOC_ASR_VAL
+ .word PIOC_BSR
+ .word PIOC_BSR_VAL
+ .word PIOC_PDR
+ .word PIOC_PDR_VAL
+ .word EBI_CSA
+ .word EBI_CSA_VAL
+ .word SDRC_CR
+ .word SDRC_CR_VAL
+ .word SDRC_MR
+ .word SDRC_MR_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRC_MR
+ .word SDRC_MR_VAL1
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRC_MR
+ .word SDRC_MR_VAL2
+ .word SDRAM1
+ .word SDRAM_VAL
+ .word SDRC_TR
+ .word SDRC_TR_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRC_MR
+ .word SDRC_MR_VAL3
+ .word SDRAM
+ .word SDRAM_VAL
+ /* SMRDATA1 is 176 bytes long */
+#endif /* CONFIG_BOOTBINFUNC */

1.5.2.5

---
CREDITS | 16 ++++++++++++++++

1 files changed, 16 insertions(+), 0 deletions(-)

index 57a82d2..b3c55ae 100644
@@ -509,3 +509,19 @@ N: Nobuhiro Iwamatsu

E: iwamatsu at nigauri.org
D: Support for SuperH, MS7750SE01 and MS7722SE01 boards.
W: http://www.nigauri.org/~iwamatsu/
+
+N: Alan Lu
+E: alnalu001 at gmail.com
+D: Support for Artila M-501 starter kit
+W: http://www.artila.com/
+
+N: Kimmo Leppala
+E: kimmo.leppala at sysart.fi
+D: Support for Artila M-501 starter kit
+W: http://www.sysart.fi/
+
+N: Timo Tuunainen
+E: timo.tuunainen at sysart.fi
+D: Support for Artila M-501 starter kit
+W: http://www.sysart.fi/
+

1.5.2.5