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POST: Disable cache while SPR POST

PATCH New Anatolij Gustschin 2 participants 2 messages Feb 25, 2008 – Mar 2, 2008

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Anatolij Gustschin

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PATCH 1/1 POST: Disable cache while SPR POST

Currently (since commit b2e2142c) u-boot crashes on sequoia board while SPR test if CONFIG_4xx_DCACHE is enabled. This patch disables the cache while SPR test.

Signed-off-by Anatolij Gustschin <[email protected]>
---
 post/cpu/ppc4xx/spr.c |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)
post/cpu/ppc4xx/spr.c +14 -0
index c12e378..37c9559 100644
@@ -43,6 +43,12 @@
 
 #include <asm/processor.h>
 
+#ifdef CONFIG_4xx_DCACHE
+#include <asm/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 static struct {
 	int number;
 	char * name;

@@ -164,6 +170,10 @@ int spr_post_test (int flags)
 	};
 	unsigned long (*get_spr) (void) = (void *) code;
 
+#ifdef CONFIG_4xx_DCACHE
+	/* disable cache */
+	change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE);
+#endif
 	for (i = 0; i < spr_test_list_size; i++) {
 		int num = spr_test_list[i].number;
 

@@ -180,6 +190,10 @@ int spr_post_test (int flags)
 			ret = -1;
 		}
 	}
+#ifdef CONFIG_4xx_DCACHE
+	/* enable cache */
+	change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0);
+#endif
 
 	return ret;
 }
Signature · 1 line
1.5.3.3
Applied
#1 lore raw

PATCH 1/1 POST: Disable cache while SPR POST

Quoted 8 lines · In message <[email protected]> you wrote:

Currently (since commit b2e2142c) u-boot crashes on sequoia board while SPR test if CONFIG_4xx_DCACHE is enabled. This patch disables the cache while SPR test.

Signed-off-by Anatolij Gustschin <[email protected]>
---
 post/cpu/ppc4xx/spr.c |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

Signature · 5 lines
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
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