Add support for hammerhead AVR32 board

diff -Nur old/u-boot-avr32/board/miromico/hammerhead/eth.c new/u-boot-avr32/board/miromico/hammerhead/eth.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2008 Miromico AG
+ *
+ * Ethernet initialization for the Miromico Hammerhead AVR32 board
+ *
+ * Mostly copied form Atmel ATNGW100 sources
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/arch/memory-map.h>
+
+extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
+
+#ifdef CONFIG_CMD_NET
+void board_eth_initialize(bd_t *bi)
+{
+	macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
+}
+#endif

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diff -Nur old/u-boot-avr32/cpu/at32ap/at32ap700x/gpio.c new/u-boot-avr32/cpu/at32ap/at32ap700x/gpio.c
@@ -142,3 +142,14 @@
  	gpio_select_periph_A(GPIO_PIN_PA15, 0);	/* DATA3 */
  }
  #endif
+
+#ifdef CONFIG_HAMMERHEAD
+/*
+ * Hammerhead board uses GCLK3 (Periph A on PB29) as 25MHz clock output
+ * for ethernet PHY.
+ */
+void gpio_enable_gclk3(void)
+{
+        gpio_select_periph_A(GPIO_PIN_PB29, 0); /* GCLK3         */
+}
+#endif

diff -Nur old/u-boot-avr32/cpu/at32ap/cpu.c new/u-boot-avr32/cpu/at32ap/cpu.c
@@ -81,6 +81,16 @@
  #endif
  }
 
+#ifdef CONFIG_HAMMERHEAD
+static void gclk_init(void)
+{
+  /* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */
+
+  /* Enable GCLK3 with no input divider, from OSC0 (crystal) */
+  sm_writel( PM_GCCTRL3, SM_BIT(CEN) );
+}
+#endif
+
  int cpu_init(void)
  {
  	extern void _evba(void);

@@ -105,6 +115,10 @@
  	     p += CFG_ICACHE_LINESZ)
  		asm volatile("cache %0, 0x02" : "=m"(*p) :: "memory");
 
+#ifdef CONFIG_HAMMERHEAD
+	gclk_init();
+#endif
+
  	return 0;
  }
 

diff -Nur old/u-boot-avr32/cpu/at32ap/sm.h new/u-boot-avr32/cpu/at32ap/sm.h
@@ -21,7 +21,16 @@
  #define SM_PM_IMR				0x0048
  #define SM_PM_ISR				0x004c
  #define SM_PM_ICR				0x0050
-#define SM_PM_GCCTRL				0x0060
+
+#define SM_PM_GCCTRL0				0x0060
+#define SM_PM_GCCTRL1				0x0064
+#define SM_PM_GCCTRL2				0x0068
+#define SM_PM_GCCTRL3				0x006c
+#define SM_PM_GCCTRL4				0x0070
+#define SM_PM_GCCTRL5				0x0074
+#define SM_PM_GCCTRL6				0x0078
+#define SM_PM_GCCTRL7				0x007c
+
  #define SM_RTC_CTRL				0x0080
  #define SM_RTC_VAL				0x0084
  #define SM_RTC_TOP				0x0088

diff -Nur old/u-boot-avr32/include/asm-avr32/arch-at32ap700x/gpio.h new/u-boot-avr32/include/asm-avr32/arch-at32ap700x/gpio.h
@@ -217,4 +217,8 @@
  void gpio_enable_mmci(void);
  #endif
 
+#ifdef CONFIG_HAMMERHEAD
+void gpio_enable_gclk3(void);
+#endif
+
  #endif /* __ASM_AVR32_ARCH_GPIO_H__ */

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diff -Nur old/u-boot-avr32/net/eth.c new/u-boot-avr32/net/eth.c
@@ -64,6 +64,7 @@
  extern int mcffec_initialize(bd_t*);
  extern int mcdmafec_initialize(bd_t*);
  extern int at91cap9_eth_initialize(bd_t *);
+extern int board_eth_initialize(bd_t *);
 
  #ifdef CONFIG_API
  extern void (*push_packet)(volatile void *, int);

@@ -288,6 +289,8 @@
  	at91cap9_eth_initialize(bis);
  #endif
 
+	board_eth_initialize(bis);
+
  	if (!eth_devices) {
  		puts ("No ethernet found.\n");
  		show_boot_progress (-64);

diff -Naur old/u-boot-avr32/board/miromico/hammerhead/eth.c new/u-boot-avr32/board/miromico/hammerhead/eth.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2008 Miromico AG
+ *
+ * Ethernet initialization for the Miromico Hammerhead AVR32 board
+ *
+ * Mostly copied form Atmel ATNGW100 sources
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/arch/memory-map.h>
+
+extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
+
+#ifdef CONFIG_CMD_NET
+void board_eth_initialize(bd_t *bi)
+{
+	macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
+}
+#endif

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diff -Naur old/u-boot-avr32/cpu/at32ap/at32ap700x/gpio.c new/u-boot-avr32/cpu/at32ap/at32ap700x/gpio.c
@@ -142,3 +142,14 @@
  	gpio_select_periph_A(GPIO_PIN_PA15, 0);	/* DATA3 */
  }
  #endif
+
+#ifdef CONFIG_HAMMERHEAD
+/*
+ * Hammerhead board uses GCLK3 (Periph A on PB29) as 25MHz clock output
+ * for ethernet PHY.
+ */
+void gpio_enable_gclk3(void)
+{
+  gpio_select_periph_A(GPIO_PIN_PB29, 0); /* GCLK3         */
+}
+#endif

diff -Naur old/u-boot-avr32/cpu/at32ap/cpu.c new/u-boot-avr32/cpu/at32ap/cpu.c
@@ -81,6 +81,16 @@
  #endif
  }
 
+#ifdef CONFIG_HAMMERHEAD
+static void gclk_init(void)
+{
+  /* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */
+
+  /* Enable GCLK3 with no input divider, from OSC0 (crystal) */
+  sm_writel( PM_GCCTRL3, SM_BIT(CEN) );
+}
+#endif
+
  int cpu_init(void)
  {
  	extern void _evba(void);

@@ -105,6 +115,10 @@
  	     p += CFG_ICACHE_LINESZ)
  		asm volatile("cache %0, 0x02" : "=m"(*p) :: "memory");
 
+#ifdef CONFIG_HAMMERHEAD
+	gclk_init();
+#endif
+
  	return 0;
  }
 

diff -Naur old/u-boot-avr32/cpu/at32ap/sm.h new/u-boot-avr32/cpu/at32ap/sm.h
@@ -21,7 +21,16 @@
  #define SM_PM_IMR				0x0048
  #define SM_PM_ISR				0x004c
  #define SM_PM_ICR				0x0050
-#define SM_PM_GCCTRL				0x0060
+
+#define SM_PM_GCCTRL0				0x0060
+#define SM_PM_GCCTRL1				0x0064
+#define SM_PM_GCCTRL2				0x0068
+#define SM_PM_GCCTRL3				0x006c
+#define SM_PM_GCCTRL4				0x0070
+#define SM_PM_GCCTRL5				0x0074
+#define SM_PM_GCCTRL6				0x0078
+#define SM_PM_GCCTRL7				0x007c
+
  #define SM_RTC_CTRL				0x0080
  #define SM_RTC_VAL				0x0084
  #define SM_RTC_TOP				0x0088

diff -Naur old/u-boot-avr32/include/asm-avr32/arch-at32ap700x/gpio.h new/u-boot-avr32/include/asm-avr32/arch-at32ap700x/gpio.h
@@ -217,4 +217,8 @@
  void gpio_enable_mmci(void);
  #endif
 
+#ifdef CONFIG_HAMMERHEAD
+void gpio_enable_gclk3(void);
+#endif
+
  #endif /* __ASM_AVR32_ARCH_GPIO_H__ */

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diff -Naur old/u-boot-avr32/net/eth.c new/u-boot-avr32/net/eth.c
@@ -64,6 +64,7 @@
  extern int mcffec_initialize(bd_t*);
  extern int mcdmafec_initialize(bd_t*);
  extern int at91cap9_eth_initialize(bd_t *);
+extern int board_eth_initialize(bd_t *);
 
  #ifdef CONFIG_API
  extern void (*push_packet)(volatile void *, int);

@@ -287,6 +288,9 @@
  #if defined(CONFIG_AT91CAP9)
  	at91cap9_eth_initialize(bis);
  #endif
+#if defined(CONFIG_HAMMERHEAD)
+	board_eth_initialize(bis);
+#endif
 
  	if (!eth_devices) {
  		puts ("No ethernet found.\n");