asm headers' updates

U-Boot-Users Shinya Kuribayashi 2 participants 4 messages Mar 17, 2008 – Mar 25, 2008

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Shinya Kuribayashi

author

2008-03-17 14:43 UTC #0 lore raw

Make some asm headers adjusted to the latest Linux kernel. Note: there might be some CodingStyle issues, but let's leave thins as they are to have a clear difference against the Linux ones.

Signed-off-by Shinya Kuribayashi <[email protected]>

---

 include/asm-mips/byteorder.h |   63 ++++++++++++++++++++++++++++++----
 include/asm-mips/cachectl.h  |   10 +++--
 include/asm-mips/cacheops.h  |   78 +++++++++++++++++++++++++++++++-----------
 include/asm-mips/regdef.h    |   60 +++++++++++++++++++++++++++++---
 include/asm-mips/types.h     |   31 +++++++++++++++--
 5 files changed, 200 insertions(+), 42 deletions(-)

include/asm-mips/byteorder.h +55 -8

index b9604cf..a10ac27 100644
@@ -1,18 +1,65 @@
-/* $Id: byteorder.h,v 1.8 1998/11/02 09:29:32 ralf Exp $
- *
+/*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) by Ralf Baechle
+ * Copyright (C) 1996, 99, 2003 by Ralf Baechle
  */
-#ifndef _MIPS_BYTEORDER_H
-#define _MIPS_BYTEORDER_H
+#ifndef _ASM_BYTEORDER_H
+#define _ASM_BYTEORDER_H
 
+#if 0
+#include <linux/compiler.h>
+#endif
 #include <asm/types.h>
 
 #ifdef __GNUC__
 
+#ifdef CONFIG_CPU_MIPSR2
+
+static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
+{
+	__asm__(
+	"	wsbh	%0, %1			\n"
+	: "=r" (x)
+	: "r" (x));
+
+	return x;
+}
+#define __arch__swab16(x)	___arch__swab16(x)
+
+static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
+{
+	__asm__(
+	"	wsbh	%0, %1			\n"
+	"	rotr	%0, %0, 16		\n"
+	: "=r" (x)
+	: "r" (x));
+
+	return x;
+}
+#define __arch__swab32(x)	___arch__swab32(x)
+
+#ifdef CONFIG_CPU_MIPS64_R2
+
+static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
+{
+	__asm__(
+	"	dsbh	%0, %1			\n"
+	"	dshd	%0, %0			\n"
+	"	drotr	%0, %0, 32		\n"
+	: "=r" (x)
+	: "r" (x));
+
+	return x;
+}
+
+#define __arch__swab64(x)	___arch__swab64(x)
+
+#endif /* CONFIG_CPU_MIPS64_R2 */
+
+#endif /* CONFIG_CPU_MIPSR2 */
+
 #if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
 #  define __BYTEORDER_HAS_U64__
 #  define __SWAB_64_THRU_32__

@@ -20,12 +67,12 @@
 
 #endif /* __GNUC__ */
 
-#if defined (__MIPSEB__)
+#if defined(__MIPSEB__)
 #  include <linux/byteorder/big_endian.h>
-#elif defined (__MIPSEL__)
+#elif defined(__MIPSEL__)
 #  include <linux/byteorder/little_endian.h>
 #else
 #  error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
 #endif
 
-#endif /* _MIPS_BYTEORDER_H */
+#endif /* _ASM_BYTEORDER_H */

include/asm-mips/cachectl.h +6 -4

index 9cc2b87..f3ce721 100644
@@ -1,10 +1,12 @@
 /*
- * cachectl.h -- defines for MIPS cache control system calls
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
  *
  * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
  */
-#ifndef	__ASM_MIPS_CACHECTL
-#define	__ASM_MIPS_CACHECTL
+#ifndef	_ASM_CACHECTL
+#define	_ASM_CACHECTL
 
 /*
  * Options for cacheflush system call

@@ -21,4 +23,4 @@
 #define CACHEABLE	0	/* make pages cacheable */
 #define UNCACHEABLE	1	/* make pages uncacheable */
 
-#endif	/* __ASM_MIPS_CACHECTL */
+#endif	/* _ASM_CACHECTL */

include/asm-mips/cacheops.h +58 ~~-20~~

101 lines not on this page · raw message

include/asm-mips/regdef.h +54 -6

73 lines not on this page · raw message

include/asm-mips/types.h +27 -4

index 707cbf4..2dd147f 100644
@@ -1,5 +1,4 @@
-/* $Id: types.h,v 1.3 1999/08/18 23:37:50 ralf Exp $
- *
+/*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.

@@ -10,6 +9,8 @@
 #ifndef _ASM_TYPES_H
 #define _ASM_TYPES_H
 
+#ifndef __ASSEMBLY__
+
 typedef unsigned short umode_t;
 
 /*

@@ -40,11 +41,18 @@ __extension__ typedef unsigned long long __u64;
 
 #endif
 
+#endif /* __ASSEMBLY__ */
+
 /*
  * These aren't exported outside the kernel to avoid name space clashes
  */
 #ifdef __KERNEL__
 
+#define BITS_PER_LONG _MIPS_SZLONG
+
+#ifndef __ASSEMBLY__
+
+
 typedef __signed char s8;
 typedef unsigned char u8;

@@ -68,9 +76,24 @@ typedef unsigned long long u64;
 
 #endif
 
-#define BITS_PER_LONG _MIPS_SZLONG
+#if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \
+    || defined(CONFIG_64BIT)
+typedef u64 dma_addr_t;
+#else
+typedef u32 dma_addr_t;
+#endif
+typedef u64 dma64_addr_t;
+
+/*
+ * Don't use phys_t.  You've been warned.
+ */
+#ifdef CONFIG_64BIT_PHYS_ADDR
+typedef unsigned long long phys_t;
+#else
+typedef unsigned long phys_t;
+#endif
 
-typedef unsigned long dma_addr_t;
+#endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */

Wolfgang Denk

2008-03-17 21:08 UTC #1 lore raw

Quoted 3 lines · In message <[email protected]> you wrote:

Make some asm headers adjusted to the latest Linux kernel. Note: there might be some CodingStyle issues, but let's leave thins as they are to have a clear difference against the Linux ones.

Umm...only where it really makes sense, please.

include/asm-mips/byteorder.h line 13

Quoted 3 lines

include/asm-mips/byteorder.h +3 -0
+#if 0
+#include <linux/compiler.h>
+#endif

Please don't add dead code. Instead, remove these line(s).

Best regards,

Wolfgang Denk

Signature · 4 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The speed of time is one second per second.

Shinya Kuribayashi

author

2008-03-18 00:04 UTC #2 lore raw

Quoted 5 lines · Wolfgang Denk

include/asm-mips/byteorder.h line 13
Quoted 3 lines
include/asm-mips/byteorder.h +3 -0
+#if 0
+#include <linux/compiler.h>
+#endif
Please don't add dead code. Instead, remove these line(s).

Fixed. Thanks,

Shinya

Shinya Kuribayashi

author

2008-03-25 05:44 UTC #3 lore raw

Quoted 7 lines · Shinya Kuribayashi

Quoted 4 lines · Wolfgang Denk
Review
Quoted 3 lines
(quoted diff) +3 -0
+#if 0
+#include <linux/compiler.h>
+#endif
Please don't add dead code. Instead, remove these line(s).
Fixed. Thanks,

Patch revised. I updated more files, and cleaned up CodingStyle issues all over the headers,

================>

[MIPS] asm headers' updates

Make some asm headers adjusted to the latest Linux kernel.

Signed-off-by Shinya Kuribayashi <[email protected]>

---

 include/asm-mips/byteorder.h |   60 +++++++++-
 include/asm-mips/cachectl.h  |   10 +-
 include/asm-mips/cacheops.h  |   78 ++++++++++---
 include/asm-mips/isadep.h    |    5 -
 include/asm-mips/processor.h |  249 +++++++++---------------------------------
 include/asm-mips/ptrace.h    |   67 ++++++-----
 include/asm-mips/reg.h       |  134 ++++++++++++++++-------
 include/asm-mips/regdef.h    |  126 +++++++++++++++------
 include/asm-mips/types.h     |   30 ++++-
 9 files changed, 416 insertions(+), 343 deletions(-)

include/asm-mips/byteorder.h +52 -8

index b9604cf..b5e685f 100644
@@ -1,18 +1,62 @@
-/* $Id: byteorder.h,v 1.8 1998/11/02 09:29:32 ralf Exp $
- *
+/*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) by Ralf Baechle
+ * Copyright (C) 1996, 99, 2003 by Ralf Baechle
  */
-#ifndef _MIPS_BYTEORDER_H
-#define _MIPS_BYTEORDER_H
+#ifndef _ASM_BYTEORDER_H
+#define _ASM_BYTEORDER_H
 
 #include <asm/types.h>
 
 #ifdef __GNUC__
 
+#ifdef CONFIG_CPU_MIPSR2
+
+static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
+{
+	__asm__(
+	"	wsbh	%0, %1			\n"
+	: "=r" (x)
+	: "r" (x));
+
+	return x;
+}
+#define __arch__swab16(x)	___arch__swab16(x)
+
+static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
+{
+	__asm__(
+	"	wsbh	%0, %1			\n"
+	"	rotr	%0, %0, 16		\n"
+	: "=r" (x)
+	: "r" (x));
+
+	return x;
+}
+#define __arch__swab32(x)	___arch__swab32(x)
+
+#ifdef CONFIG_CPU_MIPS64_R2
+
+static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
+{
+	__asm__(
+	"	dsbh	%0, %1			\n"
+	"	dshd	%0, %0			\n"
+	"	drotr	%0, %0, 32		\n"
+	: "=r" (x)
+	: "r" (x));
+
+	return x;
+}
+
+#define __arch__swab64(x)	___arch__swab64(x)
+
+#endif /* CONFIG_CPU_MIPS64_R2 */
+
+#endif /* CONFIG_CPU_MIPSR2 */
+
 #if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
 #  define __BYTEORDER_HAS_U64__
 #  define __SWAB_64_THRU_32__

@@ -20,12 +64,12 @@
 
 #endif /* __GNUC__ */
 
-#if defined (__MIPSEB__)
+#if defined(__MIPSEB__)
 #  include <linux/byteorder/big_endian.h>
-#elif defined (__MIPSEL__)
+#elif defined(__MIPSEL__)
 #  include <linux/byteorder/little_endian.h>
 #else
 #  error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
 #endif
 
-#endif /* _MIPS_BYTEORDER_H */
+#endif /* _ASM_BYTEORDER_H */

include/asm-mips/cachectl.h +6 -4

index 9cc2b87..f3ce721 100644
@@ -1,10 +1,12 @@
 /*
- * cachectl.h -- defines for MIPS cache control system calls
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
  *
  * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
  */
-#ifndef	__ASM_MIPS_CACHECTL
-#define	__ASM_MIPS_CACHECTL
+#ifndef	_ASM_CACHECTL
+#define	_ASM_CACHECTL
 
 /*
  * Options for cacheflush system call

@@ -21,4 +23,4 @@
 #define CACHEABLE	0	/* make pages cacheable */
 #define UNCACHEABLE	1	/* make pages uncacheable */
 
-#endif	/* __ASM_MIPS_CACHECTL */
+#endif	/* _ASM_CACHECTL */

include/asm-mips/cacheops.h +58 ~~-20~~

101 lines not on this page · raw message

include/asm-mips/isadep.h +2 -3

index 3cd1eb8..24c6cda 100644
@@ -1,16 +1,15 @@
 /*
- * Various ISA level dependant constants.
+ * Various ISA level dependent constants.
  * Most of the following constants reflect the different layout
  * of Coprocessor 0 registers.
  *
  * Copyright (c) 1998 Harald Koerfgen
  */
-#include <linux/config.h>
 
 #ifndef __ASM_ISADEP_H
 #define __ASM_ISADEP_H
 
-#if defined(CONFIG_CPU_R3000)
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
 /*
  * R2000 or R3000
  */

include/asm-mips/processor.h +54 ~~-195~~

315 lines not on this page · raw message

include/asm-mips/ptrace.h +34 ~~-33~~

114 lines not on this page · raw message

include/asm-mips/reg.h +97 ~~-37~~

153 lines not on this page · raw message

include/asm-mips/regdef.h +87 ~~-39~~

139 lines not on this page · raw message

include/asm-mips/types.h +26 -4

index 707cbf4..f49a217 100644
@@ -1,5 +1,4 @@
-/* $Id: types.h,v 1.3 1999/08/18 23:37:50 ralf Exp $
- *
+/*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.

@@ -10,6 +9,8 @@
 #ifndef _ASM_TYPES_H
 #define _ASM_TYPES_H
 
+#ifndef __ASSEMBLY__
+
 typedef unsigned short umode_t;
 
 /*

@@ -40,11 +41,17 @@ __extension__ typedef unsigned long long __u64;
 
 #endif
 
+#endif /* __ASSEMBLY__ */
+
 /*
  * These aren't exported outside the kernel to avoid name space clashes
  */
 #ifdef __KERNEL__
 
+#define BITS_PER_LONG _MIPS_SZLONG
+
+#ifndef __ASSEMBLY__
+
 typedef __signed char s8;
 typedef unsigned char u8;

@@ -68,9 +75,24 @@ typedef unsigned long long u64;
 
 #endif
 
-#define BITS_PER_LONG _MIPS_SZLONG
+#if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \
+    || defined(CONFIG_64BIT)
+typedef u64 dma_addr_t;
+#else
+typedef u32 dma_addr_t;
+#endif
+typedef u64 dma64_addr_t;
+
+/*
+ * Don't use phys_t.  You've been warned.
+ */
+#ifdef CONFIG_64BIT_PHYS_ADDR
+typedef unsigned long long phys_t;
+#else
+typedef unsigned long phys_t;
+#endif
 
-typedef unsigned long dma_addr_t;
+#endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */