mpc8323erdb: use readable DDR config macros
PATCH 1/3 mpc8323erdb: use readable DDR config macros
Use available shift/mask macros to define DDR configuration.
Signed-off-by Michael Barkowski <[email protected]>
Acked-by Kim Phillips <[email protected]>
--- include/configs/MPC8323ERDB.h | 50 ++++++++++++++++++++++++++++++++++------ 1 files changed, 42 insertions(+), 8 deletions(-)
include/configs/MPC8323ERDB.h +42 -8
@@ -82,17 +82,51 @@/* Manually set up DDR parameters */ #define CFG_DDR_SIZE 64/* MB */ -#define CFG_DDR_CS0_CONFIG 0x80840101 -#define CFG_DDR_TIMING_0 0x00220802 -#define CFG_DDR_TIMING_1 0x3935d322 -#define CFG_DDR_TIMING_2 0x0f9048ca +#define CFG_DDR_CS0_CONFIG ( CSCONFIG_EN \ + | CSCONFIG_AP \ + | 0x00040000 /* TODO */ \ + | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9 ) +/* 0x80840101 */ +#define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ + | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ + | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ + | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ + | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ + | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ + | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ + | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) +/* 0x00220802 */ +#define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ + | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ + | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ + | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ + | (13 << TIMING_CFG1_REFREC_SHIFT ) \ + | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ + | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ + | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) +/* 0x3935d322 */ +#define CFG_DDR_TIMING_2 ( (31 << TIMING_CFG2_CPO_SHIFT ) \ + | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ + | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ + | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ + | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ + | (10 << TIMING_CFG2_FOUR_ACT_SHIFT) ) +/* 0x0f9048ca */ #define CFG_DDR_TIMING_3 0x00000000 -#define CFG_DDR_CLK_CNTL 0x02000000 -#define CFG_DDR_MODE 0x44400232 +#define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 +/* 0x02000000 */ +#define CFG_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \ + | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) +/* 0x44400232 */ #define CFG_DDR_MODE2 0x8000c000 -#define CFG_DDR_INTERVAL 0x03200064 +#define CFG_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \ + | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) +/* 0x03200064 */ #define CFG_DDR_CS0_BNDS 0x00000003 -#define CFG_DDR_SDRAM_CFG 0x43080000 +#define CFG_DDR_SDRAM_CFG ( SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_32_BE ) +/* 0x43080000 */ #define CFG_DDR_SDRAM_CFG2 0x00401000#endif
Signature · 1 line
1.5.3.6
PATCH 1/3 mpc8323erdb: use readable DDR config macros
Quoted 8 lines · On Thu, 20 Mar 2008 13:15:28 -0400 Michael Barkowski…
Use available shift/mask macros to define DDR configuration.
Signed-off-by Michael Barkowski <[email protected]>Acked-by Kim Phillips <[email protected]>--- include/configs/MPC8323ERDB.h | 50 ++++++++++++++++++++++++++++++++++------ 1 files changed, 42 insertions(+), 8 deletions(-)
applied 1-3, thanks.
Kim