CPM1: implement GPIO LIB API
Subsystems (2)
PATCH 1/1 CPM1: implement GPIO LIB API
Implement GPIO LIB API on CPM1 Freescale SoC.
---
This is based on the series starting at http://patchwork.ozlabs.org/linuxppc/patch?id=17299
arch/powerpc/platforms/8xx/Kconfig | 2 + arch/powerpc/sysdev/cpm1.c | 240 +++++++++++++++++++++++++++++++++++- 2 files changed, 241 insertions(+), 1 deletions(-)
arch/powerpc/platforms/8xx/Kconfig +2 -0
@@ -4,6 +4,8 @@ config FADS config CPM1 bool select CPM + select GENERIC_GPIO + select GPIO_LIB choice prompt "8xx Machine Type"
arch/powerpc/sysdev/cpm1.c +239 -1
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Signature · 1 line
1.5.4.4
arch/powerpc/platforms/8xx/Kconfig config FADS · line 8
Quoted 10 lines · Jochen Friedrich
arch/powerpc/platforms/8xx/Kconfig +2
-0@@ -4,6 +4,8 @@ config FADS config CPM1 bool select CPM + select GENERIC_GPIO + select GPIO_LIB
Shouldn't this depend on the user enabling GPIO support? Some 8xx boards are very memory-constrained, so we don't want to be making the kernel even bigger than it already is unless it's actually needed.
-Scott
Hi Scott,
Quoted 6 lines
Quoted 6 lines
arch/powerpc/platforms/8xx/Kconfig +0
-0@@ -4,6 +4,8 @@ config FADS config CPM1
Quoted 8 lines
arch/powerpc/platforms/8xx/Kconfig config FADS · line 8
Quoted 4 lines
arch/powerpc/platforms/8xx/Kconfig +2
-0bool select CPM + select GENERIC_GPIO + select GPIO_LIBShouldn't this depend on the user enabling GPIO support? Some 8xx boards are very memory-constrained, so we don't want to be making the kernel even bigger than it already is unless it's actually needed.
Are you more comfortable with this?
Implement GPIO LIB API on CPM1 Freescale SoC.
--- arch/powerpc/platforms/8xx/Kconfig | 10 ++ arch/powerpc/sysdev/cpm1.c | 246 +++++++++++++++++++++++++++++++++++- 2 files changed, 255 insertions(+), 1 deletions(-)
arch/powerpc/platforms/8xx/Kconfig +10 -0
@@ -109,6 +109,16 @@ config 8xx_COPYBACK If in doubt, say Y here. +config 8xx_GPIO + bool "GPIO API Support" + select GENERIC_GPIO + select HAVE_GPIO_LIB + help + Saying Y here will cause the ports on an MPC8xx processor to be used + with the GPIO API. If you say N here, the kernel needs less memory. + + If in doubt, say Y here. + config 8xx_CPU6 bool "CPU6 Silicon Errata (860 Pre Rev. C)" help
arch/powerpc/sysdev/cpm1.c +245 -1
267 lines not on this page · raw message
Signature · 1 line
1.5.4.4
Quoted 14 lines · Jochen Friedrich
Hi Scott,
Quoted 11 lines
arch/powerpc/platforms/8xx/Kconfig config FADS · line 8
Quoted 10 lines
arch/powerpc/platforms/8xx/Kconfig +2
-0@@ -4,6 +4,8 @@ config FADS config CPM1 bool select CPM + select GENERIC_GPIO + select GPIO_LIBShouldn't this depend on the user enabling GPIO support? Some 8xx boards are very memory-constrained, so we don't want to be making the kernel even bigger than it already is unless it's actually needed.
Quoted 1 line
Are you more comfortable with this?
Sure.
-Scott
Hi Jochen,
Quoted 6 lines · Jochen Friedrich
Implement GPIO LIB API on CPM1 Freescale SoC.
Signed-off-by Jochen Friedrich <[email protected]>---
This is based on the series starting at
http://patchwork.ozlabs.org/linuxppc/patch?id=17299
Quoted 3 lines
arch/powerpc/platforms/8xx/Kconfig | 2 + arch/powerpc/sysdev/cpm1.c | 240
+++++++++++++++++++++++++++++++++++-
Quoted 2 lines
2 files changed, 241 insertions(+), 1 deletions(-)
[snip]
Quoted 20 lines
arch/powerpc/sysdev/cpm1.c +3
-0@@ -30,11 +30,14 @@#include <linux/interrupt.h> #include <linux/irq.h> #include <linux/module.h> +#include <linux/spinlock.h> +#include <linux/of_gpio.h> #include <asm/page.h> #include <asm/pgtable.h> #include <asm/8xx_immap.h> #include <asm/cpm1.h> #include <asm/io.h> +#include <asm/gpio.h> #include <asm/tlbflush.h> #include <asm/rheap.h> #include <asm/prom.h>
arch/powerpc/sysdev/cpm1.c struct cpm_ioport16 { · line 410
Quoted 6 lines
arch/powerpc/sysdev/cpm1.c +1
-1@@ -403,7 +406,7 @@ struct cpm_ioport16 { };struct cpm_ioport32 { -__be32 dir, par, sor; +__be32 dir, par, sor, dat; };
I haven't checked all CPM1-based parts, but for the MPC855 family this doesn't look right. The MPC855 has two 32-bit ports, port B and port E. Registers for port B are dir, par, odr and dat, and registers for port E are dir, par, sor, odr and dat.
Are you working on a similar patch for the CPM2 ? CPM2 I/O ports are 32 bit wide and their registers are layed out like for port E on the MPC855. It should thus be possible to share code between CPM1 and CPM2.
Best regards,
Signature · 9 lines
Laurent Pinchart CSE Semaphore Belgium Chaussée de Bruxelles, 732A B-1410 Waterloo Belgium T +32 (2) 387 42 59 F +32 (2) 387 42 75
Hi Laurent,
Quoted 4 lines
I haven't checked all CPM1-based parts, but for the MPC855 family this doesn't look right. The MPC855 has two 32-bit ports, port B and port E. Registers for port B are dir, par, odr and dat, and registers for port E are dir, par, sor, odr and dat.
You probably mean MPC885. Thanks for catching this, the 32bit registers really are a mess on CPM1 platforms.
Quoted 3 lines
Are you working on a similar patch for the CPM2 ? CPM2 I/O ports are 32 bit wide and their registers are layed out like for port E on the MPC855. It should thus be possible to share code between CPM1 and CPM2.
Yes, some common port setup code could probably be moved to cpm.c.
Thanks,
Jochen