Add Vitesse 8601 support to TSEC driver

PATCH New Tor Krill 5 participants 17 messages Mar 28, 2008 – Apr 24, 2008 Network drivers

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Tor Krill

author

2008-03-28 14:29 UTC #0 lore raw

PATCH 1/1 Add Vitesse 8601 support to TSEC driver

Add phy_info for Vitesse VSC8601.
Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing compensation.

Signed-off-by Tor Krill <[email protected]>

---
 drivers/net/tsec.c |   30 ++++++++++++++++++++++++++++++
 drivers/net/tsec.h |    5 +++++
 2 files changed, 35 insertions(+), 0 deletions(-)

drivers/net/tsec.c +30 -0

index 431a8d2..9d22aa3 100644
@@ -1267,6 +1267,35 @@ struct phy_info phy_info_VSC8244 = {
 			   },
 };
 
+struct phy_info phy_info_VSC8601 = {
+		0x00007042,
+		"Vitesse VSC8601",
+		4,
+		(struct phy_cmd[]){     /* config */
+				/* Override PHY config settings */
+				/* Configure some basic stuff */
+				{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+#ifdef CFG_VSC8601_SKEWFIX
+				{MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
+#endif
+				{miim_end,}
+				 },
+		(struct phy_cmd[]){     /* startup */
+				/* Read the Status (2x to make sure link is right) */
+				{MIIM_STATUS, miim_read, NULL},
+				/* Auto-negotiate */
+				{MIIM_STATUS, miim_read, &mii_parse_sr},
+				/* Read the status */
+				{MIIM_VSC8244_AUX_CONSTAT, miim_read,
+						&mii_parse_vsc8244},
+				{miim_end,}
+				},
+		(struct phy_cmd[]){     /* shutdown */
+				{miim_end,}
+				},
+};
+
+
 struct phy_info phy_info_dm9161 = {
 	0x0181b88,
 	"Davicom DM9161E",

@@ -1462,6 +1491,7 @@ struct phy_info *phy_info[] = {
 	&phy_info_dm9161,
 	&phy_info_lxt971,
 	&phy_info_VSC8244,
+	&phy_info_VSC8601,
 	&phy_info_dp83865,
 	&phy_info_rtl8211b,
 	&phy_info_generic,

drivers/net/tsec.h +5 -0

index d4dc15a..cfa7d1a 100644
@@ -159,6 +159,11 @@
 #define MIIM_VSC8244_LED_CON            0x1b
 #define MIIM_VSC8244_LEDCON_INIT        0xF011
 
+/* Entry for Vitesse VSC8601 regs starts here (Not complete) */
+/* Vitesse VSC8601 Extended PHY Control Register 1 */
+#define MIIM_VSC8601_EPHY_CON			0x17
+#define MIIM_VSC8601_EPHY_CON_INIT_SKEW	0x1120
+
 /* 88E1011 PHY Status Register */
 #define MIIM_88E1011_PHY_STATUS         0x11
 #define MIIM_88E1011_PHYSTAT_SPEED      0xc000

Signature · 1 line

1.5.4.4

André Schwarz

2008-03-28 21:33 UTC #1 lore raw

PATCH 1/1 Add Vitesse 8601 support to TSEC driver

Tor,

what a pitty - I've been working on this for 2 days now.
I did not implement the skew since I configured it by hardware strapping.

Very interesting PHY : low power, self calibrating ...... and cheap :-)

Is yor PHY already up and running including data ?

regards,
Andr? Schwarz
Matrix Vision

Quoted 64 lines · Tor Krill

Add phy_info for Vitesse VSC8601.
Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing compensation.

Signed-off-by Tor Krill <[email protected]>

---
 drivers/net/tsec.c |   30 ++++++++++++++++++++++++++++++
 drivers/net/tsec.h |    5 +++++
 2 files changed, 35 insertions(+), 0 deletions(-)

drivers/net/tsec.c +30 -0

index 431a8d2..9d22aa3 100644
@@ -1267,6 +1267,35 @@ struct phy_info phy_info_VSC8244 = {
 			   },
 };
 
+struct phy_info phy_info_VSC8601 = {
+		0x00007042,
+		"Vitesse VSC8601",
+		4,
+		(struct phy_cmd[]){     /* config */
+				/* Override PHY config settings */
+				/* Configure some basic stuff */
+				{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+#ifdef CFG_VSC8601_SKEWFIX
+				{MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
+#endif
+				{miim_end,}
+				 },
+		(struct phy_cmd[]){     /* startup */
+				/* Read the Status (2x to make sure link is right) */
+				{MIIM_STATUS, miim_read, NULL},
+				/* Auto-negotiate */
+				{MIIM_STATUS, miim_read, &mii_parse_sr},
+				/* Read the status */
+				{MIIM_VSC8244_AUX_CONSTAT, miim_read,
+						&mii_parse_vsc8244},
+				{miim_end,}
+				},
+		(struct phy_cmd[]){     /* shutdown */
+				{miim_end,}
+				},
+};
+
+
 struct phy_info phy_info_dm9161 = {
 	0x0181b88,
 	"Davicom DM9161E",

@@ -1462,6 +1491,7 @@ struct phy_info *phy_info[] = {
 	&phy_info_dm9161,
 	&phy_info_lxt971,
 	&phy_info_VSC8244,
+	&phy_info_VSC8601,
 	&phy_info_dp83865,
 	&phy_info_rtl8211b,
 	&phy_info_generic,

drivers/net/tsec.h +0 -0

index d4dc15a..cfa7d1a 100644
@@ -159,6 +159,11 @@
 #define MIIM_VSC8244_LED_CON            0x1b

drivers/net/tsec.h line 169

Quoted 10 lines

drivers/net/tsec.h +5 -0

 #define MIIM_VSC8244_LEDCON_INIT        0xF011
 
+/* Entry for Vitesse VSC8601 regs starts here (Not complete) */
+/* Vitesse VSC8601 Extended PHY Control Register 1 */
+#define MIIM_VSC8601_EPHY_CON			0x17
+#define MIIM_VSC8601_EPHY_CON_INIT_SKEW	0x1120
+
 /* 88E1011 PHY Status Register */
 #define MIIM_88E1011_PHY_STATUS         0x11
 #define MIIM_88E1011_PHYSTAT_SPEED      0xc000

MATRIX VISION GmbH, Talstra?e 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Gesch?ftsf?hrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner

Ben Warren

2008-03-31 14:04 UTC #3 lore raw

PATCH 1/1 Add Vitesse 8601 support to TSEC driver

Quoted 5 lines · Tor Krill

Ben regarding your call for network related patches. Im not sure if i should have sent this one to you? Got no reactions on it.
/Tor

No problem. If either Kim Phillips or Andy Fleming blesses it, I'll pull it in today.

regards,
Ben

Ben Warren

2008-03-31 14:01 UTC #4 lore raw

PATCH 1/1 Add Vitesse 8601 support to TSEC driver

In reply to Tor Krill

Quoted 5 lines · Tor Krill

Add phy_info for Vitesse VSC8601.
Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing compensation.
Signed-off-by Tor Krill <[email protected]>

Acked-by Ben Warren <[email protected]>

Quoted 70 lines

---
 drivers/net/tsec.c |   30 ++++++++++++++++++++++++++++++
 drivers/net/tsec.h |    5 +++++
 2 files changed, 35 insertions(+), 0 deletions(-)

drivers/net/tsec.c +30 -0

index 431a8d2..9d22aa3 100644
@@ -1267,6 +1267,35 @@ struct phy_info phy_info_VSC8244 = {
 			   },
 };
 
+struct phy_info phy_info_VSC8601 = {
+		0x00007042,
+		"Vitesse VSC8601",
+		4,
+		(struct phy_cmd[]){     /* config */
+				/* Override PHY config settings */
+				/* Configure some basic stuff */
+				{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+#ifdef CFG_VSC8601_SKEWFIX
+				{MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
+#endif
+				{miim_end,}
+				 },
+		(struct phy_cmd[]){     /* startup */
+				/* Read the Status (2x to make sure link is right) */
+				{MIIM_STATUS, miim_read, NULL},
+				/* Auto-negotiate */
+				{MIIM_STATUS, miim_read, &mii_parse_sr},
+				/* Read the status */
+				{MIIM_VSC8244_AUX_CONSTAT, miim_read,
+						&mii_parse_vsc8244},
+				{miim_end,}
+				},
+		(struct phy_cmd[]){     /* shutdown */
+				{miim_end,}
+				},
+};
+
+
 struct phy_info phy_info_dm9161 = {
 	0x0181b88,
 	"Davicom DM9161E",

@@ -1462,6 +1491,7 @@ struct phy_info *phy_info[] = {
 	&phy_info_dm9161,
 	&phy_info_lxt971,
 	&phy_info_VSC8244,
+	&phy_info_VSC8601,
 	&phy_info_dp83865,
 	&phy_info_rtl8211b,
 	&phy_info_generic,

drivers/net/tsec.h +5 -0

index d4dc15a..cfa7d1a 100644
@@ -159,6 +159,11 @@
 #define MIIM_VSC8244_LED_CON            0x1b
 #define MIIM_VSC8244_LEDCON_INIT        0xF011
 
+/* Entry for Vitesse VSC8601 regs starts here (Not complete) */
+/* Vitesse VSC8601 Extended PHY Control Register 1 */
+#define MIIM_VSC8601_EPHY_CON			0x17
+#define MIIM_VSC8601_EPHY_CON_INIT_SKEW	0x1120
+
 /* 88E1011 PHY Status Register */
 #define MIIM_88E1011_PHY_STATUS         0x11
 #define MIIM_88E1011_PHYSTAT_SPEED      0xc000

Kim Phillips

2008-03-31 18:18 UTC #5 lore raw

PATCH 1/1 Add Vitesse 8601 support to TSEC driver

Quoted 7 lines · On Mon, 31 Mar 2008 10:01:34 -0400 Ben Warren <[email protected]> wrote:

Quoted 5 lines · Tor Krill
Add phy_info for Vitesse VSC8601.
Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing compensation.
Signed-off-by Tor Krill <[email protected]>
Acked-by Ben Warren <[email protected]>

I don't have a Vitesse 8601, so technically I can't ack it, but I can:

Reviewed-by Kim Phillips <[email protected]>

minor nit: it would be nice if the following:

Quoted 3 lines

drivers/net/tsec.c struct phy_info phy_info_VSC8244 = { · line 1280
Quoted 3 lines
drivers/net/tsec.c +3 -0
+#ifdef CFG_VSC8601_SKEWFIX
+				{MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
+#endif

were made to have spaces after commas, and flow onto a separate line so as to not be a 96 char line..

Kim

Andre Schwarz

2008-04-01 11:38 UTC #6 lore raw

PATCH 1/1 Add Vitesse 8601 support to TSEC driver

Kim,

would it help if we donate one or two boards to the custodians ? Or do you have no time at all for specific testing ?

After bring-up + validation I could offer 1-2 MPC8343B based boards with 2x VSC8601.
The system also has a miniPCI Slot, USB-A and 512MB DDR-II Micron memory.

Please let me know if you're interested.

regards,
Andre Schwarz
Matrix Vision

Quoted 32 lines · Kim Phillips

Quoted 10 lines · On Mon, 31 Mar 2008 10:01:34 -0400 Ben Warren <[email protected]> wrote:
Quoted 6 lines · Tor Krill
Add phy_info for Vitesse VSC8601.
Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing compensation.
Signed-off-by Tor Krill <[email protected]>
Acked-by Ben Warren <[email protected]>
I don't have a Vitesse 8601, so technically I can't ack it, but I can:
Reviewed-by Kim Phillips <[email protected]>
minor nit: it would be nice if the following:
Quoted 4 lines
drivers/net/tsec.c struct phy_info phy_info_VSC8244 = { · line 1280
Quoted 4 lines
drivers/net/tsec.c +3 -0
+#ifdef CFG_VSC8601_SKEWFIX
+				{MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
+#endif
were made to have spaces after commas, and flow onto a separate line so as to not be a 96 char line..
Kim

Quoted 10 lines

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Andre Schwarz

2008-04-17 18:32 UTC #7 lore raw

PATCH 1/1 Add Vitesse 8601 support to TSEC driver

In reply to Kim Phillips

Tor,

after all my VSC8601 is up and running on MPC8343 :-)

I'm sorry to say that I don't find this patch ok after going through the manuals :

Register 0x17 is a very coarse setting. If the capabilities of the PHY should be taken into account and be configurable we should use the skew control in extended register 0x1c. This should be definable - CFG_VSC8601_SKEWFIX simply applies maximum skew ...

After all changing the bits in register 0x17 _require_ a soft reset by asserting bit 15 in register 0 before they are going to work.

Obviously this patch has no effect at all.
Do you reset the PHY manually after this configuration ?

This PHY definitely needs a proper setup function since there are quite interesting registers which need read-modify-write.

What do you think ?

regards,
Andre

Quoted 32 lines · Kim Phillips

Quoted 10 lines · On Mon, 31 Mar 2008 10:01:34 -0400 Ben Warren <[email protected]> wrote:
Quoted 6 lines · Tor Krill
Add phy_info for Vitesse VSC8601.
Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing compensation.
Signed-off-by Tor Krill <[email protected]>
Acked-by Ben Warren <[email protected]>
I don't have a Vitesse 8601, so technically I can't ack it, but I can:
Reviewed-by Kim Phillips <[email protected]>
minor nit: it would be nice if the following:
Quoted 4 lines
drivers/net/tsec.c struct phy_info phy_info_VSC8244 = { · line 1280
Quoted 4 lines
drivers/net/tsec.c +3 -0
+#ifdef CFG_VSC8601_SKEWFIX
+				{MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
+#endif
were made to have spaces after commas, and flow onto a separate line so as to not be a 96 char line..
Kim

Quoted 10 lines

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Tor Krill

author

2008-04-18 08:40 UTC #8 lore raw

PATCH 1/1 Add Vitesse 8601 support to TSEC driver

Hi,

Quoted 11 lines · Andre Schwarz

Tor,
after all my VSC8601 is up and running on MPC8343 :-)
I'm sorry to say that I don't find this patch ok after going through the manuals :
Register 0x17 is a very coarse setting. If the capabilities of the PHY should be taken into account and be configurable we should use the skew control in extended register 0x1c. This should be definable - CFG_VSC8601_SKEWFIX simply applies maximum skew ...

Sure it certainly could have been done in a more configurable way. But you have to decide what you need. For us this was an apropriate level atm that scratched our itch. If we where to expose every setting from the start we still would not have been done ;)

Quoted 5 lines

After all changing the bits in register 0x17 _require_ a soft reset by asserting bit 15 in register 0 before they are going to work.
Obviously this patch has no effect at all.
Do you reset the PHY manually after this configuration ?

According to our datasheet (dated july 2006) only changes of bit 12 in this register needs a software reset to take. We don't reset the phy after changing this and the change obviously work (we have tested and verified that it won't work without the change).

Quoted 4 lines

This PHY definitely needs a proper setup function since there are quite interesting registers which need read-modify-write.
What do you think ?

Perhaps a patch to improve what you find missing?

/Tor

Quoted 49 lines

Quoted 32 lines · Kim Phillips
Quoted 10 lines · On Mon, 31 Mar 2008 10:01:34 -0400 Ben Warren <[email protected]> wrote:
Quoted 6 lines · Tor Krill
Add phy_info for Vitesse VSC8601.
Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing compensation.
Signed-off-by Tor Krill <[email protected]>
Acked-by Ben Warren <[email protected]>
I don't have a Vitesse 8601, so technically I can't ack it, but I can:
Reviewed-by Kim Phillips <[email protected]>
minor nit: it would be nice if the following:
Quoted 4 lines
drivers/net/tsec.c struct phy_info phy_info_VSC8244 = { · line 1280
Quoted 4 lines
drivers/net/tsec.c +3 -0
+#ifdef CFG_VSC8601_SKEWFIX
+				{MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
+#endif
were made to have spaces after commas, and flow onto a separate line so as to not be a 96 char line..
Kim
Quoted 10 lines
-------------------------------------------------------------------------
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just about anything Open Source.
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_______________________________________________
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Andre Schwarz

2008-04-24 14:23 UTC #9 lore raw

PATCH 1/1 Add Vitesse 8601 support to TSEC driver

Tor,

at last I could solve my "strange" behaviour.

Actually the PHY definitely uses both 2 bit definitions of Rx and Tx Skew at "RGMII Skew Control Reg" 0x1c - which are set up by eeprom or strapping.

Due to noise or strapping resistor mismatch these setting are not always like
I want them to be.

Setting bit 8 in "Extended PHY Control 1" @ 0x17 activates the delay lines. Obviously your Skew values did match.

I'll send a patch to configure the delay.

Cheers,
Andre

Quoted 40 lines · Tor Krill

Hi,
Quoted 4 lines · Andre Schwarz
Tor,
after all my VSC8601 is up and running on MPC8343 :-)
Quoted 8 lines
I'm sorry to say that I don't find this patch ok after going through the manuals :
Register 0x17 is a very coarse setting. If the capabilities of the PHY should be taken into account and be configurable we should use the skew control in extended register 0x1c. This should be definable - CFG_VSC8601_SKEWFIX simply applies maximum skew ...
Sure it certainly could have been done in a more configurable way. But you have to decide what you need. For us this was an apropriate level atm that scratched our itch. If we where to expose every setting from the start we still would not have been done ;)
Quoted 6 lines
After all changing the bits in register 0x17 _require_ a soft reset by asserting bit 15 in register 0 before they are going to work.
Obviously this patch has no effect at all.
Do you reset the PHY manually after this configuration ?
According to our datasheet (dated july 2006) only changes of bit 12 in this register needs a software reset to take. We don't reset the phy after changing this and the change obviously work (we have tested and verified that it won't work without the change).
Quoted 3 lines
This PHY definitely needs a proper setup function since there are quite interesting registers which need read-modify-write.

Quoted 61 lines

Quoted 2 lines
What do you think ?
Perhaps a patch to improve what you find missing?
/Tor
Quoted 53 lines
Quoted 36 lines · Kim Phillips
Quoted 13 lines · On Mon, 31 Mar 2008 10:01:34 -0400 Ben Warren <[email protected]> wrote:
Quoted 7 lines · Tor Krill
Add phy_info for Vitesse VSC8601.
Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing compensation.
Signed-off-by Tor Krill <[email protected]>
Acked-by Ben Warren <[email protected]>
I don't have a Vitesse 8601, so technically I can't ack it, but I can:
Reviewed-by Kim Phillips <[email protected]>
minor nit: it would be nice if the following:
Quoted 5 lines
drivers/net/tsec.c struct phy_info phy_info_VSC8244 = { · line 1280
Quoted 5 lines
drivers/net/tsec.c +3 -0
+#ifdef CFG_VSC8601_SKEWFIX
+				{MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
+#endif
were made to have spaces after commas, and flow onto a separate line so as to not be a 96 char line..
Kim
Quoted 11 lines
-------------------------------------------------------------------------
Check out the new SourceForge.net Marketplace.
It's the best place to buy or sell services for
just about anything Open Source.
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_______________________________________________
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U-Boot-Users at lists.sourceforge.net
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MATRIX VISION GmbH, Talstra??e 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Gesch??ftsf??hrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner

MATRIX VISION GmbH, Talstra?e 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Gesch?ftsf?hrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner

Andre Schwarz

2008-04-01 13:33 UTC #10 lore raw

PATCH 1/1 Add Vitesse 8601 support to TSEC driver

In reply to Tor Krill

Tor,

after investigating the tsec code I'm wondering how your PHY works in RGMII mode ...

I think that there are some things missing, e.g. taking RGMII into account during tsec_init.

/* Init ECNTRL */

        regs->ecntrl = ECNTRL_INIT_SETTINGS;

This will clear bit 27 which indicates RGMII as set up by the HRCW.

I would expect something like

        if ( priv->flags & TSEC_REDUCED )
                regs->ecntrl |= ECNTRL_RPM;

afterwards.

Before I'll start doing double work again : Have you some unposted patches regarding RGMII on TSEC ?

Am I missing something ?

@Kim : Did you ever run a MPC834x with a RGMII PHY ? Is it known to work ?

regards,
Andre

Quoted 64 lines · Tor Krill

Add phy_info for Vitesse VSC8601.
Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing compensation.

Signed-off-by Tor Krill <[email protected]>

---
 drivers/net/tsec.c |   30 ++++++++++++++++++++++++++++++
 drivers/net/tsec.h |    5 +++++
 2 files changed, 35 insertions(+), 0 deletions(-)

drivers/net/tsec.c +30 -0

index 431a8d2..9d22aa3 100644
@@ -1267,6 +1267,35 @@ struct phy_info phy_info_VSC8244 = {
 			   },
 };
 
+struct phy_info phy_info_VSC8601 = {
+		0x00007042,
+		"Vitesse VSC8601",
+		4,
+		(struct phy_cmd[]){     /* config */
+				/* Override PHY config settings */
+				/* Configure some basic stuff */
+				{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+#ifdef CFG_VSC8601_SKEWFIX
+				{MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
+#endif
+				{miim_end,}
+				 },
+		(struct phy_cmd[]){     /* startup */
+				/* Read the Status (2x to make sure link is right) */
+				{MIIM_STATUS, miim_read, NULL},
+				/* Auto-negotiate */
+				{MIIM_STATUS, miim_read, &mii_parse_sr},
+				/* Read the status */
+				{MIIM_VSC8244_AUX_CONSTAT, miim_read,
+						&mii_parse_vsc8244},
+				{miim_end,}
+				},
+		(struct phy_cmd[]){     /* shutdown */
+				{miim_end,}
+				},
+};
+
+
 struct phy_info phy_info_dm9161 = {
 	0x0181b88,
 	"Davicom DM9161E",

@@ -1462,6 +1491,7 @@ struct phy_info *phy_info[] = {
 	&phy_info_dm9161,
 	&phy_info_lxt971,
 	&phy_info_VSC8244,
+	&phy_info_VSC8601,
 	&phy_info_dp83865,
 	&phy_info_rtl8211b,
 	&phy_info_generic,

drivers/net/tsec.h +0 -0

index d4dc15a..cfa7d1a 100644
@@ -159,6 +159,11 @@
 #define MIIM_VSC8244_LED_CON            0x1b

drivers/net/tsec.h line 169

Quoted 10 lines

drivers/net/tsec.h +5 -0

 #define MIIM_VSC8244_LEDCON_INIT        0xF011
 
+/* Entry for Vitesse VSC8601 regs starts here (Not complete) */
+/* Vitesse VSC8601 Extended PHY Control Register 1 */
+#define MIIM_VSC8601_EPHY_CON			0x17
+#define MIIM_VSC8601_EPHY_CON_INIT_SKEW	0x1120
+
 /* 88E1011 PHY Status Register */
 #define MIIM_88E1011_PHY_STATUS         0x11
 #define MIIM_88E1011_PHYSTAT_SPEED      0xc000

MATRIX VISION GmbH, Talstra?e 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Gesch?ftsf?hrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner

Andy Fleming

2008-04-01 13:42 UTC #11 lore raw

PATCH 1/1 Add Vitesse 8601 support to TSEC driver

Quoted 10 lines · Andre Schwarz

Tor,
after investigating the tsec code I'm wondering how your PHY works in RGMII mode ...
I think that there are some things missing, e.g. taking RGMII into account during tsec_init.
/* Init ECNTRL */
        regs->ecntrl = ECNTRL_INIT_SETTINGS;

If you look carefully, you'll notice that ecntrl's RPM bit is read-only. Those bits are configured by POR pin strappings.

You may be more familiar with the UEC, which doesn't automatically detect the link type, but is otherwise fairly similar to the tsec.

Andy

Andre Schwarz

2008-04-01 14:08 UTC #12 lore raw

PATCH 1/1 Add Vitesse 8601 support to TSEC driver

Quoted 11 lines · Andy Fleming

Quoted 8 lines · Andre Schwarz
Tor,
after investigating the tsec code I'm wondering how your PHY works in RGMII mode ...
I think that there are some things missing, e.g. taking RGMII into account during tsec_init.

Quoted 8 lines

Quoted 3 lines
/* Init ECNTRL */
        regs->ecntrl = ECNTRL_INIT_SETTINGS;
If you look carefully, you'll notice that ecntrl's RPM bit is read-only. Those bits are configured by POR pin strappings.

sorry, my documentation (MPC8349EARM rev.1) declares this register read-write.
Of course it will be configured by the HRCW but can be overwritten afterwards.

If this is not true it's a documentation bug.

Quoted 4 lines

You may be more familiar with the UEC, which doesn't automatically detect the link type, but is otherwise fairly similar to the tsec.

What do you mean ?
I'm trying to get two VSC8601 RGMII PHYs running on a MPC8343B ...

Quoted 2 lines

Andy

regards,
Andre

Andy Fleming

2008-04-01 14:25 UTC #13 lore raw

PATCH 1/1 Add Vitesse 8601 support to TSEC driver

Quoted 17 lines · Andre Schwarz

Tor,
after investigating the tsec code I'm wondering how your PHY works in RGMII mode ...
I think that there are some things missing, e.g. taking RGMII into account during tsec_init.
/* Init ECNTRL */
regs->ecntrl = ECNTRL_INIT_SETTINGS;
If you look carefully, you'll notice that ecntrl's RPM bit is
read-only. Those bits are configured by POR pin strappings.

Quoted 6 lines

sorry, my documentation (MPC8349EARM rev.1) declares this register
read-write.
Of course it will be configured by the HRCW but can be overwritten
afterwards.
If this is not true it's a documentation bug.

Thank you for bringing this to my attention. It is almost certainly a bug. If you look at the 8349ERM (rather than the 8349EARM), you'll see that the bits are read-only (except for R100, which tsec.c does modify based on the link type). I will file a bug with the docs people.

Quoted 8 lines

You may be more familiar with the UEC, which doesn't automatically
detect the link type, but is otherwise fairly similar to the tsec.
What do you mean ?
I'm trying to get two VSC8601 RGMII PHYs running on a MPC8343B ...

sorry, I forgot which ethernet controller you were using, and I'm not as familiar with the 83xx family as the 85xx family. Some of our parts have the QUICC Engine, which has an ethernet controller with some similar registers to the TSEC's. I was guessing that was why you thought those bits were writable, rather than a documentation bug, but clearly I was wrong. :)

Andy

Andre Schwarz

2008-04-01 14:35 UTC #14 lore raw

PATCH 1/1 Add Vitesse 8601 support to TSEC driver

Quoted 27 lines · Andy Fleming

Quoted 15 lines · Andre Schwarz
Tor,
after investigating the tsec code I'm wondering how your PHY works in RGMII mode ...
I think that there are some things missing, e.g. taking RGMII into account during tsec_init.
/* Init ECNTRL */
regs->ecntrl = ECNTRL_INIT_SETTINGS;
If you look carefully, you'll notice that ecntrl's RPM bit is
read-only. Those bits are configured by POR pin strappings.
Quoted 7 lines
sorry, my documentation (MPC8349EARM rev.1) declares this register
read-write.
Of course it will be configured by the HRCW but can be overwritten
afterwards.
If this is not true it's a documentation bug.

Quoted 8 lines

Thank you for bringing this to my attention. It is almost certainly a bug. If you look at the 8349ERM (rather than the 8349EARM), you'll see that the bits are read-only (except for R100, which tsec.c does modify based on the link type). I will file a bug with the docs people.

I've x-checked and printed the register after init.
You're right - it's read only and the RPM bit is set.
But the ECNTL register description @ 15.5.3.1.4 says "read/write" to all bits ...

Quoted 8 lines

Quoted 7 lines
You may be more familiar with the UEC, which doesn't automatically
detect the link type, but is otherwise fairly similar to the tsec.
What do you mean ?
I'm trying to get two VSC8601 RGMII PHYs running on a MPC8343B ...

Quoted 8 lines

sorry, I forgot which ethernet controller you were using, and I'm not as familiar with the 83xx family as the 85xx family. Some of our parts have the QUICC Engine, which has an ethernet controller with some similar registers to the TSEC's. I was guessing that was why you thought those bits were writable, rather than a documentation bug, but clearly I was wrong. :)

no problem.

Andre

Quoted 4 lines

Andy
Andy

Kim Phillips

2008-04-01 16:12 UTC #15 lore raw

PATCH 1/1 Add Vitesse 8601 support to TSEC driver

In reply to Andre Schwarz

Quoted 4 lines · On Tue, 01 Apr 2008 15:33:10 +0200 Andre Schwarz…

I would expect something like

        if ( priv->flags & TSEC_REDUCED )
                regs->ecntrl |= ECNTRL_RPM;

yeah, that register should be r/o..

Quoted 1 line

@Kim : Did you ever run a MPC834x with a RGMII PHY ? Is it known to work ?

834x? I haven't, but I also haven't a reason why it would not work :)

Kim

André Schwarz

2008-04-02 08:01 UTC #16 lore raw

PATCH 1/1 Add Vitesse 8601 support to TSEC driver

Quoted 10 lines · Kim Phillips

Quoted 4 lines · On Tue, 01 Apr 2008 15:33:10 +0200 Andre Schwarz…
I would expect something like
        if ( priv->flags & TSEC_REDUCED )
                regs->ecntrl |= ECNTRL_RPM;
yeah, that register should be r/o..

you're right.
The register actually _is_ r/o. But datasheet says "r/w" ...

Quoted 3 lines

Quoted 1 line
@Kim : Did you ever run a MPC834x with a RGMII PHY ? Is it known to work ?
834x? I haven't, but I also haven't a reason why it would not work :)

ok - I'll have a closer look into the hardware.

Quoted 2 lines

Kim

thanks,
Andr?

MATRIX VISION GmbH, Talstra?e 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Gesch?ftsf?hrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner