qemu gdbstub.c linux-user/main.c linux-user/sig...

Qemu-devel New Thiemo Seufer 2 participants 2 messages Feb 12, 2008 – Apr 20, 2008

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Thiemo Seufer

author

2008-02-12 21:01 UTC #0 lore raw

CVSROOT: /sources/qemu
Module name: qemu
Changes by: Thiemo Seufer <ths> 08/02/12 21:01:26

Modified files:
. : gdbstub.c
linux-user : main.c signal.c syscall.c
linux-user/mips: target_signal.h
linux-user/mips64: target_signal.h
linux-user/mipsn32: target_signal.h
target-mips : cpu.h op.c op_helper.c op_template.c
translate.c

Log message:
Make MIPS MT implementation more cache friendly.

Stefan Weil

2008-04-20 10:32 UTC #1 lore raw

PATCH 1/1 Change MIPS register access

Quoted 13 lines · Thiemo Seufer

CVSROOT: /sources/qemu
Module name: qemu
Changes by: Thiemo Seufer <ths> 08/02/12 21:01:26
Modified files:
. : gdbstub.c
linux-user : main.c signal.c syscall.c linux-user/mips: target_signal.h linux-user/mips64: target_signal.h linux-user/mipsn32: target_signal.h target-mips : cpu.h op.c op_helper.c op_template.c translate.c

Quoted 2 lines

Log message:
Make MIPS MT implementation more cache friendly.

Appendix mips.patch tries to complete Thiemo's changes. Please check it and add it to QEMU trunk if it is correct.

I don't have a test scenario which could test the effects of the patch.

Regards
Stefan Weil

op.c +8 -8

Index: target-mips/op.c
===================================================================
@@ -2300,7 +2300,7 @@
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->gpr[PARAM1][other_tc];
+    T0 = env->gpr[other_tc][PARAM1];
     FORCE_RET();
 }

@@ -2308,7 +2308,7 @@
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->LO[PARAM1][other_tc];
+    T0 = env->LO[other_tc][PARAM1];
     FORCE_RET();
 }

@@ -2316,7 +2316,7 @@
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->HI[PARAM1][other_tc];
+    T0 = env->HI[other_tc][PARAM1];
     FORCE_RET();
 }

@@ -2324,7 +2324,7 @@
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->ACX[PARAM1][other_tc];
+    T0 = env->ACX[other_tc][PARAM1];
     FORCE_RET();
 }

@@ -2340,7 +2340,7 @@
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->gpr[PARAM1][other_tc];
+    T0 = env->gpr[other_tc][PARAM1];
     FORCE_RET();
 }

@@ -2348,7 +2348,7 @@
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->LO[PARAM1][other_tc];
+    T0 = env->LO[other_tc][PARAM1];
     FORCE_RET();
 }

@@ -2356,7 +2356,7 @@
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->HI[PARAM1][other_tc];
+    T0 = env->HI[other_tc][PARAM1];
     FORCE_RET();
 }

@@ -2364,7 +2364,7 @@
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->ACX[PARAM1][other_tc];
+    T0 = env->ACX[other_tc][PARAM1];
     FORCE_RET();
 }

op_template.c +2 -2

Index: target-mips/op_template.c
===================================================================
@@ -52,13 +52,13 @@
 
 void glue(op_load_srsgpr_T0_gpr, REG) (void)
 {
-    T0 = env->gpr[REG][(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf];
+    T0 = env->gpr[(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf][REG];
     FORCE_RET();
 }
 
 void glue(op_store_T0_srsgpr_gpr, REG) (void)
 {
-    env->gpr[REG][(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf] = T0;
+    env->gpr[(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf][REG] = T0;
     FORCE_RET();
 }
 #endif