Add support for AT91SAM9263EK (again)
Subsystems (4)
PATCH 1/1 Add support for AT91SAM9263EK (again)
Apologies for the previous patch, forgot to add the new files to it. No wonder it seemed so short.
Here it is again
---
Makefile +0 -0
@@ -2311,6 +2311,9 @@ at91rm9200dk_config : unconfig
at91sam9260ek_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9260ek atmel at91sam9
+at91sam9263ek_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9263ek atmel at91sam9
+cmc_pu2_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
(quoted diff) +0 -0
b/board/atmel/at91sam9263ek/Makefile
new file mode 100644
index 0000000..72e8faa
board/atmel/at91sam9263ek/Makefile new file +52 -0
52 lines not on this page · raw message
(quoted diff) +0 -0
b/board/atmel/at91sam9263ek/at91sam9263ek.c
new file mode 100644
index 0000000..316cdea
board/atmel/at91sam9263ek/at91sam9263ek.c new file +39 -0
@@ -0,0 +1,239 @@ +/* +* (C) Copyright 2007-2008 +* Stelian Pop <stelian.pop <at> leadtechdesign.com> +* Lead Tech Design <www.leadtechdesign.com> +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <common.h> +#include <asm/arch/at91sam9263.h> +#include <asm/arch/at91sam9263_matrix.h> +#include <asm/arch/at91sam926x_mc.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> +#if defined(CONFIG_RESET_PHY_R ) && defined(CONFIG_MACB ) +#include <net.h> +#endif + +DECLARE_GLOBAL_DATA_PTR ; + +/*
------------------------------------------------------------------------- */ +/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static void at91sam9263ek_serial_hw_init(void)
+{
+#ifdef CONFIG_USART0
+ at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0); +#endif + +#ifdef CONFIG_USART1 + at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1); +#endif + +#ifdef CONFIG_USART2 + at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */ + at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2); +#endif + +#ifdef CONFIG_USART3 /* DBGU */ + at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */ + at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
+#endif
+}
+
+#ifdef CONFIG_CMD_NAND
+static void at91sam9263ek_nand_hw_init(void)
+{
+ unsigned long csa;
+
+ /* Enable CS3 */ + csa = at91_sys_read(AT91_MATRIX_CSA); + at91_sys_write(AT91_MATRIX_CSA,
+ csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ at91_sys_write(AT91_SMC_SETUP(3),
+ AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(3), + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); + at91_sys_write(AT91_SMC_CYCLE(3), + AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); + at91_sys_write(AT91_SMC_MODE(3), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | + AT91_SMC_DBW_8 | AT91_SMC_TDF_(2));
+
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA);
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOCDE);
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(AT91_PIN_PA22, 1);
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(AT91_PIN_PD15, 1);
+}
+#endif
+
+#ifdef CONFIG_HAS_DATAFLASH
+static void at91sam9263ek_spi_hw_init(void)
+{
+ at91_set_B_periph(AT91_PIN_PA5, 0); /* SPI0_NPCS0 */ + at91_set_B_periph(AT91_PIN_PA3, 0); /* SPI0_NPCS1 */ + + at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ + at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ + at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
+
+ /* Enable clock */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI0);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void at91sam9263ek_macb_hw_init(void)
+{
+ /* Enable clock */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
+
+ /*
+ * Disable pull-up on: + * RXDV (PC25) => PHY normal mode (not Test mode) + * ERX0 (PE25) => PHY ADDR0 + * ERX1 (PE26) => PHY ADDR1 + * ERX2 (PC22) => PHY ADDR2 + * ERX3 (PC23) => PHY ADDR3 + * ECRS (PE22) => PHY ADDR4 => PHYADDR = 0x0 + * + * PHY has internal pull-down + */ + writel(pin_to_mask(AT91_PIN_PC22) | + pin_to_mask(AT91_PIN_PC23) | + pin_to_mask(AT91_PIN_PC25), + pin_to_controller(AT91_PIN_PC0) + PIO_PUDR); + writel(pin_to_mask(AT91_PIN_PE22) | + pin_to_mask(AT91_PIN_PE25) | + pin_to_mask(AT91_PIN_PE26), + pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
+
+ /* Need to reset PHY -> 500ms reset */
+ at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+ AT91_RSTC_ERSTL | (0x0D << 8) |
+ AT91_RSTC_URSTEN);
+
+ at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+
+ /* Wait for end hardware reset */
+ while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
+
+ /* Restore NRST value */
+ at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+ AT91_RSTC_ERSTL | (0x0 << 8) |
+ AT91_RSTC_URSTEN);
+
+ /* Re-enable pull-up */
+ writel(pin_to_mask(AT91_PIN_PC22) |
+ pin_to_mask(AT91_PIN_PC23) | + pin_to_mask(AT91_PIN_PC25), + pin_to_controller(AT91_PIN_PC0) + PIO_PUER); + writel(pin_to_mask(AT91_PIN_PE22) | + pin_to_mask(AT91_PIN_PE25) | + pin_to_mask(AT91_PIN_PE26), + pin_to_controller(AT91_PIN_PE0) + PIO_PUER); + + at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */ + at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */ + at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */ + at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */ + at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */ + at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */ + at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */ + at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */ + at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */ + at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */ + +#ifndef CONFIG_RMII + at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */ + at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */ + at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */ + at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */ + at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */ + at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */ + at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */ + at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
+#endif
+
+}
+#endif
+
+int board_init(void)
+{
+ /* Enable Ctrlc */
+ console_init_f();
+
+ /* arch number of at91sam9263EK-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK; + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ at91sam9263ek_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+ at91sam9263ek_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+ at91sam9263ek_spi_hw_init();
+#endif
+#ifdef CONFIG_MACB
+ at91sam9263ek_macb_hw_init();
+#endif
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_MACB
+ /*
+ * Initialize ethernet HW addr prior to starting Linux, + * needed for nfsroot + */
+ eth_init(gd->bd);
+#endif
+}
+#endif
(quoted diff) +0 -0
b/board/atmel/at91sam9263ek/config.mk
new file mode 100644
index 0000000..ff2cfd1
board/atmel/at91sam9263ek/config.mk new file +1 -0
@@ -0,0 +1 @@ +TEXT_BASE = 0x23f00000
(quoted diff) +0 -0
b/board/atmel/at91sam9263ek/led.c
new file mode 100644
index 0000000..2a71d61
board/atmel/at91sam9263ek/led.c new file +78 -0
78 lines not on this page · raw message
(quoted diff) +0 -0
b/board/atmel/at91sam9263ek/nand.c
new file mode 100644
index 0000000..8c5b4b1
board/atmel/at91sam9263ek/nand.c new file +76 -0
76 lines not on this page · raw message
(quoted diff) +0 -0
b/board/atmel/at91sam9263ek/u-boot.lds
new file mode 100644
index 0000000..05a6d83
board/atmel/at91sam9263ek/u-boot.lds new file +57 -0
57 lines not on this page · raw message
drivers/net/macb.c +0 -0
@@ -417,13 +417,13 @@ static int macb_init(struct eth_device *netdev,
bd_t *bd)
/* choose RMII or MII mode. This depends on the board */
#ifdef CONFIG_RMII
-#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260)
+#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || defined
(CONFIG_AT91SAM9263)
macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
#else
macb_writel(macb, USRIO, 0);
#endif
#else
-#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260)
+#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || defined
(CONFIG_AT91SAM9263)
macb_writel(macb, USRIO, MACB_BIT(CLKEN));
#else
macb_writel(macb, USRIO, MACB_BIT(MII));(quoted diff) +0 -0
b/include/asm-arm/arch-at91sam9/at91sam9263.h
new file mode 100644
index 0000000..f91a357
include/asm-arm/arch-at91sam9/at91sam9263.h new file +107 -0
107 lines not on this page · raw message
address */
+#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size
(128Kb) */
+
+#define AT91SAM9263_SRAM0_BASE 0x00500000 /* Internal SRAM 0 base
address */
+#define AT91SAM9263_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size
(16Kb) */
+#define AT91SAM9263_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base
address */
+#define AT91SAM9263_SRAM1_SIZE SZ_80K /* Internal SRAM 1 size
(80Kb) */
+
+#define AT91SAM9263_UHP_BASE 0x00A00000 /* USB Host controller */
+
+#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base
address */
+#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base
address */
+
+#endif
(quoted diff) +0 -0
b/include/asm-arm/arch-at91sam9/at91sam9263_matrix.h new file mode 100644
index 0000000..c90f01a
include/asm-arm/arch-at91sam9/at91sam9263_matrix.h new file +16 -0
@@ -0,0 +1,88 @@ +/* +* include/asm-arm/arch-at91/at91sam9260_matrix.h +* +* Memory Controllers (MATRIX, EBI) - System peripherals registers. +* Based on AT91SAM9260 datasheet revision B. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +*/ + +#ifndef AT91SAM9260_MATRIX_H +#define AT91SAM9260_MATRIX_H + +#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00)/* Master
Configuration Register 0 */
+#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master
Configuration Register 1 */
+#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master
Configuration Register 2 */
+#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master
Configuration Register 3 */
+#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master
Configuration Register 4 */
+#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master
Configuration Register 5 */
+#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length
Burst Type */
+#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
+
+#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave
Configuration Register 0 */
+#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave
Configuration Register 1 */
+#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave
Configuration Register 2 */
+#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave
Configuration Register 3 */
+#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave
Configuration Register 4 */
+#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum
Number of Allowed Cycles for a Burst */
+#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default
Master Type */
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed
Index of Default Master */
+#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration
Type */
+#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
+#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+
+#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority
Register A for Slave 0 */
+#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority
Register A for Slave 1 */
+#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority
Register A for Slave 2 */
+#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority
Register A for Slave 3 */
+#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority
Register A for Slave 4 */
+#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ +#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ +#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ +#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ +#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ +#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
+
+#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap
Control Register */
+#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for
AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for
AHB Master 1 (ARM926EJ-S Data Master) */
+
+#define AT91_MATRIX_CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select
Assignment Register */
+#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1
Assignment */
+#define AT91_MATRIX_CS1A_SMC (0 << 1)
+#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
+#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3
Assignment */
+#define AT91_MATRIX_CS3A_SMC (0 << 3)
+#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4
Assignment */
+#define AT91_MATRIX_CS4A_SMC (0 << 4) +#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) +#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ +#define AT91_MATRIX_CS5A_SMC (0 << 5) +#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
+#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up
Configuration */
+#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory
voltage selection */
+#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
+#define AT91_MATRIX_EBI1_CSA (AT91_MATRIX + 0x124) /* EBI1 Chip
Select Assignment Register */
+#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select
1 Assignment */
+#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1)
+#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1)
+#define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select
3 Assignment */
+#define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3)
+#define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3)
+#define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus
Pull-up Configuration */
+#define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory
voltage selection */
+#define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16)
+#endif
(quoted diff) +0 -0
b/include/asm-arm/arch-at91sam9/at91sam9263_mc.h
new file mode 100644
index 0000000..041138f
include/asm-arm/arch-at91sam9/at91sam9263_mc.h new file +17 -0
@@ -0,0 +1,140 @@ +/* +* include/asm-arm/arch-at91/at91sam926x_mc.h +* +* Memory Controllers (SMC, SDRAMC) - System peripherals registers. +* Based on AT91SAM9261 datasheet revision D. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +*/ + +#ifndef AT91SAM926x_MC_H +#define AT91SAM926x_MC_H + +/* SDRAM Controller (SDRAMC) registers */ +#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00)/* SDRAM
Controller Mode Register */
+#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
+#define AT91_SDRAMC_MODE_NORMAL 0 +#define AT91_SDRAMC_MODE_NOP 1 +#define AT91_SDRAMC_MODE_PRECHARGE 2 +#define AT91_SDRAMC_MODE_LMR 3 +#define AT91_SDRAMC_MODE_REFRESH 4 +#define AT91_SDRAMC_MODE_EXT_LMR 5 +#define AT91_SDRAMC_MODE_DEEP 6
+
+#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM
Controller Refresh Timer Register */
+#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh
Timer Counter */
+
+#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM
Controller Configuration Register */
+#define AT91_SDRAMC_NC (3 << 0) /* Number of
Column Bits */
+#define AT91_SDRAMC_NC_8 (0 << 0) +#define AT91_SDRAMC_NC_9 (1 << 0) +#define AT91_SDRAMC_NC_10 (2 << 0) +#define AT91_SDRAMC_NC_11 (3 << 0) +#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ +#define AT91_SDRAMC_NR_11 (0 << 2) +#define AT91_SDRAMC_NR_12 (1 << 2) +#define AT91_SDRAMC_NR_13 (2 << 2) +#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ +#define AT91_SDRAMC_NB_2 (0 << 4) +#define AT91_SDRAMC_NB_4 (1 << 4) +#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ +#define AT91_SDRAMC_CAS_1 (1 << 5) +#define AT91_SDRAMC_CAS_2 (2 << 5) +#define AT91_SDRAMC_CAS_3 (3 << 5) +#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */ +#define AT91_SDRAMC_DBW_32 (0 << 7) +#define AT91_SDRAMC_DBW_16 (1 << 7)
+#define AT91_SDRAMC_TWR (0xf << 8) /* Write
Recovery Delay */
+#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle
Delay */
+#define AT91_SDRAMC_TRP (0xf << 16) /* Row
Precharge Delay */
+#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column
Delay */
+#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to
Precharge Delay */
+#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self
Refresh to Active Delay */
+
+#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM
Controller Low Power Register */
+#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power
Configurations */
+#define AT91_SDRAMC_LPCB_DISABLE 0 +#define AT91_SDRAMC_LPCB_SELF_REFRESH 1 +#define AT91_SDRAMC_LPCB_POWER_DOWN 2 +#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
+#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array
Self Refresh */
+#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature
Compensated Self Refresh */
+#define AT91_SDRAMC_DS (3 << 10) /* Drive Strenght */
+#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to
define when Low Power Mode is enabled */
+#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12) +#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) +#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
+
+#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM
Controller Interrupt Enable Register */
+#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM
Controller Interrupt Disable Register */
+#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM
Controller Interrupt Mask Register */
+#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM
Controller Interrupt Status Register */
+#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error
Status */
+
+#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory
Device Register */
+#define AT91_SDRAMC_MD (3 << 0) /* Memory Device
Type */
+#define AT91_SDRAMC_MD_SDRAM 0
+#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
+
+/* Static Memory Controller (SMC) registers */
+#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup
Register for CS n */
+#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup
Length */
+#define AT91_SMC_NWESETUP_(x) ((x) << 0)
+#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS
Setup Length in Write Access */
+#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
+#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD
Setup Length */
+#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
+#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS
Setup Length in Read Access */
+#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
+
+#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse
Register for CS n */
+#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE
Pulse Length */
+#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
+#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS
Pulse Length in Write Access */
+#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
+#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD
Pulse Length */
+#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
+#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS
Pulse Length in Read Access */
+#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
+
+#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle
Register for CS n */
+#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total
Write Cycle Length */
+#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
+#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total
Read Cycle Length */
+#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
+
+#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode
Register for CS n */
+#define AT91_SMC_READMODE (1 << 0) /* Read Mode */ +#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ +#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ +#define AT91_SMC_EXNWMODE_DISABLE (0 << 4) +#define AT91_SMC_EXNWMODE_FROZEN (2 << 4) +#define AT91_SMC_EXNWMODE_READY (3 << 4)
+#define AT91_SMC_BAT (1 << 8) /* Byte Access
Type */
+#define AT91_SMC_BAT_SELECT (0 << 8)
+#define AT91_SMC_BAT_WRITE (1 << 8)
+#define AT91_SMC_DBW (3 << 12) /* Data Bus
Width */
+#define AT91_SMC_DBW_8 (0 << 12) +#define AT91_SMC_DBW_16 (1 << 12) +#define AT91_SMC_DBW_32 (2 << 12)
+#define AT91_SMC_TDF (0xf << 16) /* Data Float
Time. */
+#define AT91_SMC_TDF_(x) ((x) << 16)
+#define AT91_SMC_TDFMODE (1 << 20) /* TDF
Optimization - Enabled */
+#define AT91_SMC_PMEN (1 << 24) /* Page Mode
Enabled */
+#define AT91_SMC_PS (3 << 28) /* Page Size */
+#define AT91_SMC_PS_4 (0 << 28) +#define AT91_SMC_PS_8 (1 << 28) +#define AT91_SMC_PS_16 (2 << 28) +#define AT91_SMC_PS_32 (3 << 28)
+
+#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory
contollers */
+#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /*
Setup Register for CS n */
+#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /*
Pulse Register for CS n */
+#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /*
Cycle Register for CS n */
+#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode
Register for CS n */
+#endif
+
+#endif
(quoted diff) +0 -0
b/include/asm-arm/arch-at91sam9/hardware.h
index 80b334f..4f9f2a8 100644
include/asm-arm/arch-at91sam9/hardware.h +0 -0
@@ -28,6 +28,10 @@
#include <asm/arch/at91sam9261.h>
#elif defined(CONFIG_AT91SAM9263)
#include <asm/arch/at91sam9263.h>
+#define AT91_BASE_EMAC AT91SAM9263_BASE_EMAC
+#define AT91_BASE_SPI AT91SAM9263_BASE_SPI0
+#define AT91_ID_UHP AT91SAM9263_ID_UHP
+#define AT91_PMC_UHP AT91SAM926x_PMC_UHP
#elif defined(CONFIG_AT91SAM9RL)
#include <asm/arch/at91sam9rl.h>
#elif defined(CONFIG_AT91CAP9)
(quoted diff) +0 -0
b/include/configs/at91sam9263ek.h
new file mode 100644
index 0000000..3ae9846
include/configs/at91sam9263ek.h new file +35 -0
@@ -0,0 +1,205 @@ +/* +* (C) Copyright 2007-2008 +* Stelian Pop <stelian.pop <at> leadtechdesign.com> +* Lead Tech Design <www.leadtechdesign.com> +* +* Configuation settings for the AT91SAM9260EK board. +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define CRYSTAL_16_36766MHZ 1 + +#ifdef CRYSTAL_16_36766MHZ + +#define AT91_MAIN_CLOCK 199919000/* from 16.367 MHz crystal
(16367000 / 14 * 171) */
+#define AT91_MASTER_CLOCK (199919000/2) /* peripheral clock
(AT91C_MAIN_CLOCK / 2) */
+
+#endif
+
+#ifdef CRYSTAL_18_432MHZ
+
+#define AT91_MAIN_CLOCK 198656000 /* from 16.367 MHz crystal
(16367000 / 5 * 61) */
+#define AT91_MASTER_CLOCK (198656000/2) /* peripheral clock
(AT91C_MAIN_CLOCK / 2) */
+
+#endif/* ARM asynchronous clock */
+
+#define CFG_HZ 1000000 /* 1us resolution */
+
+#define AT91_SLOW_CLOCK 32768 /* slow clock */
+
+#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
+#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/
+#define CONFIG_AT91SAM9263EK 1 /* on an AT91SAM9263EK Board */
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_ATMEL_USART 1
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+#undef CONFIG_USART2
+#define CONFIG_USART3 1 /* USART 3 is DBGU */
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock0 rw rootfstype=jffs2"
+
+/* #define CONFIG_ENV_OVERWRITE 1 */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE 1
+#define CONFIG_BOOTP_BOOTPATH 1
+#define CONFIG_BOOTP_GATEWAY 1
+#define CONFIG_BOOTP_HOSTNAME 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_NAND 1
+#define CONFIG_CMD_USB 1
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x20000000
+#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
+
+/* DataFlash */
+#define CONFIG_HAS_DATAFLASH 1
+#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
+#define CFG_MAX_DATAFLASH_BANKS 2
+#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ +#define CFG_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* CS1 */
+#define AT91_SPI_CLK 33000000
+#define DATAFLASH_TCSS (0x1a << 16)
+#define DATAFLASH_TCHS (0x1 << 24)
+
+/* NAND flash */
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1
+#define CFG_NAND_BASE 0x40000000
+
+/* NOR flash - no real flash on this board */
+#define CFG_NO_FLASH 1
+
+/* Ethernet */
+#define CONFIG_MACB 1
+#define CONFIG_RMII 1
+#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_RESET_PHY_R 1
+
+/* USB */
+#define CONFIG_USB_OHCI_NEW 1
+#define LITTLEENDIAN 1
+#define CONFIG_DOS_PARTITION 1
+#define CFG_USB_OHCI_CPU_INIT 1
+#define CFG_USB_OHCI_REGS_BASE 0x00a00000 /*AT91SAM9260_UHP_BASE */
+#define CFG_USB_OHCI_SLOT_NAME "at91sam9263"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_STORAGE 1
+
+#define CFG_LOAD_ADDR 0x22000000 /* load address */
+
+#define CFG_MEMTEST_START PHYS_SDRAM
+#define CFG_MEMTEST_END 0x23e00000
+
+#undef CFG_USE_DATAFLASH_CS0
+#undef CFG_USE_DATAFLASH_CS1
+#define CFG_USE_NANDFLASH 1
+
+#ifdef CFG_USE_DATAFLASH_CS0
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CFG_ENV_IS_IN_DATAFLASH 1
+#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
+#define CFG_ENV_OFFSET 0x4200
+#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
+#define CFG_ENV_SIZE 0x4200
+#define CONFIG_BOOTCOMMAND "cp.b 0xC003DE00 0x22000000 0x200040; bootm"
+
+#elif CFG_USE_DATAFLASH_CS1
+
+/* bootstrap + u-boot + env + linux in dataflash on CS1 */
+#define CFG_ENV_IS_IN_DATAFLASH 1
+#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS1 + 0x8400)
+#define CFG_ENV_OFFSET 0x4200
+#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS1 + CFG_ENV_OFFSET)
+#define CFG_ENV_SIZE 0x4200
+#define CONFIG_BOOTCOMMAND "cp.b 0xD003DE00 0x22000000 0x200040; bootm"
+
+#else /* CFG_USE_NANDFLASH */
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CFG_ENV_IS_IN_NAND 1
+#define CFG_ENV_OFFSET 0x60000
+#define CFG_ENV_OFFSET_REDUND 0x80000
+#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000;
bootm"
+
+#endif
+
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
+
+#define CFG_PROMPT "U-Boot> "
+#define CFG_CBSIZE 256
+#define CFG_MAXARGS 16
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+
+#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000)
+#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE (32*1024) /* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
net/eth.c +0 -0
@@ -284,7 +284,7 @@ int eth_initialize(bd_t *bis)
#if defined(CONFIG_FSLDMAFEC)
mcdmafec_initialize(bis);
#endif
-#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260)
+#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) ||
defined(CONFIG_AT91SAM9263)
at91sam9_eth_initialize(bis);#endif
Signature · 21 lines
Regards, Jared Holzman ------------------------------------------------------------------------ *Electronics Design Engineer* *Genesys Electronics Design Pty Ltd* Unit 5, 33 Ryde Rd Pymble NSW, Australia 2073 Direct: +612 9496 8924 Phone: +612 9496 8900 Fax: +612 9496 8999 j.holzman at genesysdesign.com.au <mailto:[email protected]> www.genesysdesign.com.au <http://www.genesysdesign.com.au> ------------------------------------------------------------------------
PATCH 1/1 Add support for AT91SAM9263EK (again)
Quoted 3 lines · In message <[email protected]> you wrote:
Apologies for the previous patch, forgot to add the new files to it. No wonder it seemed so short.
Here it is again
Signed-off-by line missing.
MAINTAINERS entry missing.
Patch corrupted because your mailer line-wrapped it.
Best regards,
Wolfgang Denk
Signature · 5 lines
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de It is surely a great calamity for a human being to have no ob- sessions. - Robert Bly