ARM: EXYNOS: Map SYSRAM through generic SRAM bindings
PATCH v2 1/2 ARM: EXYNOS: Map SYSRAM through generic SRAM bindings
Instead of hardcoding the SYSRAM details for each SoC, pass this information through device tree (DT) and make the code SoC agnostic. Generic SRAM bindings are used for achieving this.
---
This patch is based on linux next (next-20140501) on top of my Kconfig consolidation patch
http://comments.gmane.org/gmane.linux.kernel.samsung-soc/28642
Changes since v1:
Type and presence of sram nodes is SoC/board dependent. V1 mandated the presence of both the nodes and used to return an error if one of the nodes was absent and thus fail the boot altogether. Removed this dependency.
Tested on 4210/4412 Origen, 5250/5420 Arndale and SMDK5420 boards.
--- arch/arm/Kconfig | 1 + arch/arm/boot/dts/exynos4210-universal_c210.dts | 17 ++++++ arch/arm/boot/dts/exynos4210.dtsi | 18 +++++++ arch/arm/boot/dts/exynos4x12.dtsi | 18 +++++++ arch/arm/boot/dts/exynos5250.dtsi | 18 +++++++ arch/arm/boot/dts/exynos5420.dtsi | 18 +++++++ arch/arm/mach-exynos/common.h | 1 + arch/arm/mach-exynos/exynos.c | 64 ----------------------- arch/arm/mach-exynos/firmware.c | 8 ++- arch/arm/mach-exynos/include/mach/map.h | 7 --- arch/arm/mach-exynos/platsmp.c | 33 ++++++++++-- 11 files changed, 128 insertions(+), 75 deletions(-)
arch/arm/Kconfig +1 -0
@@ -855,6 +855,7 @@ config ARCH_EXYNOS select S5P_DEV_MFC select SAMSUNG_DMADEV select SPARSE_IRQ + select SRAM select USE_OF help Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
arch/arm/boot/dts/exynos4210-universal_c210.dts +17 -0
@@ -28,6 +28,23 @@ bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1"; }; + sram at 02020000 { + status = "disabled"; + }; + + sram at 02025000 { + compatible = "mmio-sram"; + reg = <0x02025000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02025000 0x1000>; + + smp-sram at 0 { + compatible = "samsung,exynos4210-sram"; + reg = <0x0 0x1000>; + }; + }; + mct at 10050000 { compatible = "none"; };
arch/arm/boot/dts/exynos4210.dtsi +18 -0
@@ -31,6 +31,24 @@ pinctrl2 = &pinctrl_2; }; + sram at 02020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x20000>; + + smp-sram at 0 { + compatible = "samsung,exynos4210-sram"; + reg = <0x0 0x1000>; + }; + + smp-sram at 1f000 { + compatible = "samsung,exynos4210-sram-ns"; + reg = <0x1f000 0x1000>; + }; + }; + pd_lcd1: lcd1-power-domain at 10023CA0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023CA0 0x20>;
arch/arm/boot/dts/exynos4x12.dtsi +18 -0
@@ -37,6 +37,24 @@ interrupts = <2 2>, <3 2>, <18 2>, <19 2>; }; + sram at 02020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x40000>; + + smp-sram at 0 { + compatible = "samsung,exynos4210-sram"; + reg = <0x0 0x1000>; + }; + + smp-sram at 2f000 { + compatible = "samsung,exynos4210-sram-ns"; + reg = <0x2f000 0x1000>; + }; + }; + pd_isp: isp-power-domain at 10023CA0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023CA0 0x20>;
arch/arm/boot/dts/exynos5250.dtsi +18 -0
@@ -72,6 +72,24 @@ }; }; + sram at 02020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x30000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x30000>; + + smp-sram at 0 { + compatible = "samsung,exynos4210-sram"; + reg = <0x0 0x1000>; + }; + + smp-sram at 2f000 { + compatible = "samsung,exynos4210-sram-ns"; + reg = <0x2f000 0x1000>; + }; + }; + pd_gsc: gsc-power-domain at 10044000 { compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>;
arch/arm/boot/dts/exynos5420.dtsi +18 -0
@@ -110,6 +110,24 @@ }; }; + sram at 02020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x54000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x54000>; + + smp-sram at 0 { + compatible = "samsung,exynos4210-sram"; + reg = <0x0 0x1000>; + }; + + smp-sram at 53000 { + compatible = "samsung,exynos4210-sram-ns"; + reg = <0x53000 0x1000>; + }; + }; + clock: clock-controller at 10010000 { compatible = "samsung,exynos5420-clock"; reg = <0x10010000 0x30000>;
arch/arm/mach-exynos/common.h +1 -0
@@ -18,6 +18,7 @@void mct_init (void __iomem *base,int irq_g0,int irq_l0,int irq_l1);struct map_desc ; +extern void __iomem *sram_ns_base_addr;void exynos_init_io (void );void exynos_restart (enum reboot_mode mode,const char *cmd);void exynos_cpuidle_init (void );
arch/arm/mach-exynos/exynos.c +0 -64
82 lines not on this page · raw message
arch/arm/mach-exynos/firmware.c +7 -1
@@ -18,6 +18,7 @@#include <mach/map.h> +#include "common.h" #include "smc.h" static int exynos_do_idle (void )
@@ -34,7 +35,12 @@ static int exynos_cpu_boot(int cpu)static int exynos_set_cpu_boot_addr (int cpu,unsigned long boot_addr) { -void __iomem *boot_reg =S5P_VA_SYSRAM_NS +0x1c +4 *cpu; +void __iomem *boot_reg; + +if (!sram_ns_base_addr) +return 0 ; + + boot_reg = sram_ns_base_addr +0x1c +4 *cpu;__raw_writel (boot_addr, boot_reg);return 0 ;
arch/arm/mach-exynos/include/mach/map.h +0 -7
@@ -23,13 +23,6 @@#include <plat/map-s5p.h> -#define EXYNOS4_PA_SYSRAM0 0x02025000 -#define EXYNOS4_PA_SYSRAM1 0x02020000 -#define EXYNOS5_PA_SYSRAM 0x02020000 -#define EXYNOS4210_PA_SYSRAM_NS 0x0203F000 -#define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000 -#define EXYNOS5250_PA_SYSRAM_NS 0x0204F000 -#define EXYNOS_PA_CHIPID 0x10000000#define EXYNOS4_PA_SYSCON 0x10010000
arch/arm/mach-exynos/platsmp.c +30 -3
@@ -20,6 +20,7 @@#include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> +#include <linux/of_address.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h>
@@ -33,11 +34,33 @@extern void exynos4_secondary_startup (void ); +static void __iomem *sram_base_addr; +void __iomem *sram_ns_base_addr; + +static void __init exynos_smp_prepare_sram (void ) +{ +struct device_node *node; + + node =of_find_compatible_node (NULL ,NULL ,"samsung,exynos4210-sram" ); +if (node) { + sram_base_addr =of_iomap (node,0 ); +if (!sram_base_addr) +pr_err ("Secondary CPU boot address not found\n" ); + } + + node =of_find_compatible_node (NULL ,NULL ,"samsung,exynos4210-sram-ns" ); +if (node) { + sram_ns_base_addr =of_iomap (node,0 ); +if (!sram_ns_base_addr) +pr_err ("Secondary CPU boot address not found\n" ); + } +} +static inline void __iomem *cpu_boot_reg_base (void ) {if (soc_is_exynos4210 () &&samsung_rev () ==EXYNOS4210_REV_1_1 )return S5P_INFORM5 ; -return S5P_VA_SYSRAM ; +return sram_base_addr; }static inline void __iomem *cpu_boot_reg (int cpu)
@@ -147,7 +170,8 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)* and fall back to boot register if it fails. */ if (call_firmware_op (set_cpu_boot_addr, phys_cpu, boot_addr)) -__raw_writel (boot_addr,cpu_boot_reg (phys_cpu)); +if (cpu_boot_reg_base ()) +__raw_writel (boot_addr,cpu_boot_reg (phys_cpu));call_firmware_op (cpu_boot, phys_cpu);
@@ -205,6 +229,8 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)if (read_cpuid_part_number () ==ARM_CPU_PART_CORTEX_A9 )scu_enable (scu_base_addr ()); +exynos_smp_prepare_sram (); +/* * Write the address of secondary startup into the * system-wide flags register. The boot monitor waits
@@ -222,7 +248,8 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) boot_addr =virt_to_phys (exynos4_secondary_startup);if (call_firmware_op (set_cpu_boot_addr, phys_cpu, boot_addr)) -__raw_writel (boot_addr,cpu_boot_reg (phys_cpu)); +if (cpu_boot_reg_base ()) +__raw_writel (boot_addr,cpu_boot_reg (phys_cpu)); } }
Signature · 1 line
1.7.9.5
PATCH v2 2/2 Documentation: DT: Exynos: Bind SRAM though DT
Add SRAM binding documentation.
---
Changes since v1:
Minor re-wording for better clarity.
--- .../devicetree/bindings/arm/exynos/smp-sram.txt | 38 ++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/exynos/smp-sram.txt
Documentation/devicetree/bindings/arm/exynos/smp-sram.txt new file +38 -0
@@ -0,0 +1,38 @@ +Samsung Exynos SRAM for SMP bringup: +------------------------------------ + +Samsung SMP-capable Exynos SoCs use part of the SRAM for the bringup +of the secondary cores. Once the core gets powered up it executes the +code that is residing at some specific location of the SRAM. + +Therefore reserved section sub-nodes have to be added to the mmio-sram +declaration. These nodes are of two types depending upon secure or +non-secure execution environment. + +Required sub-node properties: +- compatible : depending upon boot mode, should be + "samsung,exynos4210-sram" : for Secure SYSRAM + "samsung,exynos4210-sram-ns" : for Non-secure SYSRAM + +The rest of the properties should follow the generic mmio-sram discription +found in ../../misc/sram.txt + +Example: + + sram at 02020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x54000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x54000>; + + smp-sram at 0 { + compatible = "samsung,exynos4210-sram"; + reg = <0x0 0x1000>; + }; + + smp-sram at 53000 { + compatible = "samsung,exynos4210-sram-ns"; + reg = <0x53000 0x1000>; + }; + };
Signature · 1 line
1.7.9.5
PATCH v2 2/2 Documentation: DT: Exynos: Bind SRAM though DT
Documentation/devicetree/bindings/arm/exynos/smp-sram.txt line 28
Quoted 7 lines · On Friday 02 May 2014 10:36:20 Sachin Kamat wrote:
Documentation/devicetree/bindings/arm/exynos/smp-sram.txt new file +7
-0+ sram at 02020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x54000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x54000>; +
That is actually quite a lot of unused SRAM. Since it came up this morning in another thread, there may be value in using this for coherent DMA allocations for some devices. Not sure about how to best hook this up, but there could be some serious performance improvements. A typical case would be DMA descriptors for a gigabit ethernet adapter, which are a pain to maintain on platforms without cache-coherent DMA.
You could check what drivers you have that call dma_alloc_coherent, and see if any of them are performance-critical, then hack them up to use this memory instead as an experiment.
Arnd
PATCH v2 1/2 ARM: EXYNOS: Map SYSRAM through generic SRAM bindings
In reply to Sachin KamatHi Sachin,
The whole series looks quite good, but I have one concern about support for Universal C210 board. Please see my comment inline.
Quoted 50 lines · Sachin Kamat
Instead of hardcoding the SYSRAM details for each SoC, pass this information through device tree (DT) and make the code SoC agnostic. Generic SRAM bindings are used for achieving this.
Signed-off-by Sachin Kamat <[email protected]>Acked-by Arnd Bergmann <[email protected]>Acked-by Heiko Stuebner <[email protected]>---
This patch is based on linux next (next-20140501) on top of myKconfigconsolidation patch
http://comments.gmane.org/gmane.linux.kernel.samsung-soc/28642Changes since v1:
Type and presence of sram nodes is SoC/board dependent. V1 mandated the presence of both the nodes and used to return an error if one of the nodes was absent and thus fail the boot altogether. Removed this dependency.Tested on 4210/4412 Origen, 5250/5420 Arndale and SMDK5420 boards.
--- arch/arm/Kconfig | 1 + arch/arm/boot/dts/exynos4210-universal_c210.dts | 17 ++++++ arch/arm/boot/dts/exynos4210.dtsi | 18 +++++++ arch/arm/boot/dts/exynos4x12.dtsi | 18 +++++++ arch/arm/boot/dts/exynos5250.dtsi | 18 +++++++ arch/arm/boot/dts/exynos5420.dtsi | 18 +++++++ arch/arm/mach-exynos/common.h | 1 + arch/arm/mach-exynos/exynos.c | 64 ----------------------- arch/arm/mach-exynos/firmware.c | 8 ++- arch/arm/mach-exynos/include/mach/map.h | 7 --- arch/arm/mach-exynos/platsmp.c | 33 ++++++++++-- 11 files changed, 128 insertions(+), 75 deletions(-)arch/arm/Kconfig +1
-0@@ -855,6 +855,7 @@ config ARCH_EXYNOS select S5P_DEV_MFC select SAMSUNG_DMADEV select SPARSE_IRQ + select SRAM select USE_OF help Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)arch/arm/boot/dts/exynos4210-universal_c210.dts +0
-0
arch/arm/boot/dts/exynos4210-universal_c210.dts line 32
Quoted 5 lines
arch/arm/boot/dts/exynos4210-universal_c210.dts +2
-0@@ -28,6 +28,23 @@ bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1"; }; + sram at 02020000 { + status = "disabled";
Here you just disable just the top level node of non-secure SYSRAM, but the sub-nodes are still present and enabled.
Quoted 18 lines
arch/arm/boot/dts/exynos4210-universal_c210.dts +15
-0+ }; + + sram at 02025000 { + compatible = "mmio-sram"; + reg = <0x02025000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02025000 0x1000>; + + smp-sram at 0 { + compatible = "samsung,exynos4210-sram"; + reg = <0x0 0x1000>; + }; + }; + mct at 10050000 { compatible = "none"; };
[snip]
Quoted 14 lines
arch/arm/mach-exynos/platsmp.c +1
-0@@ -20,6 +20,7 @@#include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> +#include <linux/of_address.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h> @@ -33,11 +34,33 @@
arch/arm/mach-exynos/platsmp.c line 44
Quoted 10 lines
arch/arm/mach-exynos/platsmp.c +8
-0extern void exynos4_secondary_startup (void ); +static void __iomem *sram_base_addr; +void __iomem *sram_ns_base_addr; + +static void __init exynos_smp_prepare_sram (void ) +{ +struct device_node *node; + + node =of_find_compatible_node (NULL ,NULL ,"samsung,exynos4210-sram" );
Now here you don't check whether the node is "okay", so on Universal C210 it will pick just the first node with this compatible string,
I think you should be using for_each_compatible_node() here, then check if the node is "okay" using of_devicE_is_available() and only then use this node to map the SYSRAM.
arch/arm/mach-exynos/platsmp.c line 51
Quoted 7 lines
arch/arm/mach-exynos/platsmp.c +7
-0+if (node) { + sram_base_addr =of_iomap (node,0 ); +if (!sram_base_addr) +pr_err ("Secondary CPU boot address not found\n" ); + } + + node =of_find_compatible_node (NULL ,NULL ,"samsung,exynos4210-sram-ns" );
Same here.
Quoted 17 lines
arch/arm/mach-exynos/platsmp.c +8
-1+if (node) { + sram_ns_base_addr =of_iomap (node,0 ); +if (!sram_ns_base_addr) +pr_err ("Secondary CPU boot address not found\n" ); + } +} +static inline void __iomem *cpu_boot_reg_base (void ) {if (soc_is_exynos4210 () &&samsung_rev () ==EXYNOS4210_REV_1_1 )return S5P_INFORM5 ; -return S5P_VA_SYSRAM ; +return sram_base_addr; }static inline void __iomem *cpu_boot_reg (int cpu)
arch/arm/mach-exynos/platsmp.c static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) · line 173
Quoted 5 lines
arch/arm/mach-exynos/platsmp.c +1
-1@@ -147,7 +170,8 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)* and fall back to boot register if it fails. */ if (call_firmware_op (set_cpu_boot_addr, phys_cpu, boot_addr)) -__raw_writel (boot_addr,cpu_boot_reg (phys_cpu)); +if (cpu_boot_reg_base ())
When can this condition be not met?
Quoted 14 lines
arch/arm/mach-exynos/platsmp.c +3
-0+__raw_writel (boot_addr,cpu_boot_reg (phys_cpu));call_firmware_op (cpu_boot, phys_cpu);@@ -205,6 +229,8 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)if (read_cpuid_part_number () ==ARM_CPU_PART_CORTEX_A9 )scu_enable (scu_base_addr ()); +exynos_smp_prepare_sram (); +/* * Write the address of secondary startup into the * system-wide flags register. The boot monitor waits
arch/arm/mach-exynos/platsmp.c static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) · line 251
Quoted 5 lines
arch/arm/mach-exynos/platsmp.c +1
-1@@ -222,7 +248,8 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) boot_addr =virt_to_phys (exynos4_secondary_startup);if (call_firmware_op (set_cpu_boot_addr, phys_cpu, boot_addr)) -__raw_writel (boot_addr,cpu_boot_reg (phys_cpu)); +if (cpu_boot_reg_base ())
Ditto.
Best regards,
Tomasz
PATCH v2 1/2 ARM: EXYNOS: Map SYSRAM through generic SRAM bindings
Hi Tomasz,
Quoted 3 lines · Tomasz Figa
Hi Sachin,
The whole series looks quite good,
Thanks :)
Quoted 63 lines
but I have one concern about support for Universal C210 board. Please see my comment inline.
Quoted 58 lines · Sachin Kamat
Instead of hardcoding the SYSRAM details for each SoC, pass this information through device tree (DT) and make the code SoC agnostic. Generic SRAM bindings are used for achieving this.
Signed-off-by Sachin Kamat <[email protected]>Acked-by Arnd Bergmann <[email protected]>Acked-by Heiko Stuebner <[email protected]>---
This patch is based on linux next (next-20140501) on top of myKconfigconsolidation patch
http://comments.gmane.org/gmane.linux.kernel.samsung-soc/28642Changes since v1:
Type and presence of sram nodes is SoC/board dependent. V1 mandated the presence of both the nodes and used to return an error if one of the nodes was absent and thus fail the boot altogether. Removed this dependency.Tested on 4210/4412 Origen, 5250/5420 Arndale and SMDK5420 boards.
--- arch/arm/Kconfig | 1 + arch/arm/boot/dts/exynos4210-universal_c210.dts | 17 ++++++ arch/arm/boot/dts/exynos4210.dtsi | 18 +++++++ arch/arm/boot/dts/exynos4x12.dtsi | 18 +++++++ arch/arm/boot/dts/exynos5250.dtsi | 18 +++++++ arch/arm/boot/dts/exynos5420.dtsi | 18 +++++++ arch/arm/mach-exynos/common.h | 1 + arch/arm/mach-exynos/exynos.c | 64 ----------------------- arch/arm/mach-exynos/firmware.c | 8 ++- arch/arm/mach-exynos/include/mach/map.h | 7 --- arch/arm/mach-exynos/platsmp.c | 33 ++++++++++-- 11 files changed, 128 insertions(+), 75 deletions(-)arch/arm/Kconfig +1
-0@@ -855,6 +855,7 @@ config ARCH_EXYNOS select S5P_DEV_MFC select SAMSUNG_DMADEV select SPARSE_IRQ + select SRAM select USE_OF help Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)arch/arm/boot/dts/exynos4210-universal_c210.dts +0
-0@@ -28,6 +28,23 @@ bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1"; };
Quoted 6 lines
arch/arm/boot/dts/exynos4210-universal_c210.dts line 32
Quoted 2 lines
arch/arm/boot/dts/exynos4210-universal_c210.dts +2
-0+ sram at 02020000 { + status = "disabled";Here you just disable just the top level node of non-secure SYSRAM, but the sub-nodes are still present and enabled.
I was under the impression that disabling parent node would also disable the sub-nodes.
I will disable all of them in this case.
Quoted 42 lines
Quoted 20 lines
arch/arm/boot/dts/exynos4210-universal_c210.dts +15
-0+ }; + + sram at 02025000 { + compatible = "mmio-sram"; + reg = <0x02025000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02025000 0x1000>; + + smp-sram at 0 { + compatible = "samsung,exynos4210-sram"; + reg = <0x0 0x1000>; + }; + }; + mct at 10050000 { compatible = "none";};[snip]
Quoted 17 lines
arch/arm/mach-exynos/platsmp.c +1
-0@@ -20,6 +20,7 @@#include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> +#include <linux/of_address.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h> @@ -33,11 +34,33 @@extern void exynos4_secondary_startup (void );
Quoted 13 lines
arch/arm/mach-exynos/platsmp.c
Quoted 9 lines
arch/arm/mach-exynos/platsmp.c +8
-0+static void __iomem *sram_base_addr; +void __iomem *sram_ns_base_addr; + +static void __init exynos_smp_prepare_sram (void ) +{ +struct device_node *node; + + node =of_find_compatible_node (NULL ,NULL ,"samsung,exynos4210-sram" );Now here you don't check whether the node is "okay", so on Universal C210 it will pick just the first node with this compatible string,
Right. Missed that one.
Quoted 4 lines
I think you should be using
for_each_compatible_node()here, then check if the node is "okay" usingof_devicE_is_available()and only then use this node to map the SYSRAM.
OK.
Quoted 12 lines
arch/arm/mach-exynos/platsmp.c
Quoted 10 lines
arch/arm/mach-exynos/platsmp.c +7
-0+if (node) { + sram_base_addr =of_iomap (node,0 ); +if (!sram_base_addr) +pr_err ("Secondary CPU boot address not found\n" ); + } + + node =of_find_compatible_node (NULL ,NULL ,"samsung,exynos4210-sram-ns" );
Quoted 1 line
Same here.
OK.
Quoted 17 lines
Quoted 17 lines
arch/arm/mach-exynos/platsmp.c +8
-1+if (node) { + sram_ns_base_addr =of_iomap (node,0 ); +if (!sram_ns_base_addr) +pr_err ("Secondary CPU boot address not found\n" ); + } +} +static inline void __iomem *cpu_boot_reg_base (void ) {if (soc_is_exynos4210 () &&samsung_rev () ==EXYNOS4210_REV_1_1 )return S5P_INFORM5 ; -return S5P_VA_SYSRAM ; +return sram_base_addr; }
Quoted 12 lines
arch/arm/mach-exynos/platsmp.c static int exynos_boot_secondary(unsigned int cpu, · line 175
Quoted 9 lines
static inline void
__iomem*cpu_boot_reg(int cpu)arch/arm/mach-exynos/platsmp.c +1
-1@@ -147,7 +170,8 @@ static int exynos_boot_secondary(unsigned int cpu,struct task_struct *idle) * and fall back to boot register if it fails. */ if (call_firmware_op (set_cpu_boot_addr, phys_cpu, boot_addr)) -__raw_writel (boot_addr,cpu_boot_reg (phys_cpu)); +if (cpu_boot_reg_base ())When can this condition be not met?
I experimented with various combinations of node presence/absence in dts files and in one such case if we do not have the sram-ns node present (on arndale-octa),
the system just hung at boot time (as base address was null) and this check became
necessary.
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arch/arm/mach-exynos/platsmp.c +1
-0+__raw_writel (boot_addr,cpu_boot_reg (phys_cpu));call_firmware_op(cpu_boot, phys_cpu);arch/arm/mach-exynos/platsmp.c +2
-0@@ -205,6 +229,8 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)if (read_cpuid_part_number () ==ARM_CPU_PART_CORTEX_A9 )scu_enable (scu_base_addr ()); +exynos_smp_prepare_sram (); +/* * Write the address of secondary startup into the * system-wide flags register. The boot monitor waits
arch/arm/mach-exynos/platsmp.c +0
-0@@ -222,7 +248,8 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) boot_addr =virt_to_phys (exynos4_secondary_startup);
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arch/arm/mach-exynos/platsmp.c static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) · line 173
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arch/arm/mach-exynos/platsmp.c +1
-1if (call_firmware_op (set_cpu_boot_addr, phys_cpu, boot_addr)) -__raw_writel (boot_addr,cpu_boot_reg (phys_cpu)); +if (cpu_boot_reg_base ())Ditto.
ditto.
Thanks for your review. Will update the same in v3.
Signature · 2 lines
With warm regards, Sachin