SH4 MMU improvements.

@@ -360,6 +360,9 @@
     case SH7750_PTEL_A7:
 	s->cpu->ptel = mem_value;
 	return;
+    case SH7750_PTEA_A7:
+	s->cpu->ptea = mem_value & 0x0000000f;
+	return;
     case SH7750_TTB_A7:
 	s->cpu->ttb = mem_value;
 	return;

78 lines not on this page · raw message

diff -ruwN a/target-sh4/exec.h b/target-sh4/exec.h
@@ -64,6 +64,7 @@
 
 int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
 			     int mmu_idx, int is_softmmu);
+void cpu_load_tlb(CPUState * env);
 
 int find_itlb_entry(CPUState * env, target_ulong address,
 		    int use_asid, int update);

@@ -81,6 +82,7 @@
 void helper_subv_T0_T1(void);
 void helper_rotcl(uint32_t * addr);
 void helper_rotcr(uint32_t * addr);
+void helper_ldtlb(void);
 
 void do_interrupt(CPUState * env);
 

106 lines not on this page · raw message

diff -ruwN a/target-sh4/op.c b/target-sh4/op.c
@@ -185,6 +185,12 @@
     RETURN();
 }
 
+void OPPROTO op_ldtlb(void)
+{
+    helper_ldtlb();
+    RETURN();
+}
+
 void OPPROTO op_sets(void)
 {
     env->sr |= SR_S;

diff -ruwN a/target-sh4/op_helper.c b/target-sh4/op_helper.c
@@ -76,6 +76,16 @@
 
 #endif
 
+void helper_ldtlb(void)
+{
+#ifdef CONFIG_USER_ONLY
+    /* XXXXX */
+    assert(0);
+#else
+    cpu_load_tlb(env);
+#endif
+}
+
 void helper_addc_T0_T1(void)
 {
     uint32_t tmp0, tmp1;

diff -ruwN a/target-sh4/translate.c b/target-sh4/translate.c
@@ -256,7 +256,11 @@
 	gen_op_clrt();
 	return;
     case 0x0038:		/* ldtlb */
+#if defined(CONFIG_USER_ONLY)
 	assert(0);		/* XXXXX */
+#else
+	gen_op_ldtlb();
+#endif
 	return;
     case 0x002b:		/* rte */
 	CHECK_NOT_DELAY_SLOT gen_op_rte();