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ARM: OMAP3: Check for L2 cache enabled

PATCH In review Dirk Behme 3 participants 3 messages May 11, 2008 – May 14, 2008

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Arm (32-bit) Arm sub-architectures OMAP2+ support
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Dirk Behme

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#0 lore raw

PATCH v3 1/1 ARM: OMAP3: Check for L2 cache enabled

Enabling L2 cache of Cortex-A8 based OMAP3 has to be done by bootloader. Check if this is done and warn if not.

Signed-off-by Dirk Behme <[email protected]>

----

Changes in v3: Remove braces. Thanks to Felipe for review!

arch/arm/mach-omap2/id.c +22 -0
Index: linux-beagle/arch/arm/mach-omap2/id.c
===================================================================
@@ -267,3 +267,25 @@ void __init omap2_check_revision(void)
 
 }
 
+#ifdef CONFIG_ARCH_OMAP3
+/*
+ * OMAP3 has L2 cache which has to be enabled by bootloader.
+ */
+static int __init omap3_check_l2cache(void)
+{
+	u32 val;
+
+	/* Get CP15 AUX register, bit 1 enabled indicates L2 cache is on */
+	asm volatile("mrc p15, 0, %0, c1, c0, 1":"=r" (val));
+
+	if ((val & 0x2) == 0)
+		printk(KERN_WARNING "Warning: L2 cache not enabled. Check "
+		       "your bootloader. L2 off results in performance loss\n");
+	else
+		pr_info("OMAP3 L2 cache enabled\n");
+
+	return 0;
+}
+
+arch_initcall(omap3_check_l2cache);
+#endif /* CONFIG_ARCH_OMAP3 */
Acked-by on v3 1/1
#1 lore raw
Quoted 5 lines · Dirk Behme

Enabling L2 cache of Cortex-A8 based OMAP3 has to be done by bootloader. Check if this is done and warn if not.

Signed-off-by Dirk Behme <[email protected]>
Acked-by Felipe Balbi <[email protected]>
Quoted 35 lines

----

Changes in v3: Remove braces. Thanks to Felipe for review!

Index: linux-beagle/arch/arm/mach-omap2/id.c
===================================================================

arch/arm/mach-omap2/id.c +22 -0
@@ -267,3 +267,25 @@ void __init omap2_check_revision(void)
 
 }
 
+#ifdef CONFIG_ARCH_OMAP3
+/*
+ * OMAP3 has L2 cache which has to be enabled by bootloader.
+ */
+static int __init omap3_check_l2cache(void)
+{
+	u32 val;
+
+	/* Get CP15 AUX register, bit 1 enabled indicates L2 cache is on */
+	asm volatile("mrc p15, 0, %0, c1, c0, 1":"=r" (val));
+
+	if ((val & 0x2) == 0)
+		printk(KERN_WARNING "Warning: L2 cache not enabled. Check "
+		       "your bootloader. L2 off results in performance loss\n");
+	else
+		pr_info("OMAP3 L2 cache enabled\n");
+
+	return 0;
+}
+
+arch_initcall(omap3_check_l2cache);
+#endif /* CONFIG_ARCH_OMAP3 */
Signature · 5 lines
Best Regards,

Felipe Balbi
[email protected]
http://blog.felipebalbi.com
maintainer
#2 lore raw
Quoted 7 lines · Felipe Balbi
Quoted 5 lines · Dirk Behme

Enabling L2 cache of Cortex-A8 based OMAP3 has to be done by bootloader. Check if this is done and warn if not.

Signed-off-by Dirk Behme <[email protected]>
Acked-by Felipe Balbi <[email protected]>

Pushing today.

Tony

Quoted 47 lines
Quoted 35 lines

----

Changes in v3: Remove braces. Thanks to Felipe for review!

Index: linux-beagle/arch/arm/mach-omap2/id.c
===================================================================

arch/arm/mach-omap2/id.c +22 -0
@@ -267,3 +267,25 @@ void __init omap2_check_revision(void)
 
 }
 
+#ifdef CONFIG_ARCH_OMAP3
+/*
+ * OMAP3 has L2 cache which has to be enabled by bootloader.
+ */
+static int __init omap3_check_l2cache(void)
+{
+	u32 val;
+
+	/* Get CP15 AUX register, bit 1 enabled indicates L2 cache is on */
+	asm volatile("mrc p15, 0, %0, c1, c0, 1":"=r" (val));
+
+	if ((val & 0x2) == 0)
+		printk(KERN_WARNING "Warning: L2 cache not enabled. Check "
+		       "your bootloader. L2 off results in performance loss\n");
+	else
+		pr_info("OMAP3 L2 cache enabled\n");
+
+	return 0;
+}
+
+arch_initcall(omap3_check_l2cache);
+#endif /* CONFIG_ARCH_OMAP3 */
Signature · 9 lines
Best Regards,

Felipe Balbi
[email protected]
http://blog.felipebalbi.com
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