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85xx: various fixes for TQM85xx and support for TQM8548

PATCH New Wolfgang Grandegger 5 participants 26 messages May 28, 2008 – Jun 3, 2008

Subsystems (4)
Kbuild Memory technology devices (MTD) Input drivers NAND flash
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Wolfgang Grandegger

author
#0 lore raw

cover 85xx: various fixes for TQM85xx and support for TQM8548

This series of patches fixes various issues with TQM85xx modules and adds support for TQM8548 modules from TQ Components GmbH (http://www.tqc.de).

Note: The patches rely on "[PATCH] TQM: move TQM boards to board/tqc"
sent a few minutes ago to this list.

Wolfgang.

author
#1 lore raw

PATCH 1/1 MPC85xx: Beatify boot output of L2 cache configuration

The boot output is now aligned poperly with other boot output lines, e.g.:

FLASH: 128 MB
L2: 512 KB enabled

Signed-off-by Wolfgang Grandegger <[email protected]>
---
 cpu/mpc85xx/cpu.c      |    2 +-
 cpu/mpc85xx/cpu_init.c |   18 ++++++++++--------
 2 files changed, 11 insertions(+), 9 deletions(-)
cpu/mpc85xx/cpu.c +1 -1
index 9873383..274b486 100644
@@ -159,7 +159,7 @@ int checkcpu (void)
 	}
 
 #ifdef CONFIG_CPM2
-	printf("CPM:  %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
+	printf("CPM:   %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
 #endif
 
 	puts("L1:    D-cache 32 kB enabled\n       I-cache 32 kB enabled\n");
cpu/mpc85xx/cpu_init.c +10 -8
index e3240b5..0fb36c4 100644
@@ -265,6 +265,8 @@ int cpu_init_r(void)
 #endif
 #endif
 
+	puts ("L2:    ");
+
 #if defined(CONFIG_L2_CACHE)
 	volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR;
 	volatile uint cache_ctl;

@@ -281,17 +283,17 @@ int cpu_init_r(void)
 	case 0x20000000:
 		if (ver == SVR_8548 || ver == SVR_8548_E ||
 		    ver == SVR_8544 || ver == SVR_8568_E) {
-			printf ("L2 cache 512KB:");
+			puts ("512 KB ");
 			/* set L2E=1, L2I=1, & L2SRAM=0 */
 			cache_ctl = 0xc0000000;
 		} else {
-			printf ("L2 cache 256KB:");
+			puts("256 KB ");
 			/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
 			cache_ctl = 0xc8000000;
 		}
 		break;
 	case 0x10000000:
-		printf ("L2 cache 256KB:");
+		puts("256 KB ");
 		if (ver == SVR_8544 || ver == SVR_8544_E) {
 			cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
 		}

@@ -299,18 +301,18 @@ int cpu_init_r(void)
 	case 0x30000000:
 	case 0x00000000:
 	default:
-		printf ("L2 cache unknown size (0x%08x)\n", cache_ctl);
+		printf(" unknown size (0x%08x)\n", cache_ctl);
 		return -1;
 	}
 
 	if (l2cache->l2ctl & 0x80000000) {
-		printf(" already enabled.");
+		puts("already enabled");
 		l2srbar = l2cache->l2srbar0;
 #ifdef CFG_INIT_L2_ADDR
 		if (l2cache->l2ctl & 0x00010000 && l2srbar >= CFG_FLASH_BASE) {
 			l2srbar = CFG_INIT_L2_ADDR;
 			l2cache->l2srbar0 = l2srbar;
-			printf("  Moving to 0x%08x", CFG_INIT_L2_ADDR);
+			printf("moving to 0x%08x", CFG_INIT_L2_ADDR);
 		}
 #endif /* CFG_INIT_L2_ADDR */
 		puts("\n");

@@ -318,10 +320,10 @@ int cpu_init_r(void)
 		asm("msync;isync");
 		l2cache->l2ctl = cache_ctl; /* invalidate & enable */
 		asm("msync;isync");
-		printf(" enabled\n");
+		puts("enabled\n");
 	}
 #else
-	printf("L2 cache: disabled\n");
+	puts("disabled\n");
 #endif
 #ifdef CONFIG_QE
 	uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */
Signature · 1 line
1.5.2.2
author
#2 lore raw

PATCH 1/1 TQM85xx: Various coding style fixes

Signed-off-by Wolfgang Grandegger <[email protected]>
---
 board/tqc/tqm85xx/law.c     |   12 +-
 board/tqc/tqm85xx/sdram.c   |   56 ++++----
 board/tqc/tqm85xx/tlb.c     |   98 +++++++------
 board/tqc/tqm85xx/tqm85xx.c |  330 +++++++++++++++++++++---------------------
 include/configs/TQM85xx.h   |   88 ++++++------
 5 files changed, 293 insertions(+), 291 deletions(-)
board/tqc/tqm85xx/law.c +6 -6
index 224af6c..d937700 100644
@@ -44,11 +44,11 @@
  */
 
 struct law_entry law_table[] = {
-	SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
-	SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
-	SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
-	SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+	SET_LAW_ENTRY (1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
+	SET_LAW_ENTRY (2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW_ENTRY (3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+	SET_LAW_ENTRY (4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
+	SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
 };
 
-int num_law_entries = ARRAY_SIZE(law_table);
+int num_law_entries = ARRAY_SIZE (law_table);
board/tqc/tqm85xx/sdram.c +28 -28

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board/tqc/tqm85xx/tlb.c +52 -46

139 lines not on this page · raw message

board/tqc/tqm85xx/tqm85xx.c +165 -165

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include/configs/TQM85xx.h +42 -46

258 lines not on this page · raw message

Signature · 1 line
1.5.2.2
author
#3 lore raw

PATCH 1/1 TQM85xx: Fix CPM port pin configuration

Do not configure port pins PD30/PD31 as SCC1 TxD/RxD except for the TQM8560 board. On the other TQM85xx boards (TQM8541 and TQM8555) SCC1 is not used as serial interface anyway. Worse, on some board variants configuring the pins for SCC1 leads to short circuits (for example on the TQM8541-BG).

Signed-off-by Martin Krause <[email protected]>
---
 board/tqc/tqm85xx/tqm85xx.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)
board/tqc/tqm85xx/tqm85xx.c +6 -0
index 31364d3..af8c170 100644
@@ -165,9 +165,15 @@ const iop_conf_t iop_conf_tab[4][32] = {
 
 	/* Port D: conf, ppar, psor, pdir, podr, pdat */
 	{
+#ifdef CONFIG_TQM8560
 	 {1, 1, 0, 0, 0, 0},	/* PD31: SCC1 EN RxD */
 	 {1, 1, 1, 1, 0, 0},	/* PD30: SCC1 EN TxD */
 	 {1, 1, 0, 1, 0, 0},	/* PD29: SCC1 EN TENA */
+#else /* !CONFIG_TQM8560 */
+	 {0, 0, 0, 0, 0, 0},	/* PD31: PD31 */
+	 {0, 0, 0, 0, 0, 0},	/* PD30: PD30 */
+	 {0, 0, 0, 0, 0, 0},	/* PD29: PD29 */
+#endif /* CONFIG_TQM8560 */
 	 {1, 1, 0, 0, 0, 0},	/* PD28: PD28 */
 	 {1, 1, 0, 1, 0, 0},	/* PD27: PD27 */
 	 {1, 1, 0, 1, 0, 0},	/* PD26: PD26 */
Signature · 1 line
1.5.2.2
author
#4 lore raw

PATCH 1/1 TQM85xx: Support for Spansion 'N' type flashes added

The 'N' type Spansion flashes (S29GLxxxM series) have bigger sectors, than the formerly used 'M' types (S29GLxxxM series), so the flash layout needs to be changed -> new start address of the environment. The macro definition CONFIG_TQM_FLASH_N_TYPE is undefined by default and must be defined for boards with 'N' type flashes.

Signed-off-by Martin Krause <[email protected]>
Signed-off-by Wolfgang Grandegger <[email protected]>
---
 include/configs/TQM85xx.h |   20 ++++++++++++++++----
 1 files changed, 16 insertions(+), 4 deletions(-)
include/configs/TQM85xx.h +16 -4
index f0e7318..4011b2a 100644
@@ -109,6 +109,13 @@
 #endif /* CONFIG_TQM8541 || CONFIG_TQM8555 */
 
 /*
+ * Old TQM85xx boards have 'M' type Spansion Flashes from the S29GLxxxM
+ * series while new boards have 'N' type Flashes from the S29GLxxxN
+ * series, which have bigger sectors: 128 instead of 256 KB.
+ */
+#undef CONFIG_TQM_FLASH_N_TYPE
+
+/*
  * Flash on the Local Bus
  */
 #define CFG_FLASH0		0xFC000000

@@ -151,7 +158,7 @@
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 #define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserved for malloc	*/
 
 /* Serial Port */
 #if defined(CONFIG_TQM8560)

@@ -351,10 +358,15 @@
  * Environment
  */
 #define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x20000)
-#define CFG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env	*/
+
+#ifdef CONFIG_TQM_FLASH_N_TYPE
+#define CFG_ENV_SECT_SIZE	0x40000 /* 256K (one sector) for env	*/
+#else /* !CONFIG_TQM_FLASH_N_TYPE */
+#define CFG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) for env	*/
+#endif /* CONFIG_TQM_FLASH_N_TYPE */
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
 #define CFG_ENV_SIZE		0x2000
-#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
 #define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
Signature · 1 line
1.5.2.2
author
#5 lore raw

PATCH 1/1 TQM85xx: Fix chip select configuration for second FLASH bank

This patch fixes the re-calculation of the automatic chip select configuration for boards with two populated FLASH banks.

Signed-off-by Martin Krause <[email protected]>
---
 board/tqc/tqm85xx/tqm85xx.c |   86 +++++++++++++++++++++++-------------------
 1 files changed, 47 insertions(+), 39 deletions(-)
board/tqc/tqm85xx/tqm85xx.c +47 -39
index af8c170..f38b009 100644
@@ -274,53 +274,61 @@ int misc_init_r (void)
 	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 	gd->bd->bi_flashoffset = 0;
 
-	/*
-	 * Check if boot FLASH isn't max size
+  	/*
+	 * Recalculate CS configuration if second FLASH bank is available
 	 */
-	if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) {
-		memctl->or0 =
-		    gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff);
-		memctl->br0 =
-		    gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff);
-
+	if (flash_info[0].size > 0) {
+		memctl->or1 = ((-flash_info[0].size) & 0xffff8000) |
+			(CFG_OR1_PRELIM & 0x00007fff);
+		memctl->br1 = gd->bd->bi_flashstart |
+			(CFG_BR1_PRELIM & 0x00007fff);
 		/*
-		 * Re-check to get correct base address
+		 * Re-check to get correct base address for bank 1
 		 */
-		flash_get_size (gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
+		flash_get_size (gd->bd->bi_flashstart, 0);
+	} else {
+		memctl->or1 = 0;
+		memctl->br1 = 0;
 	}
 
 	/*
-	 * Check if only one FLASH bank is available
+	 *  If bank 1 is equipped, bank 0 is mapped after bank 1
 	 */
-	if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
-		memctl->or1 = 0;
-		memctl->br1 = 0;
+	memctl->or0 = ((-flash_info[1].size) & 0xffff8000) |
+		(CFG_OR0_PRELIM & 0x00007fff);
+	memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) |
+		(CFG_BR0_PRELIM & 0x00007fff);
+	/*
+	 * Re-check to get correct base address for bank 0
+	 */
+	flash_get_size (gd->bd->bi_flashstart + flash_info[0].size, 1);
 
-		/*
-		 * Re-do flash protection upon new addresses
-		 */
-		flash_protect (FLAG_PROTECT_CLEAR,
-			       gd->bd->bi_flashstart, 0xffffffff,
-			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
-
-		/* Monitor protection ON by default */
-		flash_protect (FLAG_PROTECT_SET,
-			       CFG_MONITOR_BASE,
-			       CFG_MONITOR_BASE + monitor_flash_len - 1,
-			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
-
-		/* Environment protection ON by default */
-		flash_protect (FLAG_PROTECT_SET,
-			       CFG_ENV_ADDR,
-			       CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
-			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
-
-		/* Redundant environment protection ON by default */
-		flash_protect (FLAG_PROTECT_SET,
-			       CFG_ENV_ADDR_REDUND,
-			       CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
-			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
-	}
+	/*
+	 * Re-do flash protection upon new addresses
+	 */
+	flash_protect (FLAG_PROTECT_CLEAR,
+		       gd->bd->bi_flashstart, 0xffffffff,
+		       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+	/* Monitor protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + monitor_flash_len - 1,
+		       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+	/* Environment protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+		       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+#ifdef CFG_ENV_ADDR_REDUND
+	/* Redundant environment protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR_REDUND,
+		       CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+		       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+#endif
 
 	return 0;
 }
Signature · 1 line
1.5.2.2
author
#6 lore raw

PATCH 1/1 TQM85xx: Bugfix in the SDRAM initialisation

The CS0_BNDS register is now set according to the detected memory size.

Signed-off-by Martin Krause <[email protected]>

---
 board/tqc/tqm85xx/sdram.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)
board/tqc/tqm85xx/sdram.c +3 -1
index 413567e..e005d84 100644
@@ -104,8 +104,10 @@ long int sdram_setup (int casl)
 		if (get_ram_size (0, ddr_cs_conf[i].size) ==
 		    ddr_cs_conf[i].size) {
 			/*
-			 * OK, size detected -> all done
+			 * size detected -> set Chip Select Bounds Register
 			 */
+			ddr->cs0_bnds = (ddr_cs_conf[i].size - 1) >> 24;
+
 			return ddr_cs_conf[i].size;
 		}
 	}
Signature · 1 line
1.5.2.2
author
#7 lore raw

PATCH 1/1 TQM85xx: Support for Intel 82527 compatible CAN controller

This patch adds initialization of the UPMC RAM to support up to two Intel 82527 compatible CAN controller on the TQM85xx modules.

Signed-off-by Thomas Waehner <[email protected]>
Signed-off-by Wolfgang Grandegger <[email protected]>
---
 board/tqc/tqm85xx/law.c     |    4 +++
 board/tqc/tqm85xx/tlb.c     |    1 +
 board/tqc/tqm85xx/tqm85xx.c |   59 +++++++++++++++++++++++++++++++++++++++++++
 include/configs/TQM85xx.h   |   11 ++++++++
 include/mpc85xx.h           |    5 +++
 5 files changed, 80 insertions(+), 0 deletions(-)
board/tqc/tqm85xx/law.c +4 -0
index d937700..ad35464 100644
@@ -35,6 +35,7 @@
  * 0xc000_0000	   0xdfff_ffff	   RapidIO		   512M
  * 0xe000_0000	   0xe000_ffff	   CCSR			   1M
  * 0xe200_0000	   0xe2ff_ffff	   PCI1 IO		   16M
+ * 0xe300_0000	   0xe3ff_ffff	   CAN			   16M
  * 0xf800_0000	   0xf80f_ffff	   BCSR			   1M
  * 0xfe00_0000	   0xffff_ffff	   FLASH (boot bank)	   32M
  *

@@ -49,6 +50,9 @@ struct law_entry law_table[] = {
 	SET_LAW_ENTRY (3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
 	SET_LAW_ENTRY (4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
 	SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+#ifdef CONFIG_CAN_DRIVER
+	SET_LAW_ENTRY (6, CFG_CAN_BASE, LAWAR_SIZE_16M, LAW_TRGT_IF_LBC),
+#endif /* CONFIG_CAN_DRIVER */
 };
 
 int num_law_entries = ARRAY_SIZE (law_table);
board/tqc/tqm85xx/tlb.c +1 -0
index 3e29062..dc36201 100644
@@ -95,6 +95,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * TLB 6:	 64M	Non-cacheable, guarded
 	 * 0xe0000000	  1M	CCSRBAR
 	 * 0xe2000000	 16M	PCI1 IO
+	 * 0xe3000000	 16M	CAN
 	 */
 	SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
board/tqc/tqm85xx/tqm85xx.c +59 -0

77 lines not on this page · raw message

include/configs/TQM85xx.h +11 -0
index 4011b2a..9eec858 100644
@@ -52,6 +52,8 @@
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code	*/
 
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support		*/
+
 /*
  * sysclk for MPC85xx
  *

@@ -199,6 +201,15 @@
 #define	CFG_PROMPT_HUSH_PS2	"> "
 #endif
 
+/* CAN */
+#ifdef CONFIG_CAN_DRIVER
+#define CFG_CAN_BASE		0xE3000000	/* CAN base address     */
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 KiB address mask  */
+#define CFG_OR2_CAN		(CFG_CAN_OR_AM | ORxU_BI)
+#define CFG_BR2_CAN		((CFG_CAN_BASE & BRx_BA_MSK) | \
+				 BRx_PS_8 | BRx_MS_UPMC | BRx_V)
+#endif /* CONFIG_CAN_DRIVER */
+
 /*
  * I2C
  */
include/mpc85xx.h +5 -0
index 321b24f..9dbc9a8 100644
@@ -53,7 +53,12 @@
 #define ORxU_AM_MSK	0xffff8000	/* Address Mask Mask		*/
 
 #define MxMR_OP_NORM	0x00000000	/* Normal Operation		*/
+#define MxMR_MAD	0x0000003F	/* Machine address, RAM address ptr*/
+#define MxMR_WLFx_3X	0x00000C00	/* Write loop executed 3 times	*/
+#define MxMR_GPL4_DIS	0x00040000	/* GPL4 output line disable	*/
 #define MxMR_DSx_2_CYCL 0x00400000	/* 2 cycle Disable Period	*/
+#define MxMR_DSx_3_CYCL 0x00800000	/* 3 cycle Disable Period	*/
+#define MxMR_DSx_4_CYCL 0x00C00000	/* 4 cycle Disable Period	*/
 #define MxMR_OP_WARR	0x10000000	/* Write to Array		*/
 #define MxMR_BSEL	0x80000000	/* Bus Select			*/
Signature · 1 line
1.5.2.2
author
#8 lore raw

PATCH 1/1 TQM85xx: Support for Flat Device Tree

This patch adds support for Linux kernels using the Flat Device Tree. It also re-defines the default environment settings for booting Linux with the FDT blob.

Signed-off-by Wolfgang Grandegger <[email protected]>
---
 Makefile                    |    3 +-
 board/tqc/tqm85xx/tqm85xx.c |   24 ++++++++++++++++++++
 include/configs/TQM85xx.h   |   50 +++++++++++++++++++++++++++++++++---------
 3 files changed, 64 insertions(+), 13 deletions(-)
Makefile +1 -2
index 7d05d62..32c9643 100644
@@ -2233,8 +2233,7 @@ TQM8560_config:		unconfig
 	echo "#define CONFIG_MPC$${CTYPE}">>$(obj)include/config.h; \
 	echo "#define CONFIG_TQM$${CTYPE}">>$(obj)include/config.h; \
 	echo "#define CONFIG_HOSTNAME tqm$${CTYPE}">>$(obj)include/config.h; \
-	echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h; \
-	echo "#define CFG_BOOTFILE_PATH \"/tftpboot/tqm$${CTYPE}/uImage\"">>$(obj)include/config.h
+	echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h;
 	@$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx tqc
 
 #########################################################################
board/tqc/tqm85xx/tqm85xx.c +24 -0
index bca59a3..8690fb1 100644
@@ -34,6 +34,8 @@
 #include <asm/io.h>
 #include <ioports.h>
 #include <flash.h>
+#include <libfdt.h>
+#include <fdt_support.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -481,6 +483,28 @@ void pci_init_board (void)
 #endif /* CONFIG_PCI */
 }
 
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup (void *blob, bd_t *bd)
+{
+	int node, tmp[2];
+	const char *path;
+
+	ft_cpu_setup (blob, bd);
+
+	node = fdt_path_offset (blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
+#ifdef CONFIG_PCI
+		path = fdt_getprop (blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = hose.last_busno - hose.first_busno;
+			do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+	}
+}
+#endif
+
 #ifdef CONFIG_BOARD_EARLY_INIT_R
 int board_early_init_r (void)
 {
include/configs/TQM85xx.h +39 -11

72 lines not on this page · raw message

Signature · 1 line
1.5.2.2
author
#9 lore raw

PATCH 1/1 TQM8548: Basic support for the TQM8548 modules

This patch adds basic support for the TQM8548 module from TQ-Components
(http://www.tqc.de/) including DDR2 SDRAM initialisation and support for eTSEC 3 and 4

Furthermore Flash buffer write has been enabled to speed up output to the Flash by approx. a factor of 10.

Signed-off-by Thomas Waehner <[email protected]>
Signed-off-by Wolfgang Grandegger <[email protected]>
---
 MAKEALL                     |    1 +
 Makefile                    |    1 +
 board/tqc/tqm85xx/sdram.c   |  150 ++++++++++++++++++++++++++++++++++++++++++-
 board/tqc/tqm85xx/tqm85xx.c |  113 ++++++++++++++++++++++++++++----
 drivers/input/ps2ser.c      |   31 ++++++---
 include/configs/TQM85xx.h   |   71 ++++++++++++++++++--
 include/mpc85xx.h           |    9 +++
 7 files changed, 343 insertions(+), 33 deletions(-)
MAKEALL +1 -0
index 0674069..ec20e62 100755
@@ -359,6 +359,7 @@ LIST_85xx="		\
 	stxssa		\
 	TQM8540		\
 	TQM8541		\
+	TQM8548		\
 	TQM8555		\
 	TQM8560		\
 "
Makefile +1 -0
index 32c9643..3cca59c 100644
@@ -2225,6 +2225,7 @@ stxssa_4M_config:	unconfig
 
 TQM8540_config		\
 TQM8541_config		\
+TQM8548_config		\
 TQM8555_config		\
 TQM8560_config:		unconfig
 	@mkdir -p $(obj)include
board/tqc/tqm85xx/sdram.c +148 -2

195 lines not on this page · raw message

board/tqc/tqm85xx/tqm85xx.c +100 -13

156 lines not on this page · raw message

drivers/input/ps2ser.c +21 -10
index 4e304f7..c1741ea 100644
@@ -49,7 +49,8 @@ DECLARE_GLOBAL_DATA_PTR;
 #error CONFIG_PS2SERIAL must be in 1 ... 6
 #endif
 
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
+      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
 
 #if CONFIG_PS2SERIAL == 1
 #define COM_BASE (CFG_CCSRBAR+0x4500)

@@ -65,7 +66,9 @@ static int	ps2ser_getc_hw(void);
 static void	ps2ser_interrupt(void *dev_id);
 
 extern struct	serial_state rs_table[]; /* in serial.c */
-#if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && !defined(CONFIG_MPC8555)
+#if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC8540) && \
+    !defined(CONFIG_MPC8541) && !defined(CONFIG_MPC8548) && \
+    !defined(CONFIG_MPC8555)
 static struct	serial_state *state;
 #endif
 

@@ -120,7 +123,8 @@ int ps2ser_init(void)
 	return (0);
 }
 
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
+      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
 int ps2ser_init(void)
 {
 	NS16550_t com_port = (NS16550_t)COM_BASE;

@@ -186,7 +190,8 @@ void ps2ser_putc(int chr)
 {
 #ifdef CONFIG_MPC5xxx
 	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
+      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
 	NS16550_t com_port = (NS16550_t)COM_BASE;
 #endif
 #ifdef DEBUG

@@ -197,7 +202,8 @@ void ps2ser_putc(int chr)
 	while (!(psc->psc_status & PSC_SR_TXRDY));
 
 	psc->psc_buffer_8 = chr;
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
+      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
 	while ((com_port->lsr & LSR_THRE) == 0);
 	com_port->thr = chr;
 #else

@@ -211,7 +217,8 @@ static int ps2ser_getc_hw(void)
 {
 #ifdef CONFIG_MPC5xxx
 	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
+      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
 	NS16550_t com_port = (NS16550_t)COM_BASE;
 #endif
 	int res = -1;

@@ -220,7 +227,8 @@ static int ps2ser_getc_hw(void)
 	if (psc->psc_status & PSC_SR_RXRDY) {
 		res = (psc->psc_buffer_8);
 	}
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
+      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
 	if (com_port->lsr & LSR_DR) {
 		res = com_port->rbr;
 	}

@@ -279,7 +287,8 @@ static void ps2ser_interrupt(void *dev_id)
 {
 #ifdef CONFIG_MPC5xxx
 	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
+      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
 	NS16550_t com_port = (NS16550_t)COM_BASE;
 #endif
 	int chr;

@@ -289,7 +298,8 @@ static void ps2ser_interrupt(void *dev_id)
 		chr = ps2ser_getc_hw();
 #ifdef CONFIG_MPC5xxx
 		status = psc->psc_status;
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
+      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
 		status = com_port->lsr;
 #else
 		status = ps2ser_in(UART_IIR);

@@ -305,7 +315,8 @@ static void ps2ser_interrupt(void *dev_id)
 		}
 #ifdef CONFIG_MPC5xxx
 	} while (status & PSC_SR_RXRDY);
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
+      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
 	} while (status & LSR_DR);
 #else
 	} while (status & UART_IIR_RDI);
include/configs/TQM85xx.h +63 -8

131 lines not on this page · raw message

include/mpc85xx.h +9 -0
index 9dbc9a8..c2a7510 100644
@@ -49,6 +49,7 @@
 #define ORxG_ACS_DIV2	0x00000600	/* CS is output 1/2 a clock later*/
 #define ORxG_CSNT	0x00000800	/* Chip Select Negation Time	*/
 
+#define ORxU_EAD	0x00000001	/* External addr latch delay	*/
 #define ORxU_BI		0x00000100	/* Burst Inhibit		*/
 #define ORxU_AM_MSK	0xffff8000	/* Address Mask Mask		*/
 

@@ -66,4 +67,12 @@
 #define P2SZ_TO_AM(s)	((~((s) - 1)) & 0xffff8000)	/* must be pow of 2 */
 #define MEG_TO_AM(m)	P2SZ_TO_AM((m) << 20)
 
+/* Clock Ratio Register */
+#define LCRR_DBYP	0x80000000	/* PLL bypass			*/
+#define	LCRR_EADC_MSK	0x00030000	/* external address delay cycles mask */
+#define	LCRR_EADC_4	0x00000000	/* 4 cycles			*/
+#define	LCRR_EADC_1	0x00010000	/* 1 cycle			*/
+#define	LCRR_EADC_2	0x00020000	/* 2 cycles			*/
+#define	LCRR_EADC_3	0x00030000	/* 3 cycles			*/
+
 #endif	/* __MPC85xx_H__ */
Signature · 1 line
1.5.2.2
author
#10 lore raw

PATCH 1/1 TQM8548: PCI express support

This patch adds support for PCI express cards. The board support now uses common FSL PCI init code, for both, PCI and PCIe on all TQM85xx modules.

Signed-off-by Thomas Waehner <[email protected]>
Signed-off-by Wolfgang Grandegger <[email protected]>
---
 board/tqc/tqm85xx/law.c     |   15 +++-
 board/tqc/tqm85xx/tlb.c     |   30 ++++++
 board/tqc/tqm85xx/tqm85xx.c |  205 ++++++++++++++++++++++++++++++++++++-------
 include/configs/TQM85xx.h   |   35 +++++++-
 4 files changed, 249 insertions(+), 36 deletions(-)
board/tqc/tqm85xx/law.c +11 -4
index ad35464..bec1ed5 100644
@@ -32,11 +32,11 @@
  *
  * 0x0000_0000	   0x7fff_ffff	   DDR			   2G
  * 0x8000_0000	   0x9fff_ffff	   PCI1 MEM		   512M
- * 0xc000_0000	   0xdfff_ffff	   RapidIO		   512M
+ * 0xc000_0000	   0xdfff_ffff	   RapidIO or PCI express  512M
  * 0xe000_0000	   0xe000_ffff	   CCSR			   1M
  * 0xe200_0000	   0xe2ff_ffff	   PCI1 IO		   16M
  * 0xe300_0000	   0xe3ff_ffff	   CAN			   16M
- * 0xf800_0000	   0xf80f_ffff	   BCSR			   1M
+ * 0xef00_0000	   0xefff_ffff     PCI express IO          16M
  * 0xfe00_0000	   0xffff_ffff	   FLASH (boot bank)	   32M
  *
  * Notes:

@@ -49,10 +49,17 @@ struct law_entry law_table[] = {
 	SET_LAW_ENTRY (2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
 	SET_LAW_ENTRY (3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
 	SET_LAW_ENTRY (4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
-	SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+#ifdef CONFIG_PCIE1
+	SET_LAW_ENTRY (5, CFG_PCIE1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+#else /* !CONFIG_PCIE1 */
+	SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+#endif /* CONFIG_PCIE1 */
 #ifdef CONFIG_CAN_DRIVER
-	SET_LAW_ENTRY (6, CFG_CAN_BASE, LAWAR_SIZE_16M, LAW_TRGT_IF_LBC),
+	SET_LAW_ENTRY (6, CFG_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
 #endif /* CONFIG_CAN_DRIVER */
+#ifdef CONFIG_PCIE1
+	SET_LAW_ENTRY (7, CFG_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1),
+#endif /* CONFIG_PCIE */
 };
 
 int num_law_entries = ARRAY_SIZE (law_table);
board/tqc/tqm85xx/tlb.c +30 -0
index dc36201..7c4b9a1 100644
@@ -74,6 +74,24 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 3, BOOKE_PAGESZ_256M, 1),
 
+#ifdef CONFIG_PCIE1
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xc0000000	256M	PCI express MEM First half
+	 */
+	SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 5:	256M	Non-cacheable, guarded
+	 * 0xd0000000	256M	PCI express MEM Second half
+	 */
+	SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE + 0x10000000,
+		       CFG_PCIE1_MEM_BASE + 0x10000000,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 5, BOOKE_PAGESZ_256M, 1),
+#else /* !CONFIG_PCIE */
 	/*
 	 * TLB 4:	256M	Non-cacheable, guarded
 	 * 0xc0000000	256M	Rapid IO MEM First half

@@ -90,6 +108,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		       CFG_RIO_MEM_BASE + 0x10000000,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 5, BOOKE_PAGESZ_256M, 1),
+#endif /* CONFIG_PCIE */
 
 	/*
 	 * TLB 6:	 64M	Non-cacheable, guarded

@@ -116,6 +135,17 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		       CFG_DDR_SDRAM_BASE + 0x10000000,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 8, BOOKE_PAGESZ_256M, 1),
+
+#ifdef CONFIG_PCIE1
+	/*
+	 * TLB 9:	 16M	Non-cacheable, guarded
+	 * 0xef000000	 16M	PCI express IO
+	 */
+	SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 9, BOOKE_PAGESZ_16M, 1),
+#endif /* CONFIG_PCIE */
+
 };
 
 int num_tlb_entries = ARRAY_SIZE (tlb_table);
board/tqc/tqm85xx/tqm85xx.c +174 -31

247 lines not on this page · raw message

include/configs/TQM85xx.h +34 -1
index da06ffd..6e62c34 100644
@@ -42,6 +42,14 @@
 #define CONFIG_MPC85xx		1	/* MPC8540/60/55/41		*/
 
 #define CONFIG_PCI
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code	*/
+#define CONFIG_PCIX_CHECK		/* PCIX olny works at 66 MHz	*/
+#ifdef CONFIG_TQM8548
+#define CONFIG_PCI1
+#define CONFIG_PCIE1
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata	*/
+#endif
+
 #define CONFIG_TSEC_ENET		/* tsec ethernet support	*/
 
 #define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/

@@ -97,6 +105,10 @@
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
+#define CFG_PCI1_ADDR		(CFG_CCSRBAR + 0x8000)
+#define CFG_PCI2_ADDR		(CFG_CCSRBAR + 0x9000)
+#define CFG_PCIE1_ADDR		(CFG_CCSRBAR + 0xa000)
+
 /*
  * DDR Setup
  */

@@ -282,10 +294,12 @@
 #define CFG_DTT_LOW_TEMP	-30
 #define CFG_DTT_HYSTERESIS	3
 
+#ifndef CONFIG_PCIE1
 /* RapidIO MMU */
 #define CFG_RIO_MEM_BASE	0xc0000000	/* base address		*/
 #define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
-#define CFG_RIO_MEM_SIZE	0x20000000	/* 128M			*/
+#define CFG_RIO_MEM_SIZE	0x20000000	/* 512M			*/
+#endif /* CONFIG_PCIE1 */
 
 /*
  * General PCI

@@ -298,6 +312,25 @@
 #define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
 #define CFG_PCI1_IO_SIZE	0x1000000	/*  16M			*/
 
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS	0x00000000
+#define CFG_PCI_MEMORY_PHYS	0x00000000
+#define CFG_PCI_MEMORY_SIZE	0x80000000
+
+#ifdef CONFIG_PCIE1
+/*
+ * General PCI express
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCIE1_MEM_BASE	0xc0000000
+#define CFG_PCIE1_MEM_PHYS	CFG_PCIE1_MEM_BASE
+#define CFG_PCIE1_MEM_SIZE	0x20000000      /* 512M                 */
+#define CFG_PCIE1_IO_BASE	0xef000000
+#define CFG_PCIE1_IO_PHYS	CFG_PCIE1_IO_BASE
+#define CFG_PCIE1_IO_SIZE	0x1000000       /* 16M                  */
+
+#endif /* CONFIG_PCIE1 */
+
 #if defined(CONFIG_PCI)
 
 #define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
Signature · 1 line
1.5.2.2
author
#11 lore raw

PATCH 1/1 TQM85xx: NAND support via local bus UPMB

This patch adds support for NAND FLASH on the TQM8548. It is disabled by default and can be enabled for the TQM8548 modules. Note that the R/B pin is not supported by that module requiring to use the specified maximum delay time.

Note: With NAND support enabled the size of the U-Boot image exceeds 256 KB and TEXT_BASE must therefore be set to 0xfff80000 in config.mk, doubling the image size :-(.

Signed-off-by Thomas Waehner <[email protected]>
Signed-off-by Wolfgang Grandegger <[email protected]>
---
 board/tqc/tqm85xx/Makefile |    8 +-
 board/tqc/tqm85xx/law.c    |    6 +-
 board/tqc/tqm85xx/nand.c   |  597 ++++++++++++++++++++++++++++++++++++++++++++
 board/tqc/tqm85xx/tlb.c    |    2 +-
 include/configs/TQM85xx.h  |   80 ++++++-
 include/mpc85xx.h          |    4 +
 6 files changed, 689 insertions(+), 8 deletions(-)
 create mode 100644 board/tqc/tqm85xx/nand.c
board/tqc/tqm85xx/Makefile +7 -1
index 52f5ef9..8ea07f2 100644
@@ -25,8 +25,14 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o sdram.o law.o tlb.o
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= sdram.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
 
+COBJS-$(CONFIG_NAND) += nand.o
+
+COBJS	:= $(COBJS-y)
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
board/tqc/tqm85xx/law.c +3 -3
index bec1ed5..914ce68 100644
@@ -35,7 +35,7 @@
  * 0xc000_0000	   0xdfff_ffff	   RapidIO or PCI express  512M
  * 0xe000_0000	   0xe000_ffff	   CCSR			   1M
  * 0xe200_0000	   0xe2ff_ffff	   PCI1 IO		   16M
- * 0xe300_0000	   0xe3ff_ffff	   CAN			   16M
+ * 0xe300_0000	   0xe3ff_ffff	   CAN and NAND Flash	   16M
  * 0xef00_0000	   0xefff_ffff     PCI express IO          16M
  * 0xfe00_0000	   0xffff_ffff	   FLASH (boot bank)	   32M
  *

@@ -54,9 +54,9 @@ struct law_entry law_table[] = {
 #else /* !CONFIG_PCIE1 */
 	SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 #endif /* CONFIG_PCIE1 */
-#ifdef CONFIG_CAN_DRIVER
+#if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND)
 	SET_LAW_ENTRY (6, CFG_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
-#endif /* CONFIG_CAN_DRIVER */
+#endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */
 #ifdef CONFIG_PCIE1
 	SET_LAW_ENTRY (7, CFG_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1),
 #endif /* CONFIG_PCIE */
board/tqc/tqm85xx/nand.c new file +597 -0

597 lines not on this page · raw message

board/tqc/tqm85xx/tlb.c +1 -1
index 7c4b9a1..7f4efc1 100644
@@ -114,7 +114,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * TLB 6:	 64M	Non-cacheable, guarded
 	 * 0xe0000000	  1M	CCSRBAR
 	 * 0xe2000000	 16M	PCI1 IO
-	 * 0xe3000000	 16M	CAN
+	 * 0xe3000000	 16M	CAN and NAND Flash
 	 */
 	SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
include/configs/TQM85xx.h +77 -3

111 lines not on this page · raw message

include/mpc85xx.h +4 -0
index c2a7510..d76957d 100644
@@ -50,6 +50,7 @@
 #define ORxG_CSNT	0x00000800	/* Chip Select Negation Time	*/
 
 #define ORxU_EAD	0x00000001	/* External addr latch delay	*/
+#define ORxU_EHTR	0x00000002	/* extended hold time on read	*/
 #define ORxU_BI		0x00000100	/* Burst Inhibit		*/
 #define ORxU_AM_MSK	0xffff8000	/* Address Mask Mask		*/
 

@@ -60,7 +61,10 @@
 #define MxMR_DSx_2_CYCL 0x00400000	/* 2 cycle Disable Period	*/
 #define MxMR_DSx_3_CYCL 0x00800000	/* 3 cycle Disable Period	*/
 #define MxMR_DSx_4_CYCL 0x00C00000	/* 4 cycle Disable Period	*/
+#define MxMR_OP_MSK	0x30000000	/* Command opcode mask		*/
 #define MxMR_OP_WARR	0x10000000	/* Write to Array		*/
+#define MxMR_OP_RARR	0x20000000	/* Write to Array		*/
+#define MxMR_OP_RUN	0x30000000	/* Write to Array		*/
 #define MxMR_BSEL	0x80000000	/* Bus Select			*/
 
 /* helpers to convert values into an OR address mask (GPCM mode) */
Signature · 1 line
1.5.2.2
author
#12 lore raw

PATCH 1/1 TQM85xx: Change memory map to support Flash memory > 128 MiB

Some TQM85xx boards could be equipped with up to 1 GiB (NOR) Flash memory. The current memory map only supports up to 128 MiB Flash. This patch adds the configuration option CONFIG_TQM_BIGFLASH. If set, up to 1 GiB flash is supported. To achieve this, the memory map has to be adjusted in great parts (for example the CCSRBAR is moved from 0xE0000000 to 0xA0000000).

If you want to boot Linux with CONFIG_TQM_BIGFLASH set, the new memory map also has to be considered in the kernel (changed CCSRBAR address, changed PCI IO base address, ...). Please use an appropriate Flat Device Tree blob (tqm8548.dtb).

Signed-off-by Martin Krause <[email protected]>
Signed-off-by Wolfgang Grandegger <[email protected]>
---
 board/tqc/tqm85xx/law.c   |   29 ++++++++++++--
 board/tqc/tqm85xx/tlb.c   |   97 +++++++++++++++++++++++++++++++++++++++++++++
 include/configs/TQM85xx.h |   52 +++++++++++++++++++++---
 3 files changed, 167 insertions(+), 11 deletions(-)
board/tqc/tqm85xx/law.c +25 -4
index 914ce68..b4e663b 100644
@@ -30,6 +30,8 @@
 /*
  * LAW(Local Access Window) configuration:
  *
+ * Standard mapping:
+ *
  * 0x0000_0000	   0x7fff_ffff	   DDR			   2G
  * 0x8000_0000	   0x9fff_ffff	   PCI1 MEM		   512M
  * 0xc000_0000	   0xdfff_ffff	   RapidIO or PCI express  512M

@@ -37,22 +39,41 @@
  * 0xe200_0000	   0xe2ff_ffff	   PCI1 IO		   16M
  * 0xe300_0000	   0xe3ff_ffff	   CAN and NAND Flash	   16M
  * 0xef00_0000	   0xefff_ffff     PCI express IO          16M
- * 0xfe00_0000	   0xffff_ffff	   FLASH (boot bank)	   32M
+ * 0xfc00_0000	   0xffff_ffff	   FLASH (boot bank)	   128M
+ *
+ * Big FLASH mapping:
+ *
+ * 0x0000_0000	   0x7fff_ffff	   DDR			   2G
+ * 0x8000_0000	   0x9fff_ffff	   PCI1 MEM		   512M
+ * 0xa000_0000	   0xa000_ffff	   CCSR			   1M
+ * 0xa200_0000	   0xa2ff_ffff	   PCI1 IO		   16M
+ * 0xa300_0000	   0xa3ff_ffff	   CAN and NAND Flash	   16M
+ * 0xaf00_0000	   0xafff_ffff     PCI express IO          16M
+ * 0xb000_0000	   0xbfff_ffff	   RapidIO or PCI express  256M
+ * 0xc000_0000	   0xffff_ffff	   FLASH (boot bank)	   1G
  *
  * Notes:
  *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
  *    If flash is 8M at default position (last 8M), no LAW needed.
  */
 
+#ifdef CONFIG_TQM_BIGFLASH
+#define LAW_3_SIZE LAW_SIZE_1G
+#define LAW_5_SIZE LAW_SIZE_256M
+#else
+#define LAW_3_SIZE LAW_SIZE_128M
+#define LAW_5_SIZE LAW_SIZE_512M
+#endif
+
 struct law_entry law_table[] = {
 	SET_LAW_ENTRY (1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
 	SET_LAW_ENTRY (2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW_ENTRY (3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+	SET_LAW_ENTRY (3, CFG_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC),
 	SET_LAW_ENTRY (4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
 #ifdef CONFIG_PCIE1
-	SET_LAW_ENTRY (5, CFG_PCIE1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW_ENTRY (5, CFG_PCIE1_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1),
 #else /* !CONFIG_PCIE1 */
-	SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+	SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO),
 #endif /* CONFIG_PCIE1 */
 #if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND)
 	SET_LAW_ENTRY (6, CFG_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
board/tqc/tqm85xx/tlb.c +97 -0

109 lines not on this page · raw message

include/configs/TQM85xx.h +45 -7

126 lines not on this page · raw message

Signature · 1 line
1.5.2.2
#13 lore raw

PATCH 1/1 TQM85xx: NAND support via local bus UPMB

In reply to Wolfgang Grandegger
Quoted 8 lines · Wolfgang Grandegger

This patch adds support for NAND FLASH on the TQM8548. It is disabled by default and can be enabled for the TQM8548 modules. Note that the R/B pin is not supported by that module requiring to use the specified maximum delay time.

Note: With NAND support enabled the size of the U-Boot image exceeds 256 KB and TEXT_BASE must therefore be set to 0xfff80000 in config.mk, doubling the image size :-(.

What does this do differently from the code in drivers/mtd/nand/fsl_upm.c?

How much of this is board-specific?

-Scott

author
#14 lore raw

PATCH 1/1 TQM85xx: NAND support via local bus UPMB

Quoted 11 lines · Scott Wood
Quoted 8 lines · Wolfgang Grandegger

This patch adds support for NAND FLASH on the TQM8548. It is disabled by default and can be enabled for the TQM8548 modules. Note that the R/B pin is not supported by that module requiring to use the specified maximum delay time.

Note: With NAND support enabled the size of the U-Boot image exceeds 256 KB and TEXT_BASE must therefore be set to 0xfff80000 in config.mk, doubling the image size :-(.

What does this do differently from the code in drivers/mtd/nand/fsl_upm.c?

Maybe it does not support multi banks on a NAND chip. I have to check.

Quoted 1 line

How much of this is board-specific?

Well, I already gave drivers/mtd/nand/fsl_upm.c a try but was unable to get it working on this board. Therefore I decided to keep this known to work driver which we have already for a while.

With Linux, I had more success.

Wolfgang.

#15 lore raw

PATCH 1/1 TQM85xx: NAND support via local bus UPMB

Quoted 7 lines · Wolfgang Grandegger
Quoted 6 lines · Scott Wood
Quoted 5 lines · Wolfgang Grandegger

This patch adds support for NAND FLASH on the TQM8548. It is disabled by default and can be enabled for the TQM8548 modules. Note that the R/B pin is not supported by that module requiring to use the specified maximum delay time.

Quoted 7 lines
Quoted 5 lines
Quoted 3 lines

Note: With NAND support enabled the size of the U-Boot image exceeds 256 KB and TEXT_BASE must therefore be set to 0xfff80000 in config.mk, doubling the image size :-(.

What does this do differently from the code in drivers/mtd/nand/fsl_upm.c?

Maybe it does not support multi banks on a NAND chip. I have to check.

Me thinks that you'll have to call fsl_upm_nand_init() for each chip, and that's all. If not, feel free to patch it as you feel appropriate, I'll able to regress-test this driver on MPC8360E-RDK.

Quoted 5 lines
Quoted 1 line

How much of this is board-specific?

Well, I already gave drivers/mtd/nand/fsl_upm.c a try but was unable to get it working on this board. Therefore I decided to keep this known to work driver which we have already for a while.

This isn't really an excuse to duplicate drivers. :-) This driver was tested on MPC8555 and MPC8360 CPUs, so it should work with no drastic changes. Some issues might still be there, and if so, fixes are highly appreciated.

Quoted 1 line

With Linux, I had more success.

..especially if general idea works well, we should use single driver.

Thanks,

Signature · 3 lines
Anton Vorontsov
email: cbouatmailru at gmail.com
irc://irc.freenode.net/bd2
author
#16 lore raw

PATCH 1/1 TQM85xx: NAND support via local bus UPMB

Quoted 11 lines · Anton Vorontsov
Quoted 10 lines · Wolfgang Grandegger
Quoted 9 lines · Scott Wood
Quoted 8 lines · Wolfgang Grandegger

This patch adds support for NAND FLASH on the TQM8548. It is disabled by default and can be enabled for the TQM8548 modules. Note that the R/B pin is not supported by that module requiring to use the specified maximum delay time.

Note: With NAND support enabled the size of the U-Boot image exceeds 256 KB and TEXT_BASE must therefore be set to 0xfff80000 in config.mk, doubling the image size :-(.

Quoted 6 lines
Quoted 2 lines
Quoted 1 line

What does this do differently from the code in drivers/mtd/nand/fsl_upm.c?

Maybe it does not support multi banks on a NAND chip. I have to check.

Me thinks that you'll have to call fsl_upm_nand_init() for each chip, and that's all. If not, feel free to patch it as you feel appropriate, I'll able to regress-test this driver on MPC8360E-RDK.

That seems not to be a minor problem. If CFG_MAX_NAND_DEVICE > 1, board_nand_init() will be called twice with the base address from CFG_NAND_BASE_LIST. The only problem I see is that the UPM interface is setup twice.

Quoted 9 lines
Quoted 4 lines
Quoted 1 line

How much of this is board-specific?

Well, I already gave drivers/mtd/nand/fsl_upm.c a try but was unable to get it working on this board. Therefore I decided to keep this known to work driver which we have already for a while.

This isn't really an excuse to duplicate drivers. :-) This driver was tested on MPC8555 and MPC8360 CPUs, so it should work with no drastic changes. Some issues might still be there, and if so, fixes are highly appreciated.

I know, sniff.

Quoted 3 lines
Quoted 1 line

With Linux, I had more success.

..especially if general idea works well, we should use single driver.

I already had a closer look and realized a difference in writing the UPM array. In fsl_upm.c there is:

static void fsl_upm_setup(struct fsl_upm *upm)

  {
	int i;

	/* write upm array */
	out_be32(upm->mxmr, FSL_UPM_MxMR_OP_WA);

	for (i = 0; i < 64; i++) {
		out_be32(upm->mdr, upm->array[i]);
		out_8(upm->io_addr, 0x0);
	}

	/* normal operation */
	out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO);
	while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO)
		eieio();

}

But in my driver I fold the machine address into mbmr for each value:

        out_be32 (&lbc->mbmr,
                 (in_be32 (&lbc->mbmr) & ~(MxMR_OP_NORM | MxMR_MAD)) |
                  MxMR_OP_WARR | (i & MxMR_MAD));
                                  ^

Seem also that defines a duplicated :-(.

Has it been tested with an MPC85xx? I will do some more test now.

Wolfgang.

#17 lore raw

PATCH 1/1 TQM85xx: NAND support via local bus UPMB

Quoted 15 lines · Wolfgang Grandegger
Quoted 14 lines · Anton Vorontsov
Quoted 12 lines · Wolfgang Grandegger
Quoted 10 lines · Scott Wood
Quoted 8 lines · Wolfgang Grandegger

This patch adds support for NAND FLASH on the TQM8548. It is disabled by default and can be enabled for the TQM8548 modules. Note that the R/B pin is not supported by that module requiring to use the specified maximum delay time.

Note: With NAND support enabled the size of the U-Boot image exceeds 256 KB and TEXT_BASE must therefore be set to 0xfff80000 in config.mk, doubling the image size :-(.

What does this do differently from the code in drivers/mtd/nand/fsl_upm.c?

Maybe it does not support multi banks on a NAND chip. I have to check.

Quoted 8 lines
Quoted 3 lines

Me thinks that you'll have to call fsl_upm_nand_init() for each chip, and that's all. If not, feel free to patch it as you feel appropriate, I'll able to regress-test this driver on MPC8360E-RDK.

That seems not to be a minor problem. If CFG_MAX_NAND_DEVICE > 1, board_nand_init() will be called twice with the base address from CFG_NAND_BASE_LIST. The only problem I see is that the UPM interface is setup twice.

Personally I think we should remove UPM programming code from the fsl_upm_nand.c, and program the UPM via its own interface, see this post:

From: David Saada <[email protected]>
To: "'u-boot-users at lists.sourceforge.net'" <[email protected]>
Date: Mon, 19 May 2008 19:05:04 +0300
Subject: [U-Boot-Users] [PATCH][resubmit] MPC85xx, MPC83xx: Add/Fix UPM configuration support

^^^ But this is still WIP, and I'm not sure if this is suitable for our needs (didn't try it).

Quoted 35 lines
Quoted 9 lines
Quoted 4 lines
Quoted 1 line

How much of this is board-specific?

Well, I already gave drivers/mtd/nand/fsl_upm.c a try but was unable to get it working on this board. Therefore I decided to keep this known to work driver which we have already for a while.

This isn't really an excuse to duplicate drivers. :-) This driver was tested on MPC8555 and MPC8360 CPUs, so it should work with no drastic changes. Some issues might still be there, and if so, fixes are highly appreciated.

I know, sniff.

Quoted 3 lines
Quoted 1 line

With Linux, I had more success.

..especially if general idea works well, we should use single driver.

I already had a closer look and realized a difference in writing the UPM array. In fsl_upm.c there is:

static void fsl_upm_setup(struct fsl_upm *upm)

  {
	int i;

	/* write upm array */
	out_be32(upm->mxmr, FSL_UPM_MxMR_OP_WA);

	for (i = 0; i < 64; i++) {
		out_be32(upm->mdr, upm->array[i]);
		out_8(upm->io_addr, 0x0);
	}

	/* normal operation */
	out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO);
	while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO)
		eieio();
Quoted 8 lines

}

But in my driver I fold the machine address into mbmr for each value:

        out_be32 (&lbc->mbmr,
                 (in_be32 (&lbc->mbmr) & ~(MxMR_OP_NORM | MxMR_MAD)) |
                  MxMR_OP_WARR | (i & MxMR_MAD));
                                  ^

I see. I think there will be a problem with a

static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset)

{
        out_be32(upm->mxmr, FSL_UPM_MxMR_OP_RP | pat_offset);
}

static void fsl_upm_end_pattern(struct fsl_upm *upm)

{
        out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO);
        while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO)
                eieio();
}

Since it zeroes these values. No problem though, this should be replaced by the Linux' versions, that is

clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RP | pat_offset); for start_pattern, and clrbits32(upm->mxmr, MxMR_OP_RP); for end_pattern.

So, this will leave your values intact, and will work for all boards as well.

Quoted 1 line

Seem also that defines a duplicated :-(.

No problem. Please, remove the ones you don't like, and leave the ones you do like. :-) Feel completely free to do everything you need to make fsl_upm_nand.c work on your hardware, and then we'll see what we can do to make our hardware work together.

As for UPM programming, as I've said, just remove UPM programming code from the NAND driver, and leave it in the board file until (if) we'll start using generic interface.

Quoted 1 line

Has it been tested with an MPC85xx? I will do some more test now.

Yup, MPC8555.

Signature · 3 lines
Anton Vorontsov
email: cbouatmailru at gmail.com
irc://irc.freenode.net/bd2
author
#18 lore raw

PATCH 1/1 TQM85xx: NAND support via local bus UPMB

Quoted 26 lines · Anton Vorontsov
Quoted 13 lines · Wolfgang Grandegger
Quoted 12 lines · Anton Vorontsov
Quoted 11 lines · Wolfgang Grandegger
Quoted 10 lines · Scott Wood
Quoted 8 lines · Wolfgang Grandegger

This patch adds support for NAND FLASH on the TQM8548. It is disabled by default and can be enabled for the TQM8548 modules. Note that the R/B pin is not supported by that module requiring to use the specified maximum delay time.

Note: With NAND support enabled the size of the U-Boot image exceeds 256 KB and TEXT_BASE must therefore be set to 0xfff80000 in config.mk, doubling the image size :-(.

What does this do differently from the code in drivers/mtd/nand/fsl_upm.c?

Quoted 8 lines
Quoted 4 lines
Quoted 1 line

Maybe it does not support multi banks on a NAND chip. I have to check.

Me thinks that you'll have to call fsl_upm_nand_init() for each chip, and that's all. If not, feel free to patch it as you feel appropriate, I'll able to regress-test this driver on MPC8360E-RDK.

That seems not to be a minor problem. If CFG_MAX_NAND_DEVICE > 1, board_nand_init() will be called twice with the base address from CFG_NAND_BASE_LIST. The only problem I see is that the UPM interface is setup twice.

Personally I think we should remove UPM programming code from the fsl_upm_nand.c, and program the UPM via its own interface, see this post:

Quoted 7 lines

From: David Saada <[email protected]>
To: "'u-boot-users at lists.sourceforge.net'" <[email protected]>
Date: Mon, 19 May 2008 19:05:04 +0300
Subject: [U-Boot-Users] [PATCH][resubmit] MPC85xx, MPC83xx: Add/Fix UPM configuration support

^^^ But this is still WIP, and I'm not sure if this is suitable for our needs (didn't try it).

OK.

Quoted 57 lines
Quoted 31 lines
Quoted 8 lines
Quoted 4 lines
Quoted 1 line

How much of this is board-specific?

Well, I already gave drivers/mtd/nand/fsl_upm.c a try but was unable to get it working on this board. Therefore I decided to keep this known to work driver which we have already for a while.

This isn't really an excuse to duplicate drivers. :-) This driver was tested on MPC8555 and MPC8360 CPUs, so it should work with no drastic changes. Some issues might still be there, and if so, fixes are highly appreciated.

I know, sniff.

Quoted 2 lines
Quoted 1 line

With Linux, I had more success.

..especially if general idea works well, we should use single driver.

I already had a closer look and realized a difference in writing the UPM array. In fsl_upm.c there is:

static void fsl_upm_setup(struct fsl_upm *upm)

  {
	int i;

	/* write upm array */
	out_be32(upm->mxmr, FSL_UPM_MxMR_OP_WA);

	for (i = 0; i < 64; i++) {
		out_be32(upm->mdr, upm->array[i]);
		out_8(upm->io_addr, 0x0);
	}

	/* normal operation */
	out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO);
	while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO)
		eieio();
Quoted 8 lines

}

But in my driver I fold the machine address into mbmr for each value:

        out_be32 (&lbc->mbmr,
                 (in_be32 (&lbc->mbmr) & ~(MxMR_OP_NORM | MxMR_MAD)) |
                  MxMR_OP_WARR | (i & MxMR_MAD));
                                  ^

I see. I think there will be a problem with a

static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset)

{
        out_be32(upm->mxmr, FSL_UPM_MxMR_OP_RP | pat_offset);
}

static void fsl_upm_end_pattern(struct fsl_upm *upm)

{
        out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO);
        while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO)
                eieio();
}

Since it zeroes these values. No problem though, this should be replaced by the Linux' versions, that is

Quoted 6 lines

clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RP | pat_offset); for start_pattern, and clrbits32(upm->mxmr, MxMR_OP_RP); for end_pattern.

So, this will leave your values intact, and will work for all boards as well.

Fix that, but I can still not access the device properly. I'm a bit puzzled because it uses a different algorithm to access the device. While my and the Linux fsl_upm driver uses NAND_ALE, NAND_CLE and friends to manage the access via hwcontrol callback, the fsl_upm driver of U-Boot uses the cmdfunc callback doing different things. What is the difference? It seems to work on the MPC8555, at least, as you mention below.

Quoted 6 lines
Quoted 1 line

Seem also that defines a duplicated :-(.

No problem. Please, remove the ones you don't like, and leave the ones you do like. :-) Feel completely free to do everything you need to make fsl_upm_nand.c work on your hardware, and then we'll see what we can do to make our hardware work together.

OK. The defines should go to fsl_lbc.h nowadays.

Quoted 7 lines

As for UPM programming, as I've said, just remove UPM programming code from the NAND driver, and leave it in the board file until (if) we'll start using generic interface.

Quoted 1 line

Has it been tested with an MPC85xx? I will do some more test now.

Yup, MPC8555.

Wolfgang.

#19 lore raw

PATCH 1/1 TQM85xx: NAND support via local bus UPMB

On Fri, May 30, 2008 at 08:00:32PM +0200, Wolfgang Grandegger wrote:
[...]

Quoted 5 lines

Fix that, but I can still not access the device properly. I'm a bit puzzled because it uses a different algorithm to access the device. While my and the Linux fsl_upm driver uses NAND_ALE, NAND_CLE and friends to manage the access via hwcontrol callback, the fsl_upm driver of U-Boot uses the cmdfunc callback doing different things.

I wonder if your NAND chip is a large page one? Because currently fsl_upm_nand hardcodes OOB stuff (bad thing, but with old mtd subsystem I didn't find better way ;-).

As for u-boot and linux doing different things... with this patch u-boot and linux are identical:

http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot/u-boot-nand-flash.git;a=commitdiff;h=dffa9a8b31b2c21fd3a72ba1f58dd04911b95b6f

This is in U-Boot's mtd-2.6.22.1 branch though. :-/ Your approach with hwctl seem to be more universal (for old mtd subsystem), since it doesn't duplicate MTD cmdfunc, thus should work for all NAND chips...

Could you prepare a patch that replacing fsl_upm_nand.c's current logic with yours (that should work for your NAND chip), and I'll test it on MPC8360E-RDK?

Signature · 3 lines
Anton Vorontsov
email: cbouatmailru at gmail.com
irc://irc.freenode.net/bd2
author
#20 lore raw

PATCH 1/1 TQM85xx: NAND support via local bus UPMB

Quoted 11 lines · Anton Vorontsov

On Fri, May 30, 2008 at 08:00:32PM +0200, Wolfgang Grandegger wrote:
[...]

Quoted 5 lines

Fix that, but I can still not access the device properly. I'm a bit puzzled because it uses a different algorithm to access the device. While my and the Linux fsl_upm driver uses NAND_ALE, NAND_CLE and friends to manage the access via hwcontrol callback, the fsl_upm driver of U-Boot uses the cmdfunc callback doing different things.

I wonder if your NAND chip is a large page one? Because currently fsl_upm_nand hardcodes OOB stuff (bad thing, but with old mtd subsystem I didn't find better way ;-).

On my TQM8548 there is a Micron MT29F8G08FABWP, page size 2048 + 64 bytes, block size 128K + 4K bytes.

Quoted 8 lines

As for u-boot and linux doing different things... with this patch u-boot and linux are identical:

http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot/u-boot-nand-flash.git;a=commitdiff;h=dffa9a8b31b2c21fd3a72ba1f58dd04911b95b6f

This is in U-Boot's mtd-2.6.22.1 branch though. :-/ Your approach with hwctl seem to be more universal (for old mtd subsystem), since it doesn't duplicate MTD cmdfunc, thus should work for all NAND chips...

A closer look to the code confirms that.

Quoted 3 lines

Could you prepare a patch that replacing fsl_upm_nand.c's current logic with yours (that should work for your NAND chip), and I'll test it on MPC8360E-RDK?

The attached preliminary patch works for me. Compared to my specific driver, it saves start_pattern and end_pattern calls :-). It now also supports a bus width of 8, 16 and 32 bits and width is now in bits like in the Linux driver. I'm going to prepare a proper patch series beginning of next week.

Wolfgang.

author
#21 lore raw

PATCH 1/1 TQM85xx: NAND support via local bus UPMB

Quoted 30 lines · Wolfgang Grandegger
Quoted 10 lines · Anton Vorontsov

On Fri, May 30, 2008 at 08:00:32PM +0200, Wolfgang Grandegger wrote:
[...]

Quoted 5 lines

Fix that, but I can still not access the device properly. I'm a bit puzzled because it uses a different algorithm to access the device. While my and the Linux fsl_upm driver uses NAND_ALE, NAND_CLE and friends to manage the access via hwcontrol callback, the fsl_upm driver of U-Boot uses the cmdfunc callback doing different things.

I wonder if your NAND chip is a large page one? Because currently fsl_upm_nand hardcodes OOB stuff (bad thing, but with old mtd subsystem I didn't find better way ;-).

On my TQM8548 there is a Micron MT29F8G08FABWP, page size 2048 + 64 bytes, block size 128K + 4K bytes.

Quoted 8 lines

As for u-boot and linux doing different things... with this patch u-boot and linux are identical:

http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot/u-boot-nand-flash.git;a=commitdiff;h=dffa9a8b31b2c21fd3a72ba1f58dd04911b95b6f

This is in U-Boot's mtd-2.6.22.1 branch though. :-/ Your approach with hwctl seem to be more universal (for old mtd subsystem), since it doesn't duplicate MTD cmdfunc, thus should work for all NAND chips...

A closer look to the code confirms that.

Quoted 3 lines

Could you prepare a patch that replacing fsl_upm_nand.c's current logic with yours (that should work for your NAND chip), and I'll test it on MPC8360E-RDK?

Quoted 5 lines

The attached preliminary patch works for me. Compared to my specific driver, it saves start_pattern and end_pattern calls :-). It now also supports a bus width of 8, 16 and 32 bits and width is now in bits like in the Linux driver. I'm going to prepare a proper patch series beginning of next week.

Here is the missing patch:

---
 drivers/mtd/nand/fsl_upm.c |  132 +++++++++++++++++----------------------------
 include/asm-ppc/io.h       |   28 +++++++++
 2 files changed, 79 insertions(+), 81 deletions(-)
drivers/mtd/nand/fsl_upm.c +51 -81
Index: u-boot/drivers/mtd/nand/fsl_upm.c
===================================================================
@@ -20,112 +20,89 @@
 #include <linux/mtd/fsl_upm.h>
 #include <nand.h>
 
-#define FSL_UPM_MxMR_OP_NO (0 << 28) /* normal operation */
-#define FSL_UPM_MxMR_OP_WA (1 << 28) /* write array */
-#define FSL_UPM_MxMR_OP_RA (2 << 28) /* read array */
-#define FSL_UPM_MxMR_OP_RP (3 << 28) /* run pattern */
+static int fsl_upm_in_pattern;
 
 static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset)
 {
-	out_be32(upm->mxmr, FSL_UPM_MxMR_OP_RP | pat_offset);
+	clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RUN | pat_offset);
 }
 
 static void fsl_upm_end_pattern(struct fsl_upm *upm)
 {
-	out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO);
-	while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO)
+	clrbits32(upm->mxmr, MxMR_OP_RUN);
+
+	while (in_be32(upm->mxmr) & MxMR_OP_RUN)
 		eieio();
 }
 
 static void fsl_upm_run_pattern(struct fsl_upm *upm, int width, u32 cmd)
 {
-	out_be32(upm->mar, cmd << (32 - width * 8));
-	out_8(upm->io_addr, 0x0);
-}
-
-static void fsl_upm_setup(struct fsl_upm *upm)
-{
-	int i;
-
-	/* write upm array */
-	out_be32(upm->mxmr, FSL_UPM_MxMR_OP_WA);
-
-	for (i = 0; i < 64; i++) {
-		out_be32(upm->mdr, upm->array[i]);
-		out_8(upm->io_addr, 0x0);
+	out_be32(upm->mar, cmd << (32 - width));
+	switch (width) {
+	case 8:
+		out_8(io_base, 0x0);
+		break;
+	case 16:
+		out_be16(io_base, 0x0);
+		break;
+	case 32:
+		out_be32(io_base, 0x0);
+		break;
 	}
-
-	/* normal operation */
-	out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO);
-	while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO)
-		eieio();
 }
 
-static void fun_cmdfunc(struct mtd_info *mtd, unsigned command, int column,
-			int page_addr)
+static void nand_hwcontrol (struct mtd_info *mtd, int cmd)
 {
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_upm_nand *fun = chip->priv;
 
-	fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
-
-	if (command == NAND_CMD_SEQIN) {
-		int readcmd;
-
-		if (column >= mtd->oobblock) {
-			/* OOB area */
-			column -= mtd->oobblock;
-			readcmd = NAND_CMD_READOOB;
-		} else if (column < 256) {
-			/* First 256 bytes --> READ0 */
-			readcmd = NAND_CMD_READ0;
-		} else {
-			column -= 256;
-			readcmd = NAND_CMD_READ1;
-		}
-		fsl_upm_run_pattern(&fun->upm, fun->width, readcmd);
+	switch (cmd) {
+	case NAND_CTL_SETCLE:
+		fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
+		fsl_upm_in_pattern++;
+		break;
+	case NAND_CTL_SETALE:
+		fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
+		fsl_upm_in_pattern++;
+		break;
+	case NAND_CTL_CLRCLE:
+	case NAND_CTL_CLRALE:
+		fsl_upm_end_pattern(&fun->upm);
+		fsl_upm_in_pattern--;
+		break;
 	}
+#if 1
+	/* Temorary check */
+	if (fsl_upm_in_pattern < 0 || fsl_upm_in_pattern > 1)
+		printf("fsl_upm: Oops, unexpected fsl_upm_in_pattern %d\n",
+		       fsl_upm_in_pattern);
+#endif
+}
 
-	fsl_upm_run_pattern(&fun->upm, fun->width, command);
-
-	fsl_upm_end_pattern(&fun->upm);
-
-	fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
-
-	if (column != -1)
-		fsl_upm_run_pattern(&fun->upm, fun->width, column);
+static void nand_write_byte(struct mtd_info *mtd, u_char byte)
+{
+	struct nand_chip *chip = mtd->priv;
 
-	if (page_addr != -1) {
-		fsl_upm_run_pattern(&fun->upm, fun->width, page_addr);
-		fsl_upm_run_pattern(&fun->upm, fun->width,
-				    (page_addr >> 8) & 0xFF);
-		if (chip->chipsize > (32 << 20)) {
-			fsl_upm_run_pattern(&fun->upm, fun->width,
-					    (page_addr >> 16) & 0x0f);
-		}
-	}
+	if (fsl_upm_in_pattern) {
+		struct fsl_upm_nand *fun = chip->priv;
 
-	fsl_upm_end_pattern(&fun->upm);
+		fsl_upm_run_pattern(&fun->upm, fun->width, byte);
 
-	if (fun->wait_pattern) {
 		/*
 		 * Some boards/chips needs this. At least on MPC8360E-RDK we
 		 * need it. Probably weird chip, because I don't see any need
 		 * for this on MPC8555E + Samsung K9F1G08U0A. Usually here are
 		 * 0-2 unexpected busy states per block read.
 		 */
-		while (!fun->dev_ready())
-			debug("unexpected busy state\n");
+		if (fun->wait_pattern) {
+			while (!fun->dev_ready())
+				debug("unexpected busy state\n");
+		}
+	} else {
+		out_8(chip->IO_ADDR_W, byte);
 	}
 }
 
-static void nand_write_byte(struct mtd_info *mtd, u_char byte)
-{
-	struct nand_chip *chip = mtd->priv;
-
-	out_8(chip->IO_ADDR_W, byte);
-}
-
 static u8 nand_read_byte(struct mtd_info *mtd)
 {
 	struct nand_chip *chip = mtd->priv;

@@ -164,10 +141,6 @@ static int nand_verify_buf(struct mtd_in
 	return 0;
 }
 
-static void nand_hwcontrol(struct mtd_info *mtd, int cmd)
-{
-}
-
 static int nand_dev_ready(struct mtd_info *mtd)
 {
 	struct nand_chip *chip = mtd->priv;

@@ -179,15 +152,12 @@ static int nand_dev_ready(struct mtd_inf
 int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
 {
 	/* yet only 8 bit accessors implemented */
-	if (fun->width != 1)
+	if (fun->width != 8 && fun->width != 16 && fun->width != 32)
 		return -ENOSYS;
 
-	fsl_upm_setup(&fun->upm);
-
 	chip->priv = fun;
 	chip->chip_delay = fun->chip_delay;
 	chip->eccmode = NAND_ECC_SOFT;
-	chip->cmdfunc = fun_cmdfunc;
 	chip->hwcontrol = nand_hwcontrol;
 	chip->read_byte = nand_read_byte;
 	chip->read_buf = nand_read_buf;
include/asm-ppc/io.h +28 -0
Index: u-boot/include/asm-ppc/io.h
===================================================================
@@ -238,6 +238,34 @@ extern inline void out_be32(volatile uns
 	__asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
 }
 
+/* access ports */
+#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) |  (_v))
+#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
+
+#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) |  (_v))
+#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
+
+#define setbits8(_addr, _v) out_8((_addr), in_8(_addr) |  (_v))
+#define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
+
+/* Clear and set bits in one shot.  These macros can be used to clear and
+ * set multiple bits in a register using a single read-modify-write.  These
+ * macros can also be used to set a multiple-bit bit pattern using a mask,
+ * by specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrsetbits(type, addr, clear, set) \
+	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
 /*
  * Given a physical address and a length, return a virtual address
  * that can be used to access the memory range with the caching
author
#22 lore raw

PATCH 1/1 TQM85xx: NAND support via local bus UPMB

In reply to Anton Vorontsov
Quoted 17 lines · Anton Vorontsov

On Fri, May 30, 2008 at 08:00:32PM +0200, Wolfgang Grandegger wrote:
[...]

Quoted 5 lines

Fix that, but I can still not access the device properly. I'm a bit puzzled because it uses a different algorithm to access the device. While my and the Linux fsl_upm driver uses NAND_ALE, NAND_CLE and friends to manage the access via hwcontrol callback, the fsl_upm driver of U-Boot uses the cmdfunc callback doing different things.

I wonder if your NAND chip is a large page one? Because currently fsl_upm_nand hardcodes OOB stuff (bad thing, but with old mtd subsystem I didn't find better way ;-).

As for u-boot and linux doing different things... with this patch u-boot and linux are identical:

http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot/u-boot-nand-flash.git;a=commitdiff;h=dffa9a8b31b2c21fd3a72ba1f58dd04911b95b6f

Quoted 7 lines

This is in U-Boot's mtd-2.6.22.1 branch though. :-/ Your approach with hwctl seem to be more universal (for old mtd subsystem), since it doesn't duplicate MTD cmdfunc, thus should work for all NAND chips...

Could you prepare a patch that replacing fsl_upm_nand.c's current logic with yours (that should work for your NAND chip), and I'll test it on MPC8360E-RDK?

Here we go. I'm going to send 4 patches that work for me on my TQM8548 module. Could you please give it a try?

Thanks,

Wolfgang.

author
#24 lore raw

PATCH 1/1 MPC85xx: Beatify boot output of L2 cache configuration

Quoted 10 lines · Andy Fleming
Quoted 7 lines · Wolfgang Grandegger

The boot output is now aligned poperly with other boot output lines, e.g.:

FLASH: 128 MB
L2: 512 KB enabled

Signed-off-by Wolfgang Grandegger <[email protected]>

A silly comment, but let's spell it "Beautify"

Of course, I didn't want to beatify this part of the code. New patch will follow.

BTW: what is the correct way to send an updated version of a patch. Should the subject be unchanged or is adding "v2" to [PATCH] preferred.

Wolfgang.

#25 lore raw

PATCH 1/1 MPC85xx: Beatify boot output of L2 cache configuration

Hi Wolfgang,

Quoted 10 lines
Quoted 9 lines · Andy Fleming
Quoted 7 lines · Wolfgang Grandegger

The boot output is now aligned poperly with other boot output lines, e.g.:

FLASH: 128 MB
L2: 512 KB enabled

Signed-off-by Wolfgang Grandegger <[email protected]>
Quoted 7 lines
Quoted 1 line

A silly comment, but let's spell it "Beautify"

Of course, I didn't want to beatify this part of the code. New patch will follow.

BTW: what is the correct way to send an updated version of a patch. Should the subject be unchanged or is adding "v2" to [PATCH] preferred.

Please change the subject, so it is easier to follow what iteration is being discussed. git-format-patch will help out nicely here:

git-format-patch --subject-prefix="PATCH v2" ...

Cheers
Detlev

Signature · 8 lines
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involves massive death and destruction. When you see it, you'll know it.
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