MIPS updates

GIT PULL Applied Shinya Kuribayashi 2 participants 2 messages Jun 7, 2008 – Jun 11, 2008

Subsystems (2)

Network drivers Arm/actions semi architecture

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Shinya Kuribayashi

author

2008-06-07 01:19 UTC #0 lore raw

Please pull MIPS updates to pick up the following patches.

The following changes since commit 8155efbd7ae9c65564ca98affe94631d612ae088:
Wolfgang Denk (1):
Merge branch 'master' of ssh://mercury/home/wd/git/u-boot/master

are available in the git repository at:

git://git.denx.de/u-boot-mips.git master

Shinya Kuribayashi (8):
[MIPS] lib_mips/time.c: Replace CP0 access functions with existing macros [MIPS] lib_mips/time.c: Fix udelay
[MIPS] lib_mips/time.c: Fix CP0 count register usage and timer routines [MIPS] Kill unused <version.h> inclusions
[MIPS] mips_config.mk: Misc fixes
[MIPS] Update <asm/addrspace.h> header
[MIPS] Rename Alchemy processor configs into CONFIGO_SOC_* [MIPS] cpu/mips/Makefile: Split [CS]OBJS onto separate lines

 board/dbau1x00/lowlevel_init.S  |    1 -
 board/gth2/gth2.c               |    2 +-
 board/gth2/lowlevel_init.S      |    1 -
 board/incaip/incaip.c           |    2 +-
 board/incaip/lowlevel_init.S    |    1 -
 board/pb1x00/lowlevel_init.S    |    1 -
 board/purple/lowlevel_init.S    |    1 -
 board/purple/purple.c           |   14 ++--
 board/qemu-mips/lowlevel_init.S |    1 -
 board/tb0229/lowlevel_init.S    |    1 -
 board/tb0229/vr4131-pci.c       |   56 ++++++------
 cpu/mips/Makefile               |   15 ++--
 cpu/mips/asc_serial.c           |    3 -
 cpu/mips/au1x00_eth.c           |   12 +--
 cpu/mips/au1x00_serial.c        |    4 -
 cpu/mips/au1x00_usb_ohci.c      |    2 +-
 cpu/mips/cache.S                |    7 +-
 cpu/mips/incaip_wdt.S           |    1 -
 cpu/mips/start.S                |    1 -
 drivers/net/inca-ip_sw.c        |   28 +++---
 include/asm-mips/addrspace.h    |  173 +++++++++++++++++++++++++++++----------
 include/asm-mips/au1x00.h       |    6 +-
 include/asm-mips/io.h           |    4 +-
 include/configs/dbau1x00.h      |   14 ++--
 include/configs/gth2.h          |    8 +-
 include/configs/incaip.h        |    4 +-
 include/configs/pb1x00.h        |   12 ++-
 include/configs/purple.h        |    3 +-
 include/configs/qemu-mips.h     |    4 +-
 include/configs/tb0229.h        |    4 +-
 lib_mips/time.c                 |   57 ++++++-------
 mips_config.mk                  |    7 +-
 32 files changed, 263 insertions(+), 187 deletions(-)

board/dbau1x00/lowlevel_init.S +0 -1

index 27b51f7..13e6bfc 100644
@@ -1,7 +1,6 @@
 /* Memory sub-system initialization code */
 
 #include <config.h>
-#include <version.h>
 #include <asm/regdef.h>
 #include <asm/au1x00.h>
 #include <asm/mipsregs.h>

board/gth2/gth2.c +1 -1

index 9bc4d3f..3e56678 100644
@@ -36,7 +36,7 @@ static int wdi_status = 0;
 #define SDRAM_SIZE ((64*1024*1024)-(12*4096))
 
 
-#define SERIAL_LOG_BUFFER KSEG1ADDR(SDRAM_SIZE + (8*4096))
+#define SERIAL_LOG_BUFFER CKSEG1ADDR(SDRAM_SIZE + (8*4096))
 
 void inline log_serial_char(char c){
 	char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER;

board/gth2/lowlevel_init.S +0 -1

index bf615c1..4c4f0eb 100644
@@ -1,7 +1,6 @@
 /* Memory sub-system initialization code */
 
 #include <config.h>
-#include <version.h>
 #include <asm/regdef.h>
 #include <asm/au1x00.h>
 #include <asm/mipsregs.h>

board/incaip/incaip.c +1 -1

index c624b3d..dc51373 100644
@@ -63,7 +63,7 @@ long int initdram(int board_type)
 
 		/* Can't probe for RAM size unless we are running from Flash.
 		 */
-	if (PHYSADDR(our_address) < PHYSADDR(PHYS_FLASH_1))
+	if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
 	{
 		return max_sdram_size();
 	}

board/incaip/lowlevel_init.S +0 -1

index 08f7f21..fe525ec 100644
@@ -23,7 +23,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 #include <asm/regdef.h>

board/pb1x00/lowlevel_init.S +0 -1

index 98bb394..b145e43 100644
@@ -1,7 +1,6 @@
 /* Memory sub-system initialization code */
 
 #include <config.h>
-#include <version.h>
 #include <asm/regdef.h>
 #include <asm/au1x00.h>
 #include <asm/mipsregs.h>

board/purple/lowlevel_init.S +0 -1

index b9d03fc..1bd3edb 100644
@@ -23,7 +23,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 #include <asm/regdef.h>
 
 #define MC_IOGP	0xBF800800

board/purple/purple.c +7 -7

index 89cb906..72d5734 100644
@@ -85,16 +85,16 @@ static void sdram_timing_init (ulong size)
 			while (p4 < 32 && done == 0) {
 			    WRITE_MC_IOGP_1;
 
-			    for (addr = KSEG1 + 0x4000;
-				 addr < KSEG1ADDR (size);
+			    for (addr = CKSEG1 + 0x4000;
+				 addr < CKSEG1ADDR (size);
 				 addr = addr + 4) {
 					*(uint *) addr = 0xaa55aa55;
 			    }
 
 			    pass = 1;
 
-			    for (addr = KSEG1 + 0x4000;
-				 addr < KSEG1ADDR (size) && pass == 1;
+			    for (addr = CKSEG1 + 0x4000;
+				 addr < CKSEG1ADDR (size) && pass == 1;
 				 addr = addr + 4) {
 					if (*(uint *) addr != 0xaa55aa55)
 						pass = 0;

@@ -138,7 +138,7 @@ long int initdram(int board_type)
 	ulong	size	= (1 << (rows + cols)) * (1 << (dw - 1)) * CFG_NB;
 	void (*  sdram_init) (ulong);
 
-	sdram_init = (void (*)(ulong)) KSEG0ADDR(&sdram_timing_init);
+	sdram_init = (void (*)(ulong)) CKSEG0ADDR(&sdram_timing_init);
 
 	sdram_init(0x10000);

@@ -260,14 +260,14 @@ void copy_code (ulong dest_addr)
 	/* flush caches
 	 */
 
-	start = KSEG0;
+	start = CKSEG0;
 	end = start + CFG_DCACHE_SIZE;
 	while(start < end) {
 		cache_unroll(start,Index_Writeback_Inv_D);
 		start += CFG_CACHELINE_SIZE;
 	}
 
-	start = KSEG0;
+	start = CKSEG0;
 	end = start + CFG_ICACHE_SIZE;
 	while(start < end) {
 		cache_unroll(start,Index_Invalidate_I);

board/qemu-mips/lowlevel_init.S +0 -1

index 836e027..b0f7072 100644
@@ -1,7 +1,6 @@
 /* Memory sub-system initialization code */
 
 #include <config.h>
-#include <version.h>
 #include <asm/regdef.h>
 #include <asm/mipsregs.h>

board/tb0229/lowlevel_init.S +0 -1

index df31806..5fce856 100644
@@ -10,7 +10,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 #include <asm/regdef.h>

board/tb0229/vr4131-pci.c +28 ~~-28~~

62 lines not on this page · raw message

cpu/mips/Makefile +9 -6

index 92dcc16..5091781 100644
@@ -25,13 +25,16 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(CPU).a
 
-START	= start.o
-COBJS	= asc_serial.o au1x00_serial.o au1x00_eth.o au1x00_usb_ohci.o \
-	  cpu.o interrupts.o incaip_clock.o
-SOBJS	= incaip_wdt.o cache.o
+SOBJS-y	= cache.o
+COBJS-y	= cpu.o interrupts.o
 
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+SOBJS-$(CONFIG_INCA_IP)	+= incaip_wdt.o
+COBJS-$(CONFIG_INCA_IP)	+= asc_serial.o incaip_clock.o
+COBJS-$(CONFIG_PURPLE)	+= asc_serial.o
+COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 START	:= $(addprefix $(obj),$(START))
 
 all:	$(obj).depend $(START) $(LIB)

cpu/mips/asc_serial.c +0 -3

index 3498b61..be686c2 100644
@@ -4,8 +4,6 @@
 
 #include <config.h>
 
-#if defined(CONFIG_PURPLE) || defined(CONFIG_INCA_IP)
-
 #ifdef CONFIG_PURPLE
 #define	serial_init	asc_serial_init
 #define	serial_putc	asc_serial_putc

@@ -368,4 +366,3 @@ int serial_tstc (void)
 
     return res;
 }
-#endif /* CONFIG_PURPLE || CONFIG_INCA_IP */

cpu/mips/au1x00_eth.c +4 -8

index d70c5fe..d0cf8e0 100644
@@ -23,8 +23,6 @@
  */
 #include <config.h>
 
-#ifdef CONFIG_AU1X00
-
 #if defined(CFG_DISCOVER_PHY)
 #error "PHY not supported yet"
 /* We just assume that we are running 100FD for now */

@@ -33,20 +31,20 @@
 
 /* I assume ethernet behaves like au1000 */
 
-#ifdef CONFIG_AU1000
+#ifdef CONFIG_SOC_AU1000
 /* Base address differ between cpu:s */
 #define ETH0_BASE AU1000_ETH0_BASE
 #define MAC0_ENABLE AU1000_MAC0_ENABLE
 #else
-#ifdef CONFIG_AU1100
+#ifdef CONFIG_SOC_AU1100
 #define ETH0_BASE AU1100_ETH0_BASE
 #define MAC0_ENABLE AU1100_MAC0_ENABLE
 #else
-#ifdef CONFIG_AU1500
+#ifdef CONFIG_SOC_AU1500
 #define ETH0_BASE AU1500_ETH0_BASE
 #define MAC0_ENABLE AU1500_MAC0_ENABLE
 #else
-#ifdef CONFIG_AU1550
+#ifdef CONFIG_SOC_AU1550
 #define ETH0_BASE AU1550_ETH0_BASE
 #define MAC0_ENABLE AU1550_MAC0_ENABLE
 #else

@@ -307,5 +305,3 @@ int au1x00_enet_initialize(bd_t *bis){
 
 	return 1;
 }
-
-#endif /* CONFIG_AU1X00 */

cpu/mips/au1x00_serial.c +0 -4

index 42c668e..6309794 100644
@@ -26,9 +26,6 @@
  */
 
 #include <config.h>
-
-#ifdef CONFIG_AU1X00
-
 #include <common.h>
 #include <asm/au1x00.h>

@@ -132,4 +129,3 @@ int serial_tstc (void)
 	}
 	return 0;
 }
-#endif /* CONFIG_SERIAL_AU1X00 */

cpu/mips/au1x00_usb_ohci.c +1 -1

index dbf72dc..1ca8aaf 100644
@@ -35,7 +35,7 @@
 
 #include <config.h>
 
-#if defined(CONFIG_AU1X00) && defined(CONFIG_USB_OHCI)
+#ifdef CONFIG_USB_OHCI
 
 /* #include <pci.h> no PCI on the AU1x00 */

cpu/mips/cache.S +3 -4

index 1b0efc3..ee5d411 100644
@@ -23,7 +23,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 #include <asm/asm.h>
 #include <asm/regdef.h>
 #include <asm/mipsregs.h>

@@ -41,7 +40,7 @@
  */
 #define MIPS_MAX_CACHE_SIZE	0x10000
 
-#define INDEX_BASE	KSEG0
+#define INDEX_BASE	CKSEG0
 
 	.macro	cache_op op addr
 	.set	push

@@ -219,7 +218,7 @@ NESTED(mips_cache_reset, 0, ra)
 	/*
 	 * Now clear that much memory starting from zero.
 	 */
-	PTR_LI		a0, KSEG1
+	PTR_LI		a0, CKSEG1
 	PTR_ADDU	a1, a0, v0
 2:	PTR_ADDIU	a0, 64
 	f_fill64	a0, -64, zero

@@ -319,7 +318,7 @@ LEAF(dcache_enable)
 	.globl	mips_cache_lock
 	.ent	mips_cache_lock
 mips_cache_lock:
-	li	a1, K0BASE - CACHE_LOCK_SIZE
+	li	a1, CKSEG0 - CACHE_LOCK_SIZE
 	addu	a0, a1
 	li	a2, CACHE_LOCK_SIZE
 	li	a3, CFG_CACHELINE_SIZE

cpu/mips/incaip_wdt.S +0 -1

index 329386b..3ade3cd 100644
@@ -24,7 +24,6 @@
 
 
 #include <config.h>
-#include <version.h>
 #include <asm/regdef.h>

cpu/mips/start.S +0 -1

index d881879..09e4aab 100644
@@ -23,7 +23,6 @@
  */
 
 #include <config.h>
-#include <version.h>
 #include <asm/regdef.h>
 #include <asm/mipsregs.h>

drivers/net/inca-ip_sw.c +14 ~~-14~~

index e4aaed6..a079b60 100644
@@ -234,7 +234,7 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis)
 	/* Initialize the descriptor rings.
 	 */
 	for (i = 0; i < NUM_RX_DESC; i++) {
-		inca_rx_descriptor_t * rx_desc = KSEG1ADDR(&rx_ring[i]);
+		inca_rx_descriptor_t * rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[i]);
 		memset(rx_desc, 0, sizeof(rx_ring[i]));
 
 		/* Set maximum size of receive buffer.

@@ -252,14 +252,14 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis)
 			/* Let the last descriptor point to the first
 			 * one.
 			 */
-			rx_desc->nextRxDescPtr = KSEG1ADDR((u32)rx_ring);
+			rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(rx_ring);
 		} else {
 			/* Set the address of the next descriptor.
 			 */
-			rx_desc->nextRxDescPtr = (u32)KSEG1ADDR(&rx_ring[i+1]);
+			rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(&rx_ring[i+1]);
 		}
 
-		rx_desc->RxDataPtr = (u32)KSEG1ADDR(NetRxPackets[i]);
+		rx_desc->RxDataPtr = (u32)CKSEG1ADDR(NetRxPackets[i]);
 	}
 
 #if 0

@@ -268,7 +268,7 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis)
 #endif
 
 	for (i = 0; i < NUM_TX_DESC; i++) {
-		inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[i]);
+		inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[i]);
 
 		memset(tx_desc, 0, sizeof(tx_ring[i]));

@@ -282,11 +282,11 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis)
 				/* Let the last descriptor point to the
 				 * first one.
 				 */
-			tx_desc->nextTxDescPtr = KSEG1ADDR((u32)tx_ring);
+			tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(tx_ring);
 		} else {
 				/* Set the address of the next descriptor.
 				 */
-			tx_desc->nextTxDescPtr = (u32)KSEG1ADDR(&tx_ring[i+1]);
+			tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(&tx_ring[i+1]);
 		}
 	}

@@ -346,7 +346,7 @@ static int inca_switch_send(struct eth_device *dev, volatile void *packet, int l
 	int		       res	= -1;
 	u32		       command;
 	u32		       regValue;
-	inca_tx_descriptor_t * tx_desc	= KSEG1ADDR(&tx_ring[tx_new]);
+	inca_tx_descriptor_t * tx_desc	= (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_new]);
 
 #if 0
 	printf("Entered inca_switch_send()\n");

@@ -365,7 +365,7 @@ static int inca_switch_send(struct eth_device *dev, volatile void *packet, int l
 	}
 
 	if (tx_old_hold >= 0) {
-		KSEG1ADDR(&tx_ring[tx_old_hold])->params.field.HOLD = 1;
+		((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_old_hold]))->params.field.HOLD = 1;
 	}
 	tx_old_hold = tx_hold;

@@ -376,7 +376,7 @@ static int inca_switch_send(struct eth_device *dev, volatile void *packet, int l
 	tx_desc->TxDataPtr = (u32)packet;
 	tx_desc->params.field.NBA = length;
 
-	KSEG1ADDR(&tx_ring[tx_hold])->params.field.HOLD = 0;
+	((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->params.field.HOLD = 0;
 
 	tx_hold = tx_new;
 	tx_new	= (tx_new + 1) % NUM_TX_DESC;

@@ -397,7 +397,7 @@ static int inca_switch_send(struct eth_device *dev, volatile void *packet, int l
 	DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
 
 #if 1
-	for(i = 0; KSEG1ADDR(&tx_ring[tx_hold])->C == 0; i++) {
+	for(i = 0; ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->C == 0; i++) {
 		if (i >= TOUT_LOOP) {
 			printf("%s: tx buffer not ready\n", dev->name);
 			goto Done;

@@ -423,7 +423,7 @@ static int inca_switch_recv(struct eth_device *dev)
 #endif
 
 	for (;;) {
-		rx_desc = KSEG1ADDR(&rx_ring[rx_new]);
+		rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_new]);
 
 		if (rx_desc->status.field.C == 0) {
 			break;

@@ -456,7 +456,7 @@ static int inca_switch_recv(struct eth_device *dev)
 #if 0
 			printf("Received %d bytes\n", length);
 #endif
-			NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_new]), length - 4);
+			NetReceive((void*)CKSEG1ADDR(NetRxPackets[rx_new]), length - 4);
 		} else {
 #if 1
 			printf("Zero length!!!\n");

@@ -464,7 +464,7 @@ static int inca_switch_recv(struct eth_device *dev)
 		}
 
 
-		KSEG1ADDR(&rx_ring[rx_hold])->params.field.HOLD = 0;
+		((inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_hold]))->params.field.HOLD = 0;
 
 		rx_hold = rx_new;

include/asm-mips/addrspace.h +128 ~~-45~~

207 lines not on this page · raw message

include/asm-mips/au1x00.h +3 -3

index 6a33197..2a948e8 100644
@@ -137,7 +137,7 @@ static __inline__ int au_ffs(int x)
 #define CP0_DEBUG		$23
 
 /* SDRAM Controller */
-#ifdef CONFIG_AU1550
+#ifdef CONFIG_SOC_AU1550
 
 #define MEM_SDMODE0                0xB4000800
 #define MEM_SDMODE1                0xB4000808

@@ -156,7 +156,7 @@ static __inline__ int au_ffs(int x)
 #define MEM_SDWRMD1                0xB4000888
 #define MEM_SDWRMD2                0xB4000890
 
-#else /* CONFIG_AU1550 */
+#else /* CONFIG_SOC_AU1550 */
 
 #define MEM_SDMODE0                0xB4000000
 #define MEM_SDMODE1                0xB4000004

@@ -174,7 +174,7 @@ static __inline__ int au_ffs(int x)
 #define MEM_SDWRMD1                0xB4000028
 #define MEM_SDWRMD2                0xB400002C
 
-#endif /* CONFIG_AU1550 */
+#endif /* CONFIG_SOC_AU1550 */
 
 #define MEM_SDSLEEP                0xB4000030
 #define MEM_SDSMCKE                0xB4000034

include/asm-mips/io.h +2 -2

index 7137072..3a0f33f 100644
@@ -120,7 +120,7 @@ static inline void set_io_port_base(unsigned long base)
  */
 extern inline unsigned long virt_to_phys(volatile void * address)
 {
-	return PHYSADDR(address);
+	return CPHYSADDR(address);
 }
 
 extern inline void * phys_to_virt(unsigned long address)

@@ -133,7 +133,7 @@ extern inline void * phys_to_virt(unsigned long address)
  */
 extern inline unsigned long virt_to_bus(volatile void * address)
 {
-	return PHYSADDR(address);
+	return CPHYSADDR(address);
 }
 
 extern inline void * bus_to_virt(unsigned long address)

include/configs/dbau1x00.h +8 -6

index b2f606f..0e10396 100644
@@ -30,21 +30,21 @@
 
 #define CONFIG_MIPS32		1  /* MIPS32 CPU core	*/
 #define CONFIG_DBAU1X00		1
-#define CONFIG_AU1X00		1  /* alchemy series cpu */
+#define CONFIG_SOC_AU1X00	1  /* alchemy series cpu */
 
 #ifdef CONFIG_DBAU1000
 /* Also known as Merlot */
-#define CONFIG_AU1000		1
+#define CONFIG_SOC_AU1000	1
 #else
 #ifdef CONFIG_DBAU1100
-#define CONFIG_AU1100		1
+#define CONFIG_SOC_AU1100	1
 #else
 #ifdef CONFIG_DBAU1500
-#define CONFIG_AU1500		1
+#define CONFIG_SOC_AU1500	1
 #else
 #ifdef CONFIG_DBAU1550
 /* Cabernet */
-#define CONFIG_AU1550           1
+#define CONFIG_SOC_AU1550	1
 #else
 #error "No valid board set"
 #endif

@@ -148,7 +148,9 @@
 #error "Invalid CPU frequency - must be multiple of 12!"
 #endif
 
-#define CFG_HZ                  (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */
+#define CFG_MIPS_TIMER_FREQ	(CFG_MHZ * 1000000)
+
+#define CFG_HZ			1000
 
 #define CFG_SDRAM_BASE		0x80000000     /* Cached addr */

include/configs/gth2.h +5 -3

index c2a50c1..c2d6ca7 100644
@@ -30,9 +30,9 @@
 
 #define CONFIG_MIPS32		1  /* MIPS32 CPU core	*/
 #define CONFIG_GTH2		1
-#define CONFIG_AU1X00		1  /* alchemy series cpu */
+#define CONFIG_SOC_AU1X00	1  /* alchemy series cpu */
 
-#define CONFIG_AU1000		1
+#define CONFIG_SOC_AU1000	1
 
 #define CONFIG_MISC_INIT_R	1

@@ -118,7 +118,9 @@
 
 #define CFG_MHZ			500
 
-#define CFG_HZ			(CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */
+#define CFG_MIPS_TIMER_FREQ	(CFG_MHZ * 1000000)
+
+#define CFG_HZ			1000
 
 #define CFG_SDRAM_BASE		0x80000000     /* Cached addr */

include/configs/incaip.h +3 -1

index 5ca00b3..2e4ee66 100644
@@ -118,7 +118,9 @@
 
 #define CFG_BOOTPARAMS_LEN	128*1024
 
-#define CFG_HZ			(incaip_get_cpuclk() / 2)
+#define CFG_MIPS_TIMER_FREQ	(incaip_get_cpuclk() / 2)
+
+#define CFG_HZ			1000
 
 #define CFG_SDRAM_BASE		0x80000000

include/configs/pb1x00.h +7 -5

index 810e0f0..2caa641 100644
@@ -30,16 +30,16 @@
 
 #define CONFIG_MIPS32		1  /* MIPS32 CPU core	*/
 #define CONFIG_PB1X00		1
-#define CONFIG_AU1X00		1  /* alchemy series cpu */
+#define CONFIG_SOC_AU1X00	1  /* alchemy series cpu */
 
 #ifdef CONFIG_PB1000
-#define CONFIG_AU1000		1
+#define CONFIG_SOC_AU1000	1
 #else
 #ifdef CONFIG_PB1100
-#define CONFIG_AU1100		1
+#define CONFIG_SOC_AU1100	1
 #else
 #ifdef CONFIG_PB1500
-#define CONFIG_AU1500		1
+#define CONFIG_SOC_AU1500	1
 #else
 #error "No valid board set"
 #endif

@@ -81,7 +81,9 @@
 
 #define CFG_BOOTPARAMS_LEN	128*1024
 
-#define CFG_HZ			396000000      /* FIXME causes overflow in net.c */
+#define CFG_MIPS_TIMER_FREQ	396000000
+
+#define CFG_HZ			1000
 
 #define CFG_SDRAM_BASE		0x80000000     /* Cached addr */

include/configs/purple.h +2 -1

index 1be4e05..ef92637 100644
@@ -114,7 +114,8 @@
 #define	CFG_PROMPT		"PURPLE # "	/* Monitor Command Prompt    */
 #define	CFG_CBSIZE		256		/* Console I/O Buffer Size   */
 #define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
-#define CFG_HZ			(CPU_CLOCK_RATE/2)
+#define CFG_MIPS_TIMER_FREQ	(CPU_CLOCK_RATE/2)
+#define CFG_HZ			1000
 #define	CFG_MAXARGS		16		/* max number of command args*/
 
 #define	CFG_LOAD_ADDR		0x80500000	/* default load address	*/

include/configs/qemu-mips.h +3 -1

index d6bcc8e..3dfd218 100644
@@ -120,7 +120,9 @@
 
 #define CFG_MHZ			132
 
-#define CFG_HZ			(CFG_MHZ * 1000000)
+#define CFG_MIPS_TIMER_FREQ	(CFG_MHZ * 1000000)
+
+#define CFG_HZ			1000
 
 #define CFG_SDRAM_BASE		0x80000000	/* Cached addr */

include/configs/tb0229.h +3 -1

index dadf5d3..fc2357d 100644
@@ -122,7 +122,9 @@
 
 #define CFG_BOOTPARAMS_LEN	128*1024
 
-#define CFG_HZ			(CPU_TCLOCK_RATE/4)
+#define CFG_MIPS_TIMER_FREQ	(CPU_TCLOCK_RATE/4)
+
+#define CFG_HZ			1000
 
 #define CFG_SDRAM_BASE		0x80000000

lib_mips/time.c +28 ~~-29~~

95 lines not on this page · raw message

mips_config.mk +3 -4

index 67fb67d..05eb05d 100644
@@ -40,10 +40,9 @@ PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__
 # LDFLAGS_vmlinux		+= -G 0 -static -n -nostdlib
 # MODFLAGS			+= -mlong-calls
 #
-
-#
-# Meanwhile, U-Boot rely on PIC. We add proper switches explicitly.
+# On the other hand, we want PIC in the U-Boot code to relocate it from ROM
+# to RAM. $28 is always used as gp.
 #
-PLATFORM_CPPFLAGS		+= -G 0 -mabicalls -fpic -pipe
+PLATFORM_CPPFLAGS		+= -G 0 -mabicalls -fpic
 PLATFORM_CPPFLAGS		+= -msoft-float
 PLATFORM_LDFLAGS		+= -G 0 -static -n -nostdlib

Wolfgang Denk

Applied

2008-06-11 20:51 UTC #1 lore raw

Quoted 45 lines · In message <[email protected]> you wrote:

Please pull MIPS updates to pick up the following patches.
The following changes since commit 8155efbd7ae9c65564ca98affe94631d612ae088:
Wolfgang Denk (1):
Merge branch 'master' of ssh://mercury/home/wd/git/u-boot/master
are available in the git repository at:
git://git.denx.de/u-boot-mips.git master
Shinya Kuribayashi (8):
[MIPS] lib_mips/time.c: Replace CP0 access functions with existing macros [MIPS] lib_mips/time.c: Fix udelay
[MIPS] lib_mips/time.c: Fix CP0 count register usage and timer routines [MIPS] Kill unused <version.h> inclusions
[MIPS] mips_config.mk: Misc fixes
[MIPS] Update <asm/addrspace.h> header
[MIPS] Rename Alchemy processor configs into CONFIGO_SOC_* [MIPS] cpu/mips/Makefile: Split [CS]OBJS onto separate lines
 board/dbau1x00/lowlevel_init.S  |    1 -
 board/gth2/gth2.c               |    2 +-
 board/gth2/lowlevel_init.S      |    1 -
 board/incaip/incaip.c           |    2 +-
 board/incaip/lowlevel_init.S    |    1 -
 board/pb1x00/lowlevel_init.S    |    1 -
 board/purple/lowlevel_init.S    |    1 -
 board/purple/purple.c           |   14 ++--
 board/qemu-mips/lowlevel_init.S |    1 -
 board/tb0229/lowlevel_init.S    |    1 -
 board/tb0229/vr4131-pci.c       |   56 ++++++------
 cpu/mips/Makefile               |   15 ++--
 cpu/mips/asc_serial.c           |    3 -
 cpu/mips/au1x00_eth.c           |   12 +--
 cpu/mips/au1x00_serial.c        |    4 -
 cpu/mips/au1x00_usb_ohci.c      |    2 +-
 cpu/mips/cache.S                |    7 +-
 cpu/mips/incaip_wdt.S           |    1 -
 cpu/mips/start.S                |    1 -
 drivers/net/inca-ip_sw.c        |   28 +++---
 include/asm-mips/addrspace.h    |  173 +++++++++++++++++++++++++++++----------
 include/asm-mips/au1x00.h       |    6 +-
 include/asm-mips/io.h           |    4 +-
 include/configs/dbau1x00.h      |   14 ++--
 include/configs/gth2.h          |    8 +-

Quoted 8 lines

 include/configs/incaip.h        |    4 +-
 include/configs/pb1x00.h        |   12 ++-
 include/configs/purple.h        |    3 +-
 include/configs/qemu-mips.h     |    4 +-
 include/configs/tb0229.h        |    4 +-
 lib_mips/time.c                 |   57 ++++++-------
 mips_config.mk                  |    7 +-
 32 files changed, 263 insertions(+), 187 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

Signature · 5 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
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A: The way it sounds.