Freescale DDR rewrite

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index 72af6ac..457cff3 100644
@@ -2370,6 +2370,16 @@ phys_size_t fsl_ddr_sdram(void)
 	 */
 	total_memory = fsl_ddr_sdram_compute(&info, STEP_GET_SPD);
 
+#ifdef CONFIG_FSL_DDR_INTERACTIVE
+	/*
+	 * The presence of the environment variable "ddrsetup"
+	 * causes the interactive DDR setup prompt to appear.
+	 */
+	if (getenv("ddrsetup")) {
+		total_memory = fsl_ddr_interactive(&info);
+	}
+#endif
+
 	/*
 	 * Check for memory controller interleaving.
 	 */

index 0ac44a7..4034e9c 100644
@@ -54,6 +54,9 @@ typedef struct {
 
 
 extern phys_size_t
+fsl_ddr_interactive(fsl_ddr_sdram_info_t *pinfo);
+
+extern phys_size_t
 fsl_ddr_sdram_compute(fsl_ddr_sdram_info_t *pinfo,
 				  unsigned int start_step);
 

index dca6a4d..f9bdf10 100644
@@ -72,6 +72,69 @@ void print_laws(void)
 	return;
 }
 
+#if defined(CONFIG_FSL_DDR1) || \
+    defined(CONFIG_FSL_DDR2) || \
+    defined(CONFIG_FSL_DDR3)
+#include <../cpu/mpc8xxx/fsl_ddr_sdram.h>
+
+void
+__fsl_ddr_sdram_set_lawbar(const common_timing_params_t *memctl_common_params,
+			   unsigned int memctl_interleaved,
+			   unsigned int ctrl_num)
+{
+	unsigned long law_base_address;
+	unsigned long memsize_MB;
+	unsigned int law_size;
+
+	/*
+	 * If no DIMMs on this controller, do not proceed any further.
+	 */
+	if (!memctl_common_params->ndimms_present) {
+		return;
+	}
+
+	law_base_address = memctl_common_params->base_address;
+
+	/*
+	 * Compute LAWBARn[SIZE] value for 2**(SIZE + 1) bytes.
+	 * If interleaving is used, the memory size must represent
+	 * the combined total of both controllers.
+	 * The first supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
+	 * Fnord.
+	 */
+	memsize_MB = memctl_common_params->total_mem / 0x100000;
+	law_size = 19 + __ilog2(memsize_MB << memctl_interleaved);
+
+	if (ctrl_num == 0) {
+		/*
+		 * Set up LAWBAR1 for DDR controller 1 space.
+		 */
+		unsigned int lawbar1_target_id = memctl_interleaved
+			? LAW_TRGT_IF_DDR_INTRLV : LAW_TRGT_IF_DDR_1;
+
+		set_law(1, law_base_address, law_size, lawbar1_target_id);
+		debug("ctl0 law_base_address = 0x%08X, law_size = 0x%x\n",
+		      law_base_address, law_size);
+
+	} else if (ctrl_num == 1) {
+		/*
+		 * Set up LAWBAR2 for DDR controller 2 space.
+		 */
+		set_law(2, law_base_address, law_size, LAW_TRGT_IF_DDR_2);
+		debug("ctl1 law_base_address = 0x%08X, law_size = 0x%x\n",
+		      law_base_address, law_size);
+
+	} else {
+		printf("unexpected controller number %u in fsl_ddr_sdram_set_lawbar()\n", ctrl_num);
+	}
+}
+
+__attribute__((weak, alias("__fsl_ddr_sdram_set_lawbar"))) void
+fsl_ddr_sdram_set_lawbar(const common_timing_params_t *memctl_common_params,
+			 unsigned int memctl_interleaved,
+			 unsigned int ctrl_num);
+#endif
+
 void init_laws(void)
 {
 	int i;

index 3d15d50..63f34e6 100644
@@ -90,3 +90,66 @@ void init_tlbs(void)
 
 	return ;
 }
+
+unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
+{
+	unsigned int tlb_size;
+	unsigned int ram_tlb_index;
+	unsigned int ram_tlb_address;
+
+	/*
+	 * Determine size of each TLB1 entry.
+	 */
+	switch (memsize_in_meg) {
+	case 16:
+	case 32:
+		tlb_size = BOOKE_PAGESZ_16M;
+		break;
+	case 64:
+	case 128:
+		tlb_size = BOOKE_PAGESZ_64M;
+		break;
+	case 256:
+	case 512:
+		tlb_size = BOOKE_PAGESZ_256M;
+		break;
+	case 1024:
+	case 2048:
+		if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx))
+			tlb_size = BOOKE_PAGESZ_1G;
+		else
+			tlb_size = BOOKE_PAGESZ_256M;
+		break;
+	default:
+		puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G are supported.\n");
+
+		/*
+		 * The memory was not able to be mapped.
+		 * Default to a small size.
+		 */
+		tlb_size = BOOKE_PAGESZ_64M;
+		memsize_in_meg = 64;
+		break;
+	}
+
+	/*
+	 * Configure DDR TLB1 entries.
+	 * Starting at TLB1 8, use no more than 8 TLB1 entries.
+	 */
+	ram_tlb_index = 8;
+	ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
+	while (ram_tlb_address < (memsize_in_meg * 1024 * 1024)
+	      && ram_tlb_index < 16) {
+		set_tlb(1, ram_tlb_address, ram_tlb_address,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, ram_tlb_index, tlb_size, 1);
+
+		ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
+		ram_tlb_index++;
+	}
+
+	/*
+	 * Confirm that the requested amount of memory was mapped.
+	 */
+	return memsize_in_meg;
+}

index 050a7b6..8975e6c 100644
@@ -431,6 +431,7 @@ extern void set_tlb(u8 tlb, u32 epn, u64 rpn,
 extern void disable_tlb(u8 esel);
 extern void invalidate_tlb(u8 tlb);
 extern void init_tlbs(void);
+extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
 
 #define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \
 	{ .tlb = _tlb, .epn = _epn, .rpn = _rpn, .perms = _perms, \

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index bb1f927..755c967 100644
@@ -25,18 +25,17 @@
 #include <asm/processor.h>
 #include <asm/immap_86xx.h>
 #include <asm/immap_fsl_pci.h>
-#include <spd_sdram.h>
 #include <asm/io.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 
 #include "../common/pixis.h"
+#include "../cpu/mpc8xxx/fsl_ddr_sdram.h"
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
-void sdram_init(void);
 long int fixed_sdram(void);
 
 

@@ -59,7 +58,7 @@ initdram(int board_type)
 	long dram_size = 0;
 
 #if defined(CONFIG_SPD_EEPROM)
-	dram_size = spd_sdram();
+	dram_size = fsl_ddr_sdram();
 #else
 	dram_size = fixed_sdram();
 #endif

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index 3a855b5..f8d8707 100644
@@ -33,6 +33,7 @@
 #include <spd_sdram.h>
 
 #include "../common/pixis.h"
+#include "../cpu/mpc8xxx/fsl_ddr_sdram.h"
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);

@@ -119,7 +120,7 @@ initdram(int board_type)
 	long dram_size = 0;
 
 #if defined(CONFIG_SPD_EEPROM)
-	dram_size = spd_sdram();
+	dram_size = fsl_ddr_sdram();
 #else
 	dram_size = fixed_sdram();
 #endif

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index dd10af8..d3b2f94 100644
@@ -24,22 +24,21 @@
 #include <command.h>
 #include <pci.h>
 #include <asm/processor.h>
+#include <asm/mmu.h>
 #include <asm/immap_85xx.h>
 #include <asm/immap_fsl_pci.h>
 #include <asm/io.h>
-#include <spd_sdram.h>
 #include <miiphy.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 
 #include "../common/pixis.h"
+#include "../cpu/mpc8xxx/fsl_ddr_sdram.h"
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
-void sdram_init(void);
-
 int board_early_init_f (void)
 {
 	return 0;

@@ -71,7 +70,13 @@ initdram(int board_type)
 
 	puts("Initializing\n");
 
-	dram_size = spd_sdram();
+	dram_size = fsl_ddr_sdram();
+	printf("dram_size = %u\n", dram_size);
+
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	printf("dram_size = %u after setup_ddr_tlbs\n", dram_size);
+
+	dram_size *= 0x100000;
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 	/*

@@ -96,10 +101,14 @@ testdram(void)
 	       CFG_MEMTEST_END);
 
 	printf("DRAM test phase 1:\n");
-	for (p = pstart; p < pend; p++)
+	for (p = pstart; p < pend; p++) {
+		if ((((unsigned int) p) & 0xffff) == 0) {
+			printf ("%p\n", p);
+		}
 		*p = 0xaaaaaaaa;
+	}
 
-	for (p = pstart; p < pend; p++) {
+	 for (p = pstart; p < pend; p++) {
 		if (*p != 0xaaaaaaaa) {
 			printf ("DRAM test fails at: %08x\n", (uint) p);
 			return 1;

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