AT572D940HF-EB Support

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+/*
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
+	{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+	{CFG_DATAFLASH_LOGIC_ADDR_CS1, 1}
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+	{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
+	{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
+};

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+/*
+ * include/asm-arm/arch-at572d940/at91_aic.h
+ *
+ * Copyright (C) ATMEL
+ *
+ * Advanced Interrupt Controller (AIC).
+ * Based on AT572D940 datasheet.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#define AIC_BASE 	0xfffff000
+
+#define AIC_SMR0	0x0
+#define AIC_SVR0	0x80
+#define AIC_IVR		0x100
+#define AIC_FIQ		0x104
+#define AIC_ISR		0x108
+#define AIC_IPR		0x10c
+#define AIC_IMR		0x110
+#define AIC_ICR		0x114
+#define AIC_IECR	0x120
+#define AIC_IDCR	0x124
+#define AIC_ICCR	0x128
+#define AIC_ISCR	0x12c
+#define AIC_EOICR	0x130
+#define AIC_SPU		0x134
+
+#define AIC_SMR(n)	\
+	((unsigned long) (((unsigned long*) AIC_SMR0) + (n)))
+#define AIC_SVR(n)	\
+	((unsigned long) (((unsigned long*) AIC_SVR0) + (n)))
+
+#define AIC_WRITE(reg,value) \
+	(*((volatile unsigned long*) (AIC_BASE + (reg))) = value)
+#define AIC_READ(reg,value)  \
+	(value = *((volatile unsigned long*) (AIC_BASE + (reg))))
+
+#define AIC_REG(reg)	\
+	(*((volatile unsigned long*) (AIC_BASE + (reg))))

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+/*
+ * include/asm-arm/arch-at91/at91_pit.h
+ *
+ * Periodic Interval Timer (PIT) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_PIT_H
+#define AT91_PIT_H
+
+#define AT91_PIT_MR		(AT91_PIT + 0x00)	/* Mode Register */
+#define		AT91_PIT_PITIEN		(1 << 25)	/* Timer Interrupt Enable */
+#define		AT91_PIT_PITEN		(1 << 24)	/* Timer Enabled */
+#define		AT91_PIT_PIV		(0xfffff)	/* Periodic Interval Value */
+
+#define AT91_PIT_SR		(AT91_PIT + 0x04)	/* Status Register */
+#define		AT91_PIT_PITS		(1 << 0)	/* Timer Status */
+
+#define AT91_PIT_PIVR		(AT91_PIT + 0x08)	/* Periodic Interval Value Register */
+#define AT91_PIT_PIIR		(AT91_PIT + 0x0c)	/* Periodic Interval Image Register */
+#define		AT91_PIT_PICNT		(0xfff << 20)	/* Interval Counter */
+#define		AT91_PIT_CPIV		(0xfffff)	/* Inverval Value */
+
+#endif

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+/*
+ * include/asm-arm/arch-at91/at91_rstc.h
+ *
+ * Reset Controller (RSTC) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_RSTC_H
+#define AT91_RSTC_H
+
+#define AT91_RSTC_CR		(AT91_RSTC + 0x00)	/* Reset Controller Control Register */
+#define	AT91_RSTC_PROCRST	(1 << 0)	/* Processor Reset */
+#define	AT91_RSTC_PERRST	(1 << 2)	/* Peripheral Reset */
+#define	AT91_RSTC_EXTRST	(1 << 3)	/* External Reset */
+#define	AT91_RSTC_KEY		(0xa5 << 24)	/* KEY Password */
+
+#define AT91_RSTC_SR			(AT91_RSTC + 0x04)	/* Reset Controller Status Register */
+#define	AT91_RSTC_URSTS			(1 << 0)	/* User Reset Status */
+#define	AT91_RSTC_RSTTYP		(7 << 8)	/* Reset Type */
+#define	AT91_RSTC_RSTTYP_GENERAL	(0 << 8)
+#define	AT91_RSTC_RSTTYP_WAKEUP		(1 << 8)
+#define	AT91_RSTC_RSTTYP_WATCHDOG	(2 << 8)
+#define	AT91_RSTC_RSTTYP_SOFTWARE	(3 << 8)
+#define	AT91_RSTC_RSTTYP_USER		(4 << 8)
+#define	AT91_RSTC_NRSTL			(1 << 16)	/* NRST Pin Level */
+#define	AT91_RSTC_SRCMP			(1 << 17)	/* Software Reset Command in Progress */
+
+#define AT91_RSTC_MR		(AT91_RSTC + 0x08)	/* Reset Controller Mode Register */
+#define	AT91_RSTC_URSTEN	(1 << 0)	/* User Reset Enable */
+#define	AT91_RSTC_URSTIEN	(1 << 4)	/* User Reset Interrupt Enable */
+#define	AT91_RSTC_ERSTL		(0xf << 8)	/* External Reset Length */
+
+#endif

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+/*
+ * include/asm-arm/arch-at91/hardware.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *  Copyright (C) 2003 ATMEL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+
+#if defined(CONFIG_AT572D940HF)
+#include <asm/arch/at572d940hf.h>
+#else
+#error "Unsupported AT572D940HF processor"
+#endif
+
+/*
+ * container_of - cast a member of a structure out to the containing structure
+ *
+ * @ptr:	the pointer to the member.
+ * @type:	the type of the container struct this is embedded in.
+ * @member:	the name of the member within the struct.
+ */
+#define container_of(ptr, type, member) ({			\
+	const typeof(((type *)0)->member) *__mptr = (ptr);	\
+	(type *)((char *)__mptr - offsetof(type, member)); })
+
+#endif

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+/*
+ * include/asm-arm/arch-at91/io.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#include <asm/io.h>
+
+static inline unsigned int at91_sys_read(unsigned int reg_offset)
+{
+	void *addr = (void *)AT91_BASE_SYS;
+
+	return __raw_readl(addr + reg_offset);
+}
+
+static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
+{
+	void *addr = (void *)AT91_BASE_SYS;
+
+	__raw_writel(value, addr + reg_offset);
+}
+
+#endif

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+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_ARM_ARCH_MEMORYMAP_H__
+#define __ASM_ARM_ARCH_MEMORYMAP_H__
+
+#include <asm/arch/hardware.h>
+
+#define USART0_BASE AT91_USART0
+#define USART1_BASE AT91_USART1
+#define USART2_BASE AT91_USART2
+#define USART3_BASE (AT91_BASE_SYS + AT91_DBGU)
+
+#define AT572D940_SDRAM_BASE 0x20000000
+
+#endif /* __ASM_ARM_ARCH_MEMORYMAP_H__ */

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+/*
+ * include/asm-arm/arch-at91/AT572D940HFhf.h
+ *
+ * (C) 2008 Antonio R. Costa
+ *
+ * Common definitions.
+ * Based on AT572D940HFHF datasheet rev A.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT572D940HFHF_H
+#define AT572D940HFHF_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ		0	/* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS		1	/* System Peripherals */
+#define AT572D940HF_ID_PIOA	2	/* Parallel IO Controller A */
+#define AT572D940HF_ID_PIOB	3	/* Parallel IO Controller B */
+#define AT572D940HF_ID_PIOC	4	/* Parallel IO Controller C */
+#define AT572D940HF_ID_EMAC	5	/* Ethernet */
+#define AT572D940HF_ID_US0	6	/* USART 0 */
+#define AT572D940HF_ID_US1	7	/* USART 1 */
+#define AT572D940HF_ID_US2	8	/* USART 2 */
+#define AT572D940HF_ID_MCI	9	/* Multimedia Card Interface */
+#define AT572D940HF_ID_UDP	10	/* USB Device Port */
+#define AT572D940HF_ID_TWI	11	/* Two-Wire Interface */
+#define AT572D940HF_ID_TWI0	11	/* Two-Wire Interface */
+#define AT572D940HF_ID_SPI0	12	/* Serial Peripheral Interface 0 */
+#define AT572D940HF_ID_SPI1	13	/* Serial Peripheral Interface 1 */
+#define AT572D940HF_ID_SSC	14	/* Serial Synchronous Controller */
+#define AT572D940HF_ID_SSC0	14	/* Serial Synchronous Controller */
+#define AT572D940HF_ID_SSC1	15	/* Serial Synchronous Controller */
+#define AT572D940HF_ID_SSC2	16	/* Serial Synchronous Controller */
+#define AT572D940HF_ID_TC0	17	/* Timer Counter 0 */
+#define AT572D940HF_ID_TC1	18	/* Timer Counter 1 */
+#define AT572D940HF_ID_TC2	19	/* Timer Counter 2 */
+#define AT572D940HF_ID_UHP	20	/* USB Host port */
+#define AT572D940HF_ID_SSC3	21	/* Serial Synchronous Controller */
+#define AT572D940HF_ID_TWI1	22	/* Two-Wire Interface */
+#define AT572D940HF_ID_CAN0	23	/* CAN Controller */
+#define AT572D940HF_ID_CAN1	24	/* CAN Controller */
+#define AT572D940HF_ID_mHALT	25	/* mAgicV DSP halt int */
+#define AT572D940HF_ID_mSIRQ1	26	/* mAgicV DSP SIRQ1 int */
+#define AT572D940HF_ID_mEXC	27	/* mAgicV DSP Exception int */
+#define AT572D940HF_ID_mEDMA	28	/* mAgicV DSP end of DMA transfer int */
+#define AT572D940HF_ID_IRQ0	29	/* Advanced Interrupt Controller (IRQ0) */
+#define AT572D940HF_ID_IRQ1	30	/* Advanced Interrupt Controller (IRQ1) */
+#define AT572D940HF_ID_IRQ2	31	/* Advanced Interrupt Controller (IRQ2) */
+
+#define AT91_ID_US0 		AT572D940HF_ID_US0
+#define AT91_ID_US1 		AT572D940HF_ID_US1
+#define AT91_ID_US2 		AT572D940HF_ID_US2
+#define AT91_ID_US3 		AT572D940HF_ID_US3
+
+#define AT91_ID_UHP	AT572D940HF_ID_UHP
+#define AT91_PMC_UHP	AT572D940HF_ID_UHP
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT572D940HF_BASE_TCB0		0xfffa0000
+#define AT572D940HF_BASE_TC0		0xfffa0000
+#define AT572D940HF_BASE_TC1		0xfffa0040
+#define AT572D940HF_BASE_TC2		0xfffa0080
+#define AT572D940HF_BASE_UDP		0xfffa4000
+#define AT572D940HF_BASE_MCI		0xfffa8000
+#define AT572D940HF_BASE_TWI		0xfffac000
+#define AT572D940HF_BASE_US0		0xfffb0000
+#define AT572D940HF_BASE_US1		0xfffb4000
+#define AT572D940HF_BASE_US2		0xfffb8000
+#define AT572D940HF_BASE_SSC		0xfffbc000
+#define AT572D940HF_BASE_ISI		0xfffc0000
+#define AT572D940HF_BASE_EMAC		0xfffd8000
+#define AT572D940HF_BASE_SPI0		0xfffc8000
+#define AT572D940HF_BASE_SPI1		0xfffcc000
+#define AT572D940HF_BASE_US3		0xfffd0000
+#define AT572D940HF_BASE_US4		0xfffd4000
+#define AT572D940HF_BASE_US5		0xfffd8000
+#define AT572D940HF_BASE_TCB1		0xfffdc000
+#define AT572D940HF_BASE_TC3		0xfffdc000
+#define AT572D940HF_BASE_TC4		0xfffdc040
+#define AT572D940HF_BASE_TC5		0xfffdc080
+#define AT572D940HF_BASE_ADC		0xfffe0000
+#define AT572D940HF_BASE_RSTC		0xfffffd00
+#define AT91_BASE_SYS			0xffffea00
+
+#define AT91_BASE_EMAC	AT572D940HF_BASE_EMAC
+#define AT91_BASE_SPI	AT572D940HF_BASE_SPI0
+#define MMCI_BASE	AT572D940HF_BASE_MCI
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_ECC	(0xffffe800 - AT91_BASE_SYS)
+#define AT91_SDRAMC	(0xffffea00 - AT91_BASE_SYS)
+#define AT91_SMC	(0xffffec00 - AT91_BASE_SYS)
+#define AT91_MATRIX	(0xffffee00 - AT91_BASE_SYS)
+#define AT91_CCFG	(0xffffef10 - AT91_BASE_SYS)
+#define AT91_AIC	(0xfffff000 - AT91_BASE_SYS)
+#define AT91_DBGU	(0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOA	(0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOB	(0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOC	(0xfffff800 - AT91_BASE_SYS)
+#define AT91_PMC	(0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC	(0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDWC	(0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT	(0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT	(0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT	(0xfffffd40 - AT91_BASE_SYS)
+#define AT91_GPBR	(0xfffffd50 - AT91_BASE_SYS)
+
+#define AT91_USART0	AT572D940HF_BASE_US0
+#define AT91_USART1	AT572D940HF_BASE_US1
+#define AT91_USART2	AT572D940HF_BASE_US2
+#define AT91_USART3	AT572D940HF_BASE_US3
+#define AT91_USART4	AT572D940HF_BASE_US4
+#define AT91_USART5	AT572D940HF_BASE_US5
+
+/*
+ * Internal Memory.
+ */
+#define AT572D940HF_ROM_BASE	0x00400000	/* Internal ROM base address */
+#define AT572D940HF_ROM_SIZE	SZ_32K	/* Internal ROM size (32Kb) */
+
+#define AT572D940HF_SRAM0_BASE	0x00100000	/* Internal SRAM 0 base address */
+#define AT572D940HF_SRAM0_SIZE	SZ_16K	/* Internal SRAM 0 size (4Kb) */
+#define AT572D940HF_SRAM1_BASE	0x00200000	/* Internal SRAM 0 base address */
+#define AT572D940HF_SRAM1_SIZE	SZ_16K	/* Internal SRAM 0 size (4Kb) */
+#define AT572D940HF_SRAM2_BASE	0x00300000	/* Internal SRAM 1 base address */
+#define AT572D940HF_SRAM2_SIZE	SZ_16K	/* Internal SRAM 1 size (4Kb) */
+
+//SDRAM
+#define AT572D940HF_SDRAM_BASE	0x20000000
+
+// USB Host
+#define AT572D940HF_UHP_BASE	0x00500000	/* USB Host controller */
+
+#define AT91SAM9XE_FLASH_BASE	0x00200000	/* Internal FLASH base address */
+#define AT91SAM9XE_SRAM_BASE	0x00300000	/* Internal SRAM base address */
+
+#endif

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+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Author: Antonio R. Costa
+ */
+
+#ifndef _AT91_TIMER_H_
+#define _AT91_TIMER_H_
+
+#define AT91_SLOW_FREQ    0
+#define AT91_MAIN_FREQ    1
+#define AT91_PLLA_FREQ    2
+#define AT91_PLLB_FREQ    3
+#define AT91_MASTER_FREQ  4
+#define AT91_SYS_FREQ     4
+#define AT91_PROC_FREQ    5
+
+extern int sys_get_freq(unsigned long mode, unsigned long *pfreq);
+
+#endif /* _AT91_TIMER_H_ */

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+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
+
+#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET)
+void at572d940hf_eth_initialize(bd_t *bi)
+{
+	macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x00);
+}
+#endif

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index e5733f6..eb446d1 100644
@@ -417,15 +417,15 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
 
 	/* choose RMII or MII mode. This depends on the board */
 #ifdef CONFIG_RMII
-#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
-    defined(CONFIG_AT91SAM9263)
+#if defined(CONFIG_AT91CAP9)    || defined(CONFIG_AT91SAM9260) || \
+    defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT572D940HFEB)
 	macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
 #else
 	macb_writel(macb, USRIO, 0);
 #endif
 #else
-#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
-    defined(CONFIG_AT91SAM9263)
+#if defined(CONFIG_AT91CAP9)    || defined(CONFIG_AT91SAM9260) || \
+    defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT572D940HFEB)
 	macb_writel(macb, USRIO, MACB_BIT(CLKEN));
 #else
 	macb_writel(macb, USRIO, MACB_BIT(MII));

index 21d1496..e782731 100644
@@ -65,6 +65,7 @@ extern int atngw100_eth_initialize(bd_t *);
 extern int mcffec_initialize(bd_t*);
 extern int mcdmafec_initialize(bd_t*);
 extern int at91sam9_eth_initialize(bd_t *);
+extern int at572d940hf_eth_initialize(bd_t *);
 
 #ifdef CONFIG_API
 extern void (*push_packet)(volatile void *, int);

@@ -292,6 +293,9 @@ int eth_initialize(bd_t *bis)
     defined(CONFIG_AT91SAM9263)
 	at91sam9_eth_initialize(bis);
 #endif
+#if defined(CONFIG_AT572D940HF)
+	at572d940hf_eth_initialize(bis);
+#endif
 
 	if (!eth_devices) {
 		puts ("No ethernet found.\n");

index aaf2ea2..b053b7a 100644
@@ -1595,6 +1595,7 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_P300                 1602
 #define MACH_TYPE_XDACOMET             1603
 #define MACH_TYPE_DEXFLEX2             1604
+#define MACH_TYPE_AT572D940HFEB        1783
 
 #ifdef CONFIG_ARCH_EBSA110
 # ifdef machine_arch_type

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