Add MPC5200B base board mvBC-P

PATCH Superseded Andre Schwarz 3 participants 4 messages Jul 7, 2008 – Jul 9, 2008

Subsystems (3)

Device tree bindings PowerPC Linux for PowerPC embedded MPC5XXX

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Andre Schwarz

author

2008-07-07 08:14 UTC #0 lore raw

PATCH v2 1/1 Add MPC5200B base board mvBC-P

The mvBlueCOUGAR-P is a MPC5200B based camera system with Intel Gigabit ethernet controller (using e1000). It's just another MPC5200_simple board.

Signed-off-by Andre Schwarz <[email protected]>

---

Grant,

please find attached the re-submitted patch with mods as you requested. I've also fixed the dts regarding to David's proposal.

Please let me know if anything is still incorrect.

Thanks again,
Andre

MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner

 arch/powerpc/boot/dts/mvbc-p.dts             |  261 ++++++
 arch/powerpc/configs/52xx/mvbc_p_defconfig   | 1158 ++++++++++++++++++++++++++
 arch/powerpc/platforms/52xx/Kconfig          |    3 +-
 arch/powerpc/platforms/52xx/mpc5200_simple.c |    1 +
 4 files changed, 1422 insertions(+), 1 deletions(-)

arch/powerpc/boot/dts/mvbc-p.dts new file +261 -0

new file mode 100644
index 0000000..2392dc2
@@ -0,0 +1,261 @@
+/*
+ * mvBlueCOUGAR-P device tree source
+ *
+ * Copyright (C) 2008 Matrix Vision GmbH
+ * Andre Schwarz <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+	model = "matrix-vision,mvbc-p";
+	compatible = "matrix-vision,mvbc-p";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,5200@0 {
+			device_type = "cpu";
+			reg = <0>;
+			d-cache-line-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x4000>;
+			i-cache-size = <0x4000>;
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x00000000>;
+	};
+
+	soc5200@f0000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fsl,mpc5200b-immr";
+		ranges = <0 0xf0000000 0x0000c000>;
+		reg = <0xf0000000 0x00000100>;
+		bus-frequency = <0>;
+		system-frequency = <0>;
+
+		cdm@200 {
+			compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
+			reg = <0x200 0x38>;
+		};
+
+		mpc5200_pic: interrupt-controller@500 {
+			// 5200 interrupts are encoded into two levels;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
+			reg = <0x500 0x80>;
+		};
+
+		timer@600 {	// General Purpose Timer
+			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+			reg = <0x600 0x10>;
+			interrupts = <1 9 0>;
+			interrupt-parent = <&mpc5200_pic>;
+			fsl,has-wdt;
+		};
+
+		timer@610 {	// General Purpose Timer
+			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+			cell-index = <1>;
+			reg = <0x610 0x10>;
+			interrupts = <1 10 0>;
+			interrupt-parent = <&mpc5200_pic>;
+		};
+
+		timer@620 {	// General Purpose Timer
+			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+			cell-index = <2>;
+			reg = <0x620 0x10>;
+			interrupts = <1 11 0>;
+			interrupt-parent = <&mpc5200_pic>;
+		};
+
+		timer@630 {	// General Purpose Timer
+			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+			cell-index = <3>;
+			reg = <0x630 0x10>;
+			interrupts = <1 12 0>;
+			interrupt-parent = <&mpc5200_pic>;
+		};
+
+		timer@640 {	// General Purpose Timer
+			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+			cell-index = <4>;
+			reg = <0x640 0x10>;
+			interrupts = <1 13 0>;
+			interrupt-parent = <&mpc5200_pic>;
+		};
+
+		timer@650 {	// General Purpose Timer
+			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+			cell-index = <5>;
+			reg = <0x650 0x10>;
+			interrupts = <1 14 0>;
+			interrupt-parent = <&mpc5200_pic>;
+		};
+
+		timer@660 {	// General Purpose Timer
+			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+			cell-index = <6>;
+			reg = <0x660 0x10>;
+			interrupts = <1 15 0>;
+			interrupt-parent = <&mpc5200_pic>;
+		};
+
+		timer@670 {	// General Purpose Timer
+			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+			cell-index = <7>;
+			reg = <0x670 0x10>;
+			interrupts = <1 16 0>;
+			interrupt-parent = <&mpc5200_pic>;
+		};
+
+		gpio@b00 {
+			compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
+			reg = <0xb00 0x40>;
+			interrupts = <1 7 0>;
+			interrupt-parent = <&mpc5200_pic>;
+		};
+
+		gpio@c00 {
+			compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
+			reg = <0xc00 0x40>;
+			interrupts = <1 8 0 0 3 0>;
+			interrupt-parent = <&mpc5200_pic>;
+		};
+
+		dma-controller@1200 {
+			compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
+			reg = <0x1200 0x80>;
+			interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
+				      3 4 0  3 5 0  3 6 0  3 7 0
+				      3 8 0  3 9 0  3 10 0  3 11 0
+				      3 12 0  3 13 0  3 14 0  3 15 0>;
+			interrupt-parent = <&mpc5200_pic>;
+		};
+
+		xlb@1f00 {
+			compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
+			reg = <0x1f00 0x100>;
+		};
+
+		serial0: serial@2000 {		// PSC1
+			device_type = "serial";
+			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
+			port-number = <0>;
+			reg = <0x2000 0x100>;
+			interrupts = <2 1 0>;
+			interrupt-parent = <&mpc5200_pic>;
+		};
+
+		i2c@3d00 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
+			reg = <0x3d00 0x40>;
+			interrupts = <2 15 0>;
+			interrupt-parent = <&mpc5200_pic>;
+			fsl5200-clocking;
+		};
+
+		i2c@3d40 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
+			reg = <0x3d40 0x40>;
+			interrupts = <2 16 0>;
+			interrupt-parent = <&mpc5200_pic>;
+			fsl5200-clocking;
+		};
+		sram@8000 {
+			compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram";
+			reg = <0x8000 0x4000>;
+		};
+	};
+
+	lpb {
+		compatible = "fsl,lpb","simple-bus";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0xff800000 0x00800000>;
+		flash@0,0 {
+			compatible = "amd,s29gl64","cfi-flash";
+			reg = <0 0 0x800000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bank-width = <1>;
+			device-width = <1>;
+			nor_total@0x0 {
+				reg = <0x0 0x800000>;
+			};
+			u-boot@0x0 {
+				reg = <0x0 0x40000>;
+			};
+			u-boot_autoscript@0x40000 {
+				reg = <0x40000 0x10000>;
+			};
+			u-boot_autoscript_red@0x50000 {
+				reg = <0x50000 0x10000>;
+			};
+			fpga@0x60000 {
+				reg = <0x60000 0x40000>;
+			};
+			user@0xa0000 {
+				reg = <0xa00000 0x60000>;
+			};
+			rfs@0x100000 {
+				reg = <0x100000 0x300000>;
+			};
+			kernel@0x400000 {
+				reg = <0x400000 0x3c0000>;
+			};
+			dtb@0x7c0000 {
+				reg = <0x7c0000 0x10000>;
+			};
+			dtb@0x7d0000 {
+				reg = <0x7d0000 0x10000>;
+			};
+			ppcboot_env@0x7e0000 {
+				reg = <0x7e0000 0x10000>;
+			};
+			ppcboot_env@0x7f0000 {
+				reg = <0x7f0000 0x10000>;
+			};
+		};
+	};
+
+	pci: pci@0xf0000d00 {
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		device_type = "pci";
+		compatible = "fsl,mpc5200-pci";
+		reg = <0xf0000d00 0x100>;
+		interrupt-map-mask = <0xf800 0 0 7>;
+		interrupt-map = <0x5800 0 0 1 &mpc5200_pic 1 2 3
+			0x5000 0 0 1 &mpc5200_pic 1 3 3>;
+		clock-frequency = <0>;
+		interrupts = <2 8 0 2 9 0 2 10 0>;
+		interrupt-parent = <&mpc5200_pic>;
+		bus-range = <0 0>;
+		ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
+			0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
+			0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
+	};
+};

arch/powerpc/configs/52xx/mvbc_p_defconfig new file +1158 -0

1,158 lines not on this page · raw message

arch/powerpc/platforms/52xx/Kconfig +2 -1

index acd2fc8..d2960a9 100644
@@ -21,7 +21,8 @@ config PPC_MPC5200_SIMPLE
 	    and if there is a PCI bus node defined in the device tree.
 
 	  Boards that are compatible with this generic platform support
-	  are: 'tqc,tqm5200', 'promess,motionpro', 'schindler,cm5200'.
+	  are: 'tqc,tqm5200', 'promess,motionpro', 'schindler,cm5200' and
+	       'matrix-vision,mvbc-p'.
 
 config PPC_EFIKA
 	bool "bPlan Efika 5k2. MPC5200B based computer"

arch/powerpc/platforms/52xx/mpc5200_simple.c +1 -0

index a3bda0b..6423675 100644
@@ -54,6 +54,7 @@ static char *board[] __initdata = {
 	"phytec,pcm030",
 	"schindler,cm5200",
 	"tqc,tqm5200",
+	"matrix-vision,mvbc-p",
 	NULL
 };

David Gibson

2008-07-08 03:44 UTC #1 lore raw

Quoted 2 lines · Andre Schwarz

The mvBlueCOUGAR-P is a MPC5200B based camera system with Intel Gigabit ethernet controller (using e1000). It's just another MPC5200_simple board.

[snip]

arch/powerpc/boot/dts/mvbc-p.dts line 75

Quoted 11 lines

arch/powerpc/boot/dts/mvbc-p.dts new file +11 -0

+		timer@600 {	// General Purpose Timer
+			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+			reg = <0x600 0x10>;
+			interrupts = <1 9 0>;
+			interrupt-parent = <&mpc5200_pic>;
+			fsl,has-wdt;
+		};
+
+		timer@610 {	// General Purpose Timer
+			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+			cell-index = <1>;

What shared resource is this cell-index value used to index?

Also why does it not appear on the timer@600 but does on all the others.

Signature · 4 lines

David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Andre Schwarz

author

2008-07-08 08:30 UTC #2 lore raw

Quoted 23 lines · David Gibson

Quoted 3 lines · Andre Schwarz
The mvBlueCOUGAR-P is a MPC5200B based camera system with Intel Gigabit ethernet controller (using e1000). It's just another MPC5200_simple board.
[snip]
arch/powerpc/boot/dts/mvbc-p.dts line 75
Quoted 12 lines
arch/powerpc/boot/dts/mvbc-p.dts new file +11 -0
+		timer@600 {	// General Purpose Timer
+			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+			reg = <0x600 0x10>;
+			interrupts = <1 9 0>;
+			interrupt-parent = <&mpc5200_pic>;
+			fsl,has-wdt;
+		};
+
+		timer@610 {	// General Purpose Timer
+			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+			cell-index = <1>;
What shared resource is this cell-index value used to index?

Quoted 4 lines

Also why does it not appear on the timer@600 but does on all the others.

Sorry - it's a copy paste problem. At first I only used timer0, i.e. this is the original entry.
After Grant wanting me to have a look at the lite5200b.dts I copied over the rest of the dts nodes I also have on my board. On lite5200b.dts the cell-index is defined.

If this is incorrect I'll remove it.
Is cell-index inappropriate for the timer node ?

regards,
Andre

MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner

Grant Likely

2008-07-09 00:54 UTC #3 lore raw

Quoted 28 lines · Andre Schwarz

Quoted 23 lines · David Gibson
Quoted 3 lines · Andre Schwarz
The mvBlueCOUGAR-P is a MPC5200B based camera system with Intel Gigabit ethernet controller (using e1000). It's just another MPC5200_simple board.
[snip]
arch/powerpc/boot/dts/mvbc-p.dts line 75
Quoted 12 lines
arch/powerpc/boot/dts/mvbc-p.dts new file +11 -0
+		timer@600 {	// General Purpose Timer
+			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+			reg = <0x600 0x10>;
+			interrupts = <1 9 0>;
+			interrupt-parent = <&mpc5200_pic>;
+			fsl,has-wdt;
+		};
+
+		timer@610 {	// General Purpose Timer
+			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+			cell-index = <1>;
What shared resource is this cell-index value used to index?
Quoted 4 lines
Also why does it not appear on the timer@600 but does on all the others.

Quoted 8 lines

Sorry - it's a copy paste problem. At first I only used timer0, i.e. this is the original entry.
After Grant wanting me to have a look at the lite5200b.dts I copied over the rest of the dts nodes I also have on my board. On lite5200b.dts the cell-index is defined.
If this is incorrect I'll remove it.
Is cell-index inappropriate for the timer node ?

Yes, you can drop cell-index for fsl,mpc5200-gpt nodes.