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Restore PERR/SERR bit settings during EEH device recovery

PATCH In review Mike Mason 2 participants 4 messages Jul 8, 2008

Subsystems (2)
PowerPC PCI enhanced error handling (eeh) for PowerPC
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Mike Mason

author
#0 lore raw

PATCH 1/1 Restore PERR/SERR bit settings during EEH device recovery

The following patch restores the PERR and SERR bits in the PCI
command register during an EEH device recovery.
We have found at least one case (an Agilent test card) where the
PERR/SERR bits are set to 1 by firmware at boot time, but are
not restored to 1 during EEH recovery. The patch fixes the
Agilent card problem. It has been tested on several other EEH-enabled cards with no regressions.

Signed-off-by Mike Mason <[email protected]>
arch/powerpc/platforms/pseries/eeh.c +0 -0
@@ -812,6 +812,7 @@

static inline void __restore_bars (struct pci_dn *pdn)

{
	int i;

+ u32 cmd;

	if (NULL==pdn->phb) return;
	for (i=4; i<10; i++) {

@@ -832,6 +833,15 @@

	/* max latency, min grant, interrupt pin and line */
	rtas_write_config(pdn, 15*4, 4, pdn->config_space[15]);

+
+ /* Restore PERR & SERR bits, some devices require it,
+ don't touch the other command bits */
+ rtas_read_config(pdn, PCI_COMMAND, 4, &cmd);
+ if (pdn->config_space[1] & PCI_COMMAND_PARITY)
+ cmd |= PCI_COMMAND_PARITY;
+ if (pdn->config_space[1] & PCI_COMMAND_SERR)
+ cmd |= PCI_COMMAND_SERR;
+ rtas_write_config(pdn, PCI_COMMAND, 4, cmd);
}

/**

Acked-by on v1 1/1
#1 lore raw

2008/7/7 Mike Mason <[email protected]>:

Quoted 5 lines

The following patch restores the PERR and SERR bits in the PCI command register during an EEH device recovery.
We have found at least one case (an Agilent test card) where the PERR/SERR bits are set to 1 by firmware at boot time, but are not restored to 1 during EEH recovery.

Any chance they should be zero, and were accidentally set to 1? In which case, you'd need an else clause, below.

Quoted 19 lines

The patch fixes the
Agilent card problem. It has been tested on several other EEH-enabled cards with no regressions.

Signed-off-by Mike Mason <[email protected]>

--- linux-2.6.26-rc9/arch/powerpc/platforms/pseries/eeh.c 2008-07-07
16:06:57.000000000 -0700
+++ linux-2.6.26-rc9-new/arch/powerpc/platforms/pseries/eeh.c 2008-07-07
16:11:10.000000000 -0700

(quoted diff) +1 -0
@@ -812,6 +812,7 @@
 static inline void __restore_bars (struct pci_dn *pdn)
 {
       int i;
+       u32 cmd;
 
       if (NULL==pdn->phb) return;
       for (i=4; i<10; i++) {

Review line 841

Quoted 9 lines
(quoted diff) +6 -0
@@ -832,6 +833,15 @@
 
       /* max latency, min grant, interrupt pin and line */
       rtas_write_config(pdn, 15*4, 4, pdn->config_space[15]);
+
+       /* Restore PERR & SERR bits, some devices require it,
+          don't touch the other command bits */
+       rtas_read_config(pdn, PCI_COMMAND, 4, &cmd);
+       if (pdn->config_space[1] & PCI_COMMAND_PARITY)
+               cmd |= PCI_COMMAND_PARITY;

else cmd &= ~PCI_COMMAND_PARITY;

Review line 843

Quoted 2 lines
(quoted diff) +2 -0
+       if (pdn->config_space[1] & PCI_COMMAND_SERR)
+               cmd |= PCI_COMMAND_SERR;

else cmd &= ~PCI_COMMAND_SERR;

Review line 845

Quoted 2 lines
(quoted diff) +1 -0
+       rtas_write_config(pdn, PCI_COMMAND, 4, cmd);
 }

Other than that, I'll add an

Acked-by Linas Vepstas <[email protected]>

--linas

author
#2 lore raw
Quoted 9 lines · Linas Vepstas

2008/7/7 Mike Mason <[email protected]>:

Quoted 5 lines

The following patch restores the PERR and SERR bits in the PCI command register during an EEH device recovery.
We have found at least one case (an Agilent test card) where the PERR/SERR bits are set to 1 by firmware at boot time, but are not restored to 1 during EEH recovery.

Any chance they should be zero, and were accidentally set to 1? In which case, you'd need an else clause, below.

I suppose it's possible. I'll add your suggestion and resubmit.

Mike

Quoted 45 lines
Quoted 20 lines

The patch fixes the
Agilent card problem. It has been tested on several other EEH-enabled cards with no regressions.

Signed-off-by Mike Mason <[email protected]>

--- linux-2.6.26-rc9/arch/powerpc/platforms/pseries/eeh.c 2008-07-07
16:06:57.000000000 -0700
+++ linux-2.6.26-rc9-new/arch/powerpc/platforms/pseries/eeh.c 2008-07-07
16:11:10.000000000 -0700

(quoted diff) +1 -0
@@ -812,6 +812,7 @@
 static inline void __restore_bars (struct pci_dn *pdn)
 {
       int i;
+       u32 cmd;
 
       if (NULL==pdn->phb) return;
       for (i=4; i<10; i++) {

Review line 841

Quoted 9 lines
(quoted diff) +6 -0
@@ -832,6 +833,15 @@
 
       /* max latency, min grant, interrupt pin and line */
       rtas_write_config(pdn, 15*4, 4, pdn->config_space[15]);
+
+       /* Restore PERR & SERR bits, some devices require it,
+          don't touch the other command bits */
+       rtas_read_config(pdn, PCI_COMMAND, 4, &cmd);
+       if (pdn->config_space[1] & PCI_COMMAND_PARITY)
+               cmd |= PCI_COMMAND_PARITY;

else cmd &= ~PCI_COMMAND_PARITY;

Review line 843

Quoted 2 lines
(quoted diff) +2 -0
+       if (pdn->config_space[1] & PCI_COMMAND_SERR)
+               cmd |= PCI_COMMAND_SERR;

else cmd &= ~PCI_COMMAND_SERR;

Review line 845

Quoted 2 lines
(quoted diff) +1 -0
+       rtas_write_config(pdn, PCI_COMMAND, 4, cmd);
 }

Other than that, I'll add an

Acked-by Linas Vepstas <[email protected]>

--linas

author
#3 lore raw
In reply to Linas Vepstas

Here's a resubmission of the patch with Linas' suggestion.

The following patch restores the PERR and SERR bits in the PCI command register during an EEH device recovery. We have found at least one case (an Agilent test card) where the PERR/SERR bits are set to 1 by firmware at boot time, but are not restored to 1 during EEH recovery. The patch fixes the Agilent card problem. It has been tested on several other EEH-enabled cards with no regressions.

Signed-off-by Mike Mason <[email protected]> Acked-by: Linas Vepstas <[email protected]>
arch/powerpc/platforms/pseries/eeh.c +0 -0
@@ -812,6 +812,7 @@

static inline void __restore_bars (struct pci_dn *pdn)

{
	int i;

+ u32 cmd;

	if (NULL==pdn->phb) return;
	for (i=4; i<10; i++) {

@@ -832,6 +833,19 @@

	/* max latency, min grant, interrupt pin and line */
	rtas_write_config(pdn, 15*4, 4, pdn->config_space[15]);

+
+ /* Restore PERR & SERR bits, some devices require it,
+ don't touch the other command bits */
+ rtas_read_config(pdn, PCI_COMMAND, 4, &cmd);
+ if (pdn->config_space[1] & PCI_COMMAND_PARITY)
+ cmd |= PCI_COMMAND_PARITY;
+ else
+ cmd &= ~PCI_COMMAND_PARITY;
+ if (pdn->config_space[1] & PCI_COMMAND_SERR)
+ cmd |= PCI_COMMAND_SERR;
+ else
+ cmd &= ~PCI_COMMAND_SERR;
+ rtas_write_config(pdn, PCI_COMMAND, 4, cmd);
}

/**