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85xx: various fixes for TQM85xx and support for TQM8548

PATCH Superseded Wolfgang Grandegegr 2 participants 15 messages Jun 5, 2008 – Jul 9, 2008

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Wolfgang Grandegegr

author
#0 lore raw

v2 cover 85xx: various fixes for TQM85xx and support for TQM8548

this is v2 of patches fixing various issues with TQM85xx modules and adding support for TQM8548 modules from TQ Components GmbH (http://www.tqc.de).

Note: The patches rely on "[PATCH v2] TQM: move TQM boards to board/tqc"
sent a few minutes ago to this list.

Wolfgang.

author
#1 lore raw

PATCH v2 1/12 MPC85xx: Beautify boot output of L2 cache configuration

From: Wolfgang Grandegger <[email protected]>

The boot output is now aligned poperly with other boot output lines, e.g.:

FLASH: 128 MB
L2: 512 KB enabled

Signed-off-by Wolfgang Grandegger <[email protected]>
---
 cpu/mpc85xx/cpu.c      |    2 +-
 cpu/mpc85xx/cpu_init.c |   18 ++++++++++--------
 2 files changed, 11 insertions(+), 9 deletions(-)
cpu/mpc85xx/cpu.c +1 -1
index 9873383..274b486 100644
@@ -159,7 +159,7 @@ int checkcpu (void)
 	}
 
 #ifdef CONFIG_CPM2
-	printf("CPM:  %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
+	printf("CPM:   %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
 #endif
 
 	puts("L1:    D-cache 32 kB enabled\n       I-cache 32 kB enabled\n");
cpu/mpc85xx/cpu_init.c +10 -8
index e3240b5..0fb36c4 100644
@@ -265,6 +265,8 @@ int cpu_init_r(void)
 #endif
 #endif
 
+	puts ("L2:    ");
+
 #if defined(CONFIG_L2_CACHE)
 	volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR;
 	volatile uint cache_ctl;

@@ -281,17 +283,17 @@ int cpu_init_r(void)
 	case 0x20000000:
 		if (ver == SVR_8548 || ver == SVR_8548_E ||
 		    ver == SVR_8544 || ver == SVR_8568_E) {
-			printf ("L2 cache 512KB:");
+			puts ("512 KB ");
 			/* set L2E=1, L2I=1, & L2SRAM=0 */
 			cache_ctl = 0xc0000000;
 		} else {
-			printf ("L2 cache 256KB:");
+			puts("256 KB ");
 			/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
 			cache_ctl = 0xc8000000;
 		}
 		break;
 	case 0x10000000:
-		printf ("L2 cache 256KB:");
+		puts("256 KB ");
 		if (ver == SVR_8544 || ver == SVR_8544_E) {
 			cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
 		}

@@ -299,18 +301,18 @@ int cpu_init_r(void)
 	case 0x30000000:
 	case 0x00000000:
 	default:
-		printf ("L2 cache unknown size (0x%08x)\n", cache_ctl);
+		printf(" unknown size (0x%08x)\n", cache_ctl);
 		return -1;
 	}
 
 	if (l2cache->l2ctl & 0x80000000) {
-		printf(" already enabled.");
+		puts("already enabled");
 		l2srbar = l2cache->l2srbar0;
 #ifdef CFG_INIT_L2_ADDR
 		if (l2cache->l2ctl & 0x00010000 && l2srbar >= CFG_FLASH_BASE) {
 			l2srbar = CFG_INIT_L2_ADDR;
 			l2cache->l2srbar0 = l2srbar;
-			printf("  Moving to 0x%08x", CFG_INIT_L2_ADDR);
+			printf("moving to 0x%08x", CFG_INIT_L2_ADDR);
 		}
 #endif /* CFG_INIT_L2_ADDR */
 		puts("\n");

@@ -318,10 +320,10 @@ int cpu_init_r(void)
 		asm("msync;isync");
 		l2cache->l2ctl = cache_ctl; /* invalidate & enable */
 		asm("msync;isync");
-		printf(" enabled\n");
+		puts("enabled\n");
 	}
 #else
-	printf("L2 cache: disabled\n");
+	puts("disabled\n");
 #endif
 #ifdef CONFIG_QE
 	uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */
Signature · 1 line
1.5.4.2
author
#2 lore raw

PATCH v2 2/12 TQM85xx: Various coding style fixes

From: Wolfgang Grandegger <[email protected]>

Signed-off-by Wolfgang Grandegger <[email protected]>
---
 board/tqc/tqm85xx/law.c     |   12 +-
 board/tqc/tqm85xx/sdram.c   |   56 ++++----
 board/tqc/tqm85xx/tlb.c     |   98 +++++++------
 board/tqc/tqm85xx/tqm85xx.c |  330 +++++++++++++++++++++---------------------
 include/configs/TQM85xx.h   |   88 ++++++------
 5 files changed, 293 insertions(+), 291 deletions(-)
board/tqc/tqm85xx/law.c +6 -6
index 224af6c..d937700 100644
@@ -44,11 +44,11 @@
  */
 
 struct law_entry law_table[] = {
-	SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
-	SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
-	SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
-	SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+	SET_LAW_ENTRY (1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
+	SET_LAW_ENTRY (2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW_ENTRY (3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+	SET_LAW_ENTRY (4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
+	SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
 };
 
-int num_law_entries = ARRAY_SIZE(law_table);
+int num_law_entries = ARRAY_SIZE (law_table);
board/tqc/tqm85xx/sdram.c +28 -28

140 lines not on this page · raw message

board/tqc/tqm85xx/tlb.c +52 -46

139 lines not on this page · raw message

board/tqc/tqm85xx/tqm85xx.c +165 -165

404 lines not on this page · raw message

include/configs/TQM85xx.h +42 -46

258 lines not on this page · raw message

Signature · 1 line
1.5.4.2
author
#3 lore raw

PATCH v2 3/12 TQM85xx: Fix CPM port pin configuration

From: Wolfgang Grandegger <[email protected]>

Do not configure port pins PD30/PD31 as SCC1 TxD/RxD except for the TQM8560 board. On the other TQM85xx boards (TQM8541 and TQM8555) SCC1 is not used as serial interface anyway. Worse, on some board variants configuring the pins for SCC1 leads to short circuits (for example on the TQM8541-BG).

Signed-off-by Martin Krause <[email protected]>
---
 board/tqc/tqm85xx/tqm85xx.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)
board/tqc/tqm85xx/tqm85xx.c +6 -0
index 31364d3..af8c170 100644
@@ -165,9 +165,15 @@ const iop_conf_t iop_conf_tab[4][32] = {
 
 	/* Port D: conf, ppar, psor, pdir, podr, pdat */
 	{
+#ifdef CONFIG_TQM8560
 	 {1, 1, 0, 0, 0, 0},	/* PD31: SCC1 EN RxD */
 	 {1, 1, 1, 1, 0, 0},	/* PD30: SCC1 EN TxD */
 	 {1, 1, 0, 1, 0, 0},	/* PD29: SCC1 EN TENA */
+#else /* !CONFIG_TQM8560 */
+	 {0, 0, 0, 0, 0, 0},	/* PD31: PD31 */
+	 {0, 0, 0, 0, 0, 0},	/* PD30: PD30 */
+	 {0, 0, 0, 0, 0, 0},	/* PD29: PD29 */
+#endif /* CONFIG_TQM8560 */
 	 {1, 1, 0, 0, 0, 0},	/* PD28: PD28 */
 	 {1, 1, 0, 1, 0, 0},	/* PD27: PD27 */
 	 {1, 1, 0, 1, 0, 0},	/* PD26: PD26 */
Signature · 1 line
1.5.4.2
author
#4 lore raw

PATCH v2 4/12 TQM85xx: Support for Spansion 'N' type flashes added

From: Wolfgang Grandegger <[email protected]>

The 'N' type Spansion flashes (S29GLxxxN series) have bigger sectors, than the formerly used 'M' types (S29GLxxxM series), so the flash layout needs to be changed -> new start address of the environment. The macro definition CONFIG_TQM_FLASH_N_TYPE is undefined by default and must be defined for boards with 'N' type flashes.

Signed-off-by Martin Krause <[email protected]>
Signed-off-by Wolfgang Grandegger <[email protected]>
---
 include/configs/TQM85xx.h |   20 ++++++++++++++++----
 1 files changed, 16 insertions(+), 4 deletions(-)
include/configs/TQM85xx.h +16 -4
index f0e7318..432c155 100644
@@ -109,6 +109,13 @@
 #endif /* CONFIG_TQM8541 || CONFIG_TQM8555 */
 
 /*
+ * Old TQM85xx boards have 'M' type Spansion Flashes from the S29GLxxxM
+ * series while new boards have 'N' type Flashes from the S29GLxxxN
+ * series, which have bigger sectors: 2 x 128 instead of 2 x 64 KB.
+ */
+#undef CONFIG_TQM_FLASH_N_TYPE
+
+/*
  * Flash on the Local Bus
  */
 #define CFG_FLASH0		0xFC000000

@@ -151,7 +158,7 @@
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 #define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserved for malloc	*/
 
 /* Serial Port */
 #if defined(CONFIG_TQM8560)

@@ -351,10 +358,15 @@
  * Environment
  */
 #define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x20000)
-#define CFG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env	*/
+
+#ifdef CONFIG_TQM_FLASH_N_TYPE
+#define CFG_ENV_SECT_SIZE	0x40000 /* 256K (one sector) for env	*/
+#else /* !CONFIG_TQM_FLASH_N_TYPE */
+#define CFG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) for env	*/
+#endif /* CONFIG_TQM_FLASH_N_TYPE */
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
 #define CFG_ENV_SIZE		0x2000
-#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
 #define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
Signature · 1 line
1.5.4.2
author
#5 lore raw

PATCH v2 5/12 TQM85xx: Fix chip select configuration for second FLASH bank

From: Wolfgang Grandegger <[email protected]>

This patch fixes the re-calculation of the automatic chip select configuration for boards with two populated FLASH banks.

Signed-off-by Martin Krause <[email protected]>
---
 board/tqc/tqm85xx/tqm85xx.c |   84 +++++++++++++++++++++++-------------------
 1 files changed, 46 insertions(+), 38 deletions(-)
board/tqc/tqm85xx/tqm85xx.c +46 -38
index af8c170..a45df2b 100644
@@ -275,52 +275,60 @@ int misc_init_r (void)
 	gd->bd->bi_flashoffset = 0;
 
 	/*
-	 * Check if boot FLASH isn't max size
+	 * Recalculate CS configuration if second FLASH bank is available
 	 */
-	if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) {
-		memctl->or0 =
-		    gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff);
-		memctl->br0 =
-		    gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff);
-
+	if (flash_info[0].size > 0) {
+		memctl->or1 = ((-flash_info[0].size) & 0xffff8000) |
+			(CFG_OR1_PRELIM & 0x00007fff);
+		memctl->br1 = gd->bd->bi_flashstart |
+			(CFG_BR1_PRELIM & 0x00007fff);
 		/*
-		 * Re-check to get correct base address
+		 * Re-check to get correct base address for bank 1
 		 */
-		flash_get_size (gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
+		flash_get_size (gd->bd->bi_flashstart, 0);
+	} else {
+		memctl->or1 = 0;
+		memctl->br1 = 0;
 	}
 
 	/*
-	 * Check if only one FLASH bank is available
+	 *  If bank 1 is equipped, bank 0 is mapped after bank 1
 	 */
-	if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
-		memctl->or1 = 0;
-		memctl->br1 = 0;
+	memctl->or0 = ((-flash_info[1].size) & 0xffff8000) |
+		(CFG_OR0_PRELIM & 0x00007fff);
+	memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) |
+		(CFG_BR0_PRELIM & 0x00007fff);
+	/*
+	 * Re-check to get correct base address for bank 0
+	 */
+	flash_get_size (gd->bd->bi_flashstart + flash_info[0].size, 1);
 
-		/*
-		 * Re-do flash protection upon new addresses
-		 */
-		flash_protect (FLAG_PROTECT_CLEAR,
-			       gd->bd->bi_flashstart, 0xffffffff,
-			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
-
-		/* Monitor protection ON by default */
-		flash_protect (FLAG_PROTECT_SET,
-			       CFG_MONITOR_BASE,
-			       CFG_MONITOR_BASE + monitor_flash_len - 1,
-			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
-
-		/* Environment protection ON by default */
-		flash_protect (FLAG_PROTECT_SET,
-			       CFG_ENV_ADDR,
-			       CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
-			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
-
-		/* Redundant environment protection ON by default */
-		flash_protect (FLAG_PROTECT_SET,
-			       CFG_ENV_ADDR_REDUND,
-			       CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
-			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
-	}
+	/*
+	 * Re-do flash protection upon new addresses
+	 */
+	flash_protect (FLAG_PROTECT_CLEAR,
+		       gd->bd->bi_flashstart, 0xffffffff,
+		       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+	/* Monitor protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + monitor_flash_len - 1,
+		       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+	/* Environment protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+		       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+#ifdef CFG_ENV_ADDR_REDUND
+	/* Redundant environment protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR_REDUND,
+		       CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+		       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+#endif
 
 	return 0;
 }
Signature · 1 line
1.5.4.2
author
#6 lore raw

PATCH v2 6/12 TQM85xx: Bugfix in the SDRAM initialisation

From: Wolfgang Grandegger <[email protected]>

The CS0_BNDS register is now set according to the detected memory size.

Signed-off-by Martin Krause <[email protected]>

---
 board/tqc/tqm85xx/sdram.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)
board/tqc/tqm85xx/sdram.c +3 -1
index 413567e..e005d84 100644
@@ -104,8 +104,10 @@ long int sdram_setup (int casl)
 		if (get_ram_size (0, ddr_cs_conf[i].size) ==
 		    ddr_cs_conf[i].size) {
 			/*
-			 * OK, size detected -> all done
+			 * size detected -> set Chip Select Bounds Register
 			 */
+			ddr->cs0_bnds = (ddr_cs_conf[i].size - 1) >> 24;
+
 			return ddr_cs_conf[i].size;
 		}
 	}
Signature · 1 line
1.5.4.2
author
#7 lore raw

PATCH v2 7/12 TQM85xx: Support for Intel 82527 compatible CAN controller

From: Wolfgang Grandegger <[email protected]>

This patch adds initialization of the UPMC RAM to support up to two Intel 82527 compatible CAN controller on the TQM85xx modules.

Signed-off-by Thomas Waehner <[email protected]>
Signed-off-by Wolfgang Grandegger <[email protected]>
---
 board/tqc/tqm85xx/law.c     |    4 +++
 board/tqc/tqm85xx/tlb.c     |    1 +
 board/tqc/tqm85xx/tqm85xx.c |   57 +++++++++++++++++++++++++++++++++++++++++++
 include/configs/TQM85xx.h   |   11 ++++++++
 4 files changed, 73 insertions(+), 0 deletions(-)
board/tqc/tqm85xx/law.c +4 -0
index d937700..ad35464 100644
@@ -35,6 +35,7 @@
  * 0xc000_0000	   0xdfff_ffff	   RapidIO		   512M
  * 0xe000_0000	   0xe000_ffff	   CCSR			   1M
  * 0xe200_0000	   0xe2ff_ffff	   PCI1 IO		   16M
+ * 0xe300_0000	   0xe3ff_ffff	   CAN			   16M
  * 0xf800_0000	   0xf80f_ffff	   BCSR			   1M
  * 0xfe00_0000	   0xffff_ffff	   FLASH (boot bank)	   32M
  *

@@ -49,6 +50,9 @@ struct law_entry law_table[] = {
 	SET_LAW_ENTRY (3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
 	SET_LAW_ENTRY (4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
 	SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+#ifdef CONFIG_CAN_DRIVER
+	SET_LAW_ENTRY (6, CFG_CAN_BASE, LAWAR_SIZE_16M, LAW_TRGT_IF_LBC),
+#endif /* CONFIG_CAN_DRIVER */
 };
 
 int num_law_entries = ARRAY_SIZE (law_table);
board/tqc/tqm85xx/tlb.c +1 -0
index 3e29062..dc36201 100644
@@ -95,6 +95,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * TLB 6:	 64M	Non-cacheable, guarded
 	 * 0xe0000000	  1M	CCSRBAR
 	 * 0xe2000000	 16M	PCI1 IO
+	 * 0xe3000000	 16M	CAN
 	 */
 	SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
board/tqc/tqm85xx/tqm85xx.c +57 -0

75 lines not on this page · raw message

include/configs/TQM85xx.h +11 -0
index 432c155..17df118 100644
@@ -52,6 +52,8 @@
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code	*/
 
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support		*/
+
 /*
  * sysclk for MPC85xx
  *

@@ -199,6 +201,15 @@
 #define	CFG_PROMPT_HUSH_PS2	"> "
 #endif
 
+/* CAN */
+#ifdef CONFIG_CAN_DRIVER
+#define CFG_CAN_BASE		0xE3000000	/* CAN base address     */
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 KiB address mask  */
+#define CFG_OR2_CAN		(CFG_CAN_OR_AM | OR_UPM_BI)
+#define CFG_BR2_CAN		((CFG_CAN_BASE & BR_BA) | \
+				 BR_PS_8 | BR_MS_UPMC | BR_V)
+#endif /* CONFIG_CAN_DRIVER */
+
 /*
  * I2C
  */
Signature · 1 line
1.5.4.2
author
#8 lore raw

PATCH v2 8/12 TQM85xx: Support for Flat Device Tree

From: Wolfgang Grandegger <[email protected]>

This patch adds support for Linux kernels using the Flat Device Tree. It also re-defines the default environment settings for booting Linux with the FDT blob.

Signed-off-by Wolfgang Grandegger <[email protected]>
---
 Makefile                    |    3 +-
 board/tqc/tqm85xx/tqm85xx.c |   24 ++++++++++++++++++++
 include/configs/TQM85xx.h   |   50 +++++++++++++++++++++++++++++++++---------
 3 files changed, 64 insertions(+), 13 deletions(-)
Makefile +1 -2
index 72456b2..c0b73e1 100644
@@ -2238,8 +2238,7 @@ TQM8560_config:		unconfig
 	echo "#define CONFIG_MPC$${CTYPE}">>$(obj)include/config.h; \
 	echo "#define CONFIG_TQM$${CTYPE}">>$(obj)include/config.h; \
 	echo "#define CONFIG_HOSTNAME tqm$${CTYPE}">>$(obj)include/config.h; \
-	echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h; \
-	echo "#define CFG_BOOTFILE_PATH \"/tftpboot/tqm$${CTYPE}/uImage\"">>$(obj)include/config.h
+	echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h;
 	@$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx tqc
 
 #########################################################################
board/tqc/tqm85xx/tqm85xx.c +24 -0
index 4fb9c11..17df3bb 100644
@@ -34,6 +34,8 @@
 #include <asm/io.h>
 #include <ioports.h>
 #include <flash.h>
+#include <libfdt.h>
+#include <fdt_support.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -479,6 +481,28 @@ void pci_init_board (void)
 #endif /* CONFIG_PCI */
 }
 
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup (void *blob, bd_t *bd)
+{
+	int node, tmp[2];
+	const char *path;
+
+	ft_cpu_setup (blob, bd);
+
+	node = fdt_path_offset (blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
+#ifdef CONFIG_PCI
+		path = fdt_getprop (blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = hose.last_busno - hose.first_busno;
+			do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+	}
+}
+#endif
+
 #ifdef CONFIG_BOARD_EARLY_INIT_R
 int board_early_init_r (void)
 {
include/configs/TQM85xx.h +39 -11

72 lines not on this page · raw message

Signature · 1 line
1.5.4.2
author
#9 lore raw

PATCH v2 9/12 TQM8548: Basic support for the TQM8548 modules

From: Wolfgang Grandegger <[email protected]>

This patch adds basic support for the TQM8548 module from TQ-Components
(http://www.tqc.de/) including DDR2 SDRAM initialisation and support for eTSEC 3 and 4

Furthermore Flash buffer write has been enabled to speed up output to the Flash by approx. a factor of 10.

Signed-off-by Thomas Waehner <[email protected]>
Signed-off-by Wolfgang Grandegger <[email protected]>
---
 MAKEALL                     |    1 +
 Makefile                    |    1 +
 board/tqc/tqm85xx/sdram.c   |  150 ++++++++++++++++++++++++++++++++++++++++++-
 board/tqc/tqm85xx/tqm85xx.c |  113 ++++++++++++++++++++++++++++----
 drivers/input/ps2ser.c      |   31 ++++++---
 include/configs/TQM85xx.h   |   71 ++++++++++++++++++--
 6 files changed, 334 insertions(+), 33 deletions(-)
MAKEALL +1 -0
index 3cb1d24..8fb1e86 100755
@@ -360,6 +360,7 @@ LIST_85xx="		\
 	stxssa		\
 	TQM8540		\
 	TQM8541		\
+	TQM8548		\
 	TQM8555		\
 	TQM8560		\
 "
Makefile +1 -0
index c0b73e1..894466b 100644
@@ -2230,6 +2230,7 @@ stxssa_4M_config:	unconfig
 
 TQM8540_config		\
 TQM8541_config		\
+TQM8548_config		\
 TQM8555_config		\
 TQM8560_config:		unconfig
 	@mkdir -p $(obj)include
board/tqc/tqm85xx/sdram.c +148 -2

195 lines not on this page · raw message

board/tqc/tqm85xx/tqm85xx.c +100 -13

156 lines not on this page · raw message

drivers/input/ps2ser.c +21 -10
index 4e304f7..c1741ea 100644
@@ -49,7 +49,8 @@ DECLARE_GLOBAL_DATA_PTR;
 #error CONFIG_PS2SERIAL must be in 1 ... 6
 #endif
 
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
+      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
 
 #if CONFIG_PS2SERIAL == 1
 #define COM_BASE (CFG_CCSRBAR+0x4500)

@@ -65,7 +66,9 @@ static int	ps2ser_getc_hw(void);
 static void	ps2ser_interrupt(void *dev_id);
 
 extern struct	serial_state rs_table[]; /* in serial.c */
-#if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && !defined(CONFIG_MPC8555)
+#if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC8540) && \
+    !defined(CONFIG_MPC8541) && !defined(CONFIG_MPC8548) && \
+    !defined(CONFIG_MPC8555)
 static struct	serial_state *state;
 #endif
 

@@ -120,7 +123,8 @@ int ps2ser_init(void)
 	return (0);
 }
 
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
+      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
 int ps2ser_init(void)
 {
 	NS16550_t com_port = (NS16550_t)COM_BASE;

@@ -186,7 +190,8 @@ void ps2ser_putc(int chr)
 {
 #ifdef CONFIG_MPC5xxx
 	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
+      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
 	NS16550_t com_port = (NS16550_t)COM_BASE;
 #endif
 #ifdef DEBUG

@@ -197,7 +202,8 @@ void ps2ser_putc(int chr)
 	while (!(psc->psc_status & PSC_SR_TXRDY));
 
 	psc->psc_buffer_8 = chr;
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
+      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
 	while ((com_port->lsr & LSR_THRE) == 0);
 	com_port->thr = chr;
 #else

@@ -211,7 +217,8 @@ static int ps2ser_getc_hw(void)
 {
 #ifdef CONFIG_MPC5xxx
 	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
+      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
 	NS16550_t com_port = (NS16550_t)COM_BASE;
 #endif
 	int res = -1;

@@ -220,7 +227,8 @@ static int ps2ser_getc_hw(void)
 	if (psc->psc_status & PSC_SR_RXRDY) {
 		res = (psc->psc_buffer_8);
 	}
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
+      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
 	if (com_port->lsr & LSR_DR) {
 		res = com_port->rbr;
 	}

@@ -279,7 +287,8 @@ static void ps2ser_interrupt(void *dev_id)
 {
 #ifdef CONFIG_MPC5xxx
 	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
+      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
 	NS16550_t com_port = (NS16550_t)COM_BASE;
 #endif
 	int chr;

@@ -289,7 +298,8 @@ static void ps2ser_interrupt(void *dev_id)
 		chr = ps2ser_getc_hw();
 #ifdef CONFIG_MPC5xxx
 		status = psc->psc_status;
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
+      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
 		status = com_port->lsr;
 #else
 		status = ps2ser_in(UART_IIR);

@@ -305,7 +315,8 @@ static void ps2ser_interrupt(void *dev_id)
 		}
 #ifdef CONFIG_MPC5xxx
 	} while (status & PSC_SR_RXRDY);
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
+      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
 	} while (status & LSR_DR);
 #else
 	} while (status & UART_IIR_RDI);
include/configs/TQM85xx.h +63 -8

131 lines not on this page · raw message

Signature · 1 line
1.5.4.2
author
#10 lore raw

PATCH v2 10/12 TQM8548: PCI express support

From: Wolfgang Grandegger <[email protected]>

This patch adds support for PCI express cards. The board support now uses common FSL PCI init code, for both, PCI and PCIe on all TQM85xx modules.

Signed-off-by Thomas Waehner <[email protected]>
Signed-off-by Wolfgang Grandegger <[email protected]>
---
 board/tqc/tqm85xx/law.c     |   15 +++-
 board/tqc/tqm85xx/tlb.c     |   30 ++++++
 board/tqc/tqm85xx/tqm85xx.c |  205 ++++++++++++++++++++++++++++++++++++-------
 include/configs/TQM85xx.h   |   35 +++++++-
 4 files changed, 249 insertions(+), 36 deletions(-)
board/tqc/tqm85xx/law.c +11 -4
index ad35464..bec1ed5 100644
@@ -32,11 +32,11 @@
  *
  * 0x0000_0000	   0x7fff_ffff	   DDR			   2G
  * 0x8000_0000	   0x9fff_ffff	   PCI1 MEM		   512M
- * 0xc000_0000	   0xdfff_ffff	   RapidIO		   512M
+ * 0xc000_0000	   0xdfff_ffff	   RapidIO or PCI express  512M
  * 0xe000_0000	   0xe000_ffff	   CCSR			   1M
  * 0xe200_0000	   0xe2ff_ffff	   PCI1 IO		   16M
  * 0xe300_0000	   0xe3ff_ffff	   CAN			   16M
- * 0xf800_0000	   0xf80f_ffff	   BCSR			   1M
+ * 0xef00_0000	   0xefff_ffff     PCI express IO          16M
  * 0xfe00_0000	   0xffff_ffff	   FLASH (boot bank)	   32M
  *
  * Notes:

@@ -49,10 +49,17 @@ struct law_entry law_table[] = {
 	SET_LAW_ENTRY (2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
 	SET_LAW_ENTRY (3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
 	SET_LAW_ENTRY (4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
-	SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+#ifdef CONFIG_PCIE1
+	SET_LAW_ENTRY (5, CFG_PCIE1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+#else /* !CONFIG_PCIE1 */
+	SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+#endif /* CONFIG_PCIE1 */
 #ifdef CONFIG_CAN_DRIVER
-	SET_LAW_ENTRY (6, CFG_CAN_BASE, LAWAR_SIZE_16M, LAW_TRGT_IF_LBC),
+	SET_LAW_ENTRY (6, CFG_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
 #endif /* CONFIG_CAN_DRIVER */
+#ifdef CONFIG_PCIE1
+	SET_LAW_ENTRY (7, CFG_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1),
+#endif /* CONFIG_PCIE */
 };
 
 int num_law_entries = ARRAY_SIZE (law_table);
board/tqc/tqm85xx/tlb.c +30 -0
index dc36201..7c4b9a1 100644
@@ -74,6 +74,24 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 3, BOOKE_PAGESZ_256M, 1),
 
+#ifdef CONFIG_PCIE1
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xc0000000	256M	PCI express MEM First half
+	 */
+	SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 5:	256M	Non-cacheable, guarded
+	 * 0xd0000000	256M	PCI express MEM Second half
+	 */
+	SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE + 0x10000000,
+		       CFG_PCIE1_MEM_BASE + 0x10000000,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 5, BOOKE_PAGESZ_256M, 1),
+#else /* !CONFIG_PCIE */
 	/*
 	 * TLB 4:	256M	Non-cacheable, guarded
 	 * 0xc0000000	256M	Rapid IO MEM First half

@@ -90,6 +108,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		       CFG_RIO_MEM_BASE + 0x10000000,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 5, BOOKE_PAGESZ_256M, 1),
+#endif /* CONFIG_PCIE */
 
 	/*
 	 * TLB 6:	 64M	Non-cacheable, guarded

@@ -116,6 +135,17 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		       CFG_DDR_SDRAM_BASE + 0x10000000,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 8, BOOKE_PAGESZ_256M, 1),
+
+#ifdef CONFIG_PCIE1
+	/*
+	 * TLB 9:	 16M	Non-cacheable, guarded
+	 * 0xef000000	 16M	PCI express IO
+	 */
+	SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 9, BOOKE_PAGESZ_16M, 1),
+#endif /* CONFIG_PCIE */
+
 };
 
 int num_tlb_entries = ARRAY_SIZE (tlb_table);
board/tqc/tqm85xx/tqm85xx.c +174 -31

247 lines not on this page · raw message

include/configs/TQM85xx.h +34 -1
index a02d001..2155130 100644
@@ -42,6 +42,14 @@
 #define CONFIG_MPC85xx		1	/* MPC8540/60/55/41		*/
 
 #define CONFIG_PCI
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code	*/
+#define CONFIG_PCIX_CHECK		/* PCIX olny works at 66 MHz	*/
+#ifdef CONFIG_TQM8548
+#define CONFIG_PCI1
+#define CONFIG_PCIE1
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata	*/
+#endif
+
 #define CONFIG_TSEC_ENET		/* tsec ethernet support	*/
 
 #define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/

@@ -97,6 +105,10 @@
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
+#define CFG_PCI1_ADDR		(CFG_CCSRBAR + 0x8000)
+#define CFG_PCI2_ADDR		(CFG_CCSRBAR + 0x9000)
+#define CFG_PCIE1_ADDR		(CFG_CCSRBAR + 0xa000)
+
 /*
  * DDR Setup
  */

@@ -282,10 +294,12 @@
 #define CFG_DTT_LOW_TEMP	-30
 #define CFG_DTT_HYSTERESIS	3
 
+#ifndef CONFIG_PCIE1
 /* RapidIO MMU */
 #define CFG_RIO_MEM_BASE	0xc0000000	/* base address		*/
 #define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
-#define CFG_RIO_MEM_SIZE	0x20000000	/* 128M			*/
+#define CFG_RIO_MEM_SIZE	0x20000000	/* 512M			*/
+#endif /* CONFIG_PCIE1 */
 
 /*
  * General PCI

@@ -298,6 +312,25 @@
 #define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
 #define CFG_PCI1_IO_SIZE	0x1000000	/*  16M			*/
 
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS	0x00000000
+#define CFG_PCI_MEMORY_PHYS	0x00000000
+#define CFG_PCI_MEMORY_SIZE	0x80000000
+
+#ifdef CONFIG_PCIE1
+/*
+ * General PCI express
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCIE1_MEM_BASE	0xc0000000
+#define CFG_PCIE1_MEM_PHYS	CFG_PCIE1_MEM_BASE
+#define CFG_PCIE1_MEM_SIZE	0x20000000      /* 512M                 */
+#define CFG_PCIE1_IO_BASE	0xef000000
+#define CFG_PCIE1_IO_PHYS	CFG_PCIE1_IO_BASE
+#define CFG_PCIE1_IO_SIZE	0x1000000       /* 16M                  */
+
+#endif /* CONFIG_PCIE1 */
+
 #if defined(CONFIG_PCI)
 
 #define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
Signature · 1 line
1.5.4.2
author
#11 lore raw

PATCH v2 11/12 TQM85xx: NAND support via local bus UPMB

From: Wolfgang Grandegger <[email protected]>

This patch adds support for NAND FLASH on the TQM8548. It is disabled by default and can be enabled for the TQM8548 modules. It is now based on the re-written FSL NAND UPM driver. A patch has been posted earlier today with the subject:

"NAND FSL UPM: driver re-write using the hwcontrol callback"

Note that the R/B pin is not supported by that module requiring to use the specified maximum delay time.

Note: With NAND support enabled the size of the U-Boot image exceeds 256 KB and TEXT_BASE must therefore be set to 0xfff80000 in config.mk, doubling the image size :-(.

Signed-off-by Thomas Waehner <[email protected]>
Signed-off-by Wolfgang Grandegger <[email protected]>
---
 board/tqc/tqm85xx/Makefile |    8 +-
 board/tqc/tqm85xx/law.c    |    6 +-
 board/tqc/tqm85xx/nand.c   |  469 ++++++++++++++++++++++++++++++++++++++++++++
 board/tqc/tqm85xx/tlb.c    |    2 +-
 include/configs/TQM85xx.h  |   81 ++++++++-
 5 files changed, 558 insertions(+), 8 deletions(-)
 create mode 100644 board/tqc/tqm85xx/nand.c
board/tqc/tqm85xx/Makefile +7 -1
index 52f5ef9..8ea07f2 100644
@@ -25,8 +25,14 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o sdram.o law.o tlb.o
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= sdram.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
 
+COBJS-$(CONFIG_NAND) += nand.o
+
+COBJS	:= $(COBJS-y)
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
board/tqc/tqm85xx/law.c +3 -3
index bec1ed5..914ce68 100644
@@ -35,7 +35,7 @@
  * 0xc000_0000	   0xdfff_ffff	   RapidIO or PCI express  512M
  * 0xe000_0000	   0xe000_ffff	   CCSR			   1M
  * 0xe200_0000	   0xe2ff_ffff	   PCI1 IO		   16M
- * 0xe300_0000	   0xe3ff_ffff	   CAN			   16M
+ * 0xe300_0000	   0xe3ff_ffff	   CAN and NAND Flash	   16M
  * 0xef00_0000	   0xefff_ffff     PCI express IO          16M
  * 0xfe00_0000	   0xffff_ffff	   FLASH (boot bank)	   32M
  *

@@ -54,9 +54,9 @@ struct law_entry law_table[] = {
 #else /* !CONFIG_PCIE1 */
 	SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 #endif /* CONFIG_PCIE1 */
-#ifdef CONFIG_CAN_DRIVER
+#if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND)
 	SET_LAW_ENTRY (6, CFG_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
-#endif /* CONFIG_CAN_DRIVER */
+#endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */
 #ifdef CONFIG_PCIE1
 	SET_LAW_ENTRY (7, CFG_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1),
 #endif /* CONFIG_PCIE */
board/tqc/tqm85xx/nand.c new file +469 -0

469 lines not on this page · raw message

board/tqc/tqm85xx/tlb.c +1 -1
index 7c4b9a1..7f4efc1 100644
@@ -114,7 +114,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * TLB 6:	 64M	Non-cacheable, guarded
 	 * 0xe0000000	  1M	CCSRBAR
 	 * 0xe2000000	 16M	PCI1 IO
-	 * 0xe3000000	 16M	CAN
+	 * 0xe3000000	 16M	CAN and NAND Flash
 	 */
 	SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
include/configs/TQM85xx.h +78 -3

112 lines not on this page · raw message

Signature · 1 line
1.5.4.2
author
#12 lore raw

PATCH v2 12/12 TQM85xx: Change memory map to support Flash memory > 128 MiB

From: Wolfgang Grandegger <[email protected]>

Some TQM85xx boards could be equipped with up to 1 GiB (NOR) Flash memory. The current memory map only supports up to 128 MiB Flash. This patch adds the configuration option CONFIG_TQM_BIGFLASH. If set, up to 1 GiB flash is supported. To achieve this, the memory map has to be adjusted in great parts (for example the CCSRBAR is moved from 0xE0000000 to 0xA0000000).

If you want to boot Linux with CONFIG_TQM_BIGFLASH set, the new memory map also has to be considered in the kernel (changed CCSRBAR address, changed PCI IO base address, ...). Please use an appropriate Flat Device Tree blob (tqm8548.dtb).

Signed-off-by Martin Krause <[email protected]>
Signed-off-by Wolfgang Grandegger <[email protected]>
---
 board/tqc/tqm85xx/law.c   |   29 ++++++++++++--
 board/tqc/tqm85xx/tlb.c   |   97 +++++++++++++++++++++++++++++++++++++++++++++
 include/configs/TQM85xx.h |   52 +++++++++++++++++++++---
 3 files changed, 167 insertions(+), 11 deletions(-)
board/tqc/tqm85xx/law.c +25 -4
index 914ce68..b4e663b 100644
@@ -30,6 +30,8 @@
 /*
  * LAW(Local Access Window) configuration:
  *
+ * Standard mapping:
+ *
  * 0x0000_0000	   0x7fff_ffff	   DDR			   2G
  * 0x8000_0000	   0x9fff_ffff	   PCI1 MEM		   512M
  * 0xc000_0000	   0xdfff_ffff	   RapidIO or PCI express  512M

@@ -37,22 +39,41 @@
  * 0xe200_0000	   0xe2ff_ffff	   PCI1 IO		   16M
  * 0xe300_0000	   0xe3ff_ffff	   CAN and NAND Flash	   16M
  * 0xef00_0000	   0xefff_ffff     PCI express IO          16M
- * 0xfe00_0000	   0xffff_ffff	   FLASH (boot bank)	   32M
+ * 0xfc00_0000	   0xffff_ffff	   FLASH (boot bank)	   128M
+ *
+ * Big FLASH mapping:
+ *
+ * 0x0000_0000	   0x7fff_ffff	   DDR			   2G
+ * 0x8000_0000	   0x9fff_ffff	   PCI1 MEM		   512M
+ * 0xa000_0000	   0xa000_ffff	   CCSR			   1M
+ * 0xa200_0000	   0xa2ff_ffff	   PCI1 IO		   16M
+ * 0xa300_0000	   0xa3ff_ffff	   CAN and NAND Flash	   16M
+ * 0xaf00_0000	   0xafff_ffff     PCI express IO          16M
+ * 0xb000_0000	   0xbfff_ffff	   RapidIO or PCI express  256M
+ * 0xc000_0000	   0xffff_ffff	   FLASH (boot bank)	   1G
  *
  * Notes:
  *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
  *    If flash is 8M at default position (last 8M), no LAW needed.
  */
 
+#ifdef CONFIG_TQM_BIGFLASH
+#define LAW_3_SIZE LAW_SIZE_1G
+#define LAW_5_SIZE LAW_SIZE_256M
+#else
+#define LAW_3_SIZE LAW_SIZE_128M
+#define LAW_5_SIZE LAW_SIZE_512M
+#endif
+
 struct law_entry law_table[] = {
 	SET_LAW_ENTRY (1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
 	SET_LAW_ENTRY (2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW_ENTRY (3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+	SET_LAW_ENTRY (3, CFG_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC),
 	SET_LAW_ENTRY (4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
 #ifdef CONFIG_PCIE1
-	SET_LAW_ENTRY (5, CFG_PCIE1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW_ENTRY (5, CFG_PCIE1_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1),
 #else /* !CONFIG_PCIE1 */
-	SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+	SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO),
 #endif /* CONFIG_PCIE1 */
 #if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND)
 	SET_LAW_ENTRY (6, CFG_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
board/tqc/tqm85xx/tlb.c +97 -0

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include/configs/TQM85xx.h +45 -7

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1.5.4.2
#13 lore raw

v2 cover 85xx: various fixes for TQM85xx and support for TQM8548

In reply to Wolfgang Grandegegr
Quoted 7 lines · Wolfgang Grandegegr

this is v2 of patches fixing various issues with TQM85xx modules and adding support for TQM8548 modules from TQ Components GmbH (http://www.tqc.de).

Note: The patches rely on "[PATCH v2] TQM: move TQM boards to board/tqc"
sent a few minutes ago to this list.

Wolfgang.

BTW, I applied all of these while the window was open, I just never sent a confirmation email.

Thanks!

Andy

author
#14 lore raw

v2 cover 85xx: various fixes for TQM85xx and support for TQM8548

Hi Andy,

Quoted 4 lines · Andy Fleming
Quoted 3 lines · Wolfgang Grandegegr

this is v2 of patches fixing various issues with TQM85xx modules and adding support for TQM8548 modules from TQ Components GmbH (http://www.tqc.de).

Quoted 8 lines
Quoted 4 lines

Note: The patches rely on "[PATCH v2] TQM: move TQM boards to board/tqc"
sent a few minutes ago to this list.

Wolfgang.

BTW, I applied all of these while the window was open, I just never sent a confirmation email.

OK, no problem.

Quoted 1 line

Thanks!

Thank you as well.

Wolfgang.