Various arch/powerpc changes to support the 750GX cpufreq driver

Index: arch/powerpc/kernel/Makefile
===================================================================
@@ -17,6 +17,7 @@ obj-y				:= cputable.o ptrace.o syscalls
 				   init_task.o process.o systbl.o idle.o \
 				   signal.o
 obj-y				+= vdso32/
+obj-y				+= cpu/
 obj-$(CONFIG_PPC64)		+= setup_64.o sys_ppc32.o \
 				   signal_64.o ptrace32.o \
 				   paca.o cpu_setup_ppc970.o \

Index: arch/powerpc/kernel/cpu_setup_6xx.S
===================================================================
@@ -53,6 +53,14 @@ _GLOBAL(__setup_cpu_750fx)
 	bl	setup_750fx
 	mtlr	r4
 	blr
+_GLOBAL(__setup_cpu_750gx)
+	mflr	r4
+	bl	__init_fpu_registers
+	bl	setup_common_caches
+	bl	setup_750_7400_hid0
+	bl	setup_750gx
+	mtlr	r4
+	blr
 _GLOBAL(__setup_cpu_7400)
 	mflr	r4
 	bl	__init_fpu_registers

@@ -200,6 +208,11 @@ setup_750cx:
 setup_750fx:
 	blr
 
+/* 750gx specific
+ */
+setup_750gx:
+	blr
+
 /* MPC 745x
  * Enable Store Gathering (SGE), Branch Folding (FOLD)
  * Branch History Table (BHTE), Branch Target ICache (BTIC)

Index: arch/powerpc/kernel/idle_6xx.S
===================================================================
@@ -45,11 +45,6 @@ BEGIN_FTR_SECTION
 	addis	r6,r5, nap_save_msscr0@ha
 	stw	r4,nap_save_msscr0@l(r6)
 END_FTR_SECTION_IFSET(CPU_FTR_NAP_DISABLE_L2_PR)
-BEGIN_FTR_SECTION
-	mfspr	r4,SPRN_HID1
-	addis	r6,r5,nap_save_hid1@ha
-	stw	r4,nap_save_hid1@l(r6)
-END_FTR_SECTION_IFSET(CPU_FTR_DUAL_PLL_750FX)
 	blr
 
 /*

@@ -107,18 +102,6 @@ BEGIN_FTR_SECTION
 	dcbf	0,r4
 END_FTR_SECTION_IFSET(CPU_FTR_NAP_DISABLE_L2_PR)
 2:
-BEGIN_FTR_SECTION
-	/* Go to low speed mode on some 750FX */
-	lis	r4,powersave_lowspeed@ha
-	lwz	r4,powersave_lowspeed@l(r4)
-	cmpwi	0,r4,0
-	beq	1f
-	mfspr	r4,SPRN_HID1
-	oris	r4,r4,0x0001
-	mtspr	SPRN_HID1,r4
-1:	
-END_FTR_SECTION_IFSET(CPU_FTR_DUAL_PLL_750FX)
-
 	/* Go to NAP or DOZE now */	
 	mfspr	r4,SPRN_HID0
 	lis	r5,(HID0_NAP|HID0_SLEEP)@h

@@ -178,20 +161,9 @@ BEGIN_FTR_SECTION
 	isync
 1:
 END_FTR_SECTION_IFSET(CPU_FTR_NAP_DISABLE_L2_PR)
-BEGIN_FTR_SECTION
-	addis	r9,r11,(nap_save_hid1-KERNELBASE)@ha
-	lwz	r9,nap_save_hid1@l(r9)
-	mtspr	SPRN_HID1, r9
-END_FTR_SECTION_IFSET(CPU_FTR_DUAL_PLL_750FX)
 	b	transfer_to_handler_cont
 
 	.data
 
 _GLOBAL(nap_save_msscr0)
 	.space	4*NR_CPUS
-
-_GLOBAL(nap_save_hid1)
-	.space	4*NR_CPUS
-
-_GLOBAL(powersave_lowspeed)
-	.long	0

Index: arch/powerpc/platforms/Kconfig
===================================================================
@@ -174,7 +174,7 @@ config GENERIC_IOMAP
 	bool
 	default n
 
-source "drivers/cpufreq/Kconfig"
+source "arch/powerpc/kernel/cpu/cpufreq/Kconfig"
 
 menu "CPU Frequency drivers"
 	depends on CPU_FREQ

Index: arch/powerpc/platforms/Kconfig.cputype
===================================================================
@@ -234,4 +234,34 @@ config NOT_COHERENT_CACHE
 config CHECK_CACHE_COHERENCY
 	bool
 
+config PPC_750GX_DUAL_PLL_IF
+	tristate 'Add interface for 750GX PLL' if 6xx
+	---help---
+	  This adds code to provide control of the pll config register in IBM
+	  750GX (and FX?). This is also needed by the cpufreq driver for the
+	  750GX. At least one of the interfaces below must be selected.
+
+	  If in doubt, say N here.
+
+config PPC_750GX_DUAL_PLL_IF_HRTIMER
+	bool "Use HRtimer for PLL lock delay"
+	depends on PPC_750GX_DUAL_PLL_IF
+	default n
+	help
+	  Uses HRtimers for lower latency on PLL locks.
+
+config PPC_750GX_DUAL_PLL_IF_CPU_FREQ
+	bool "Include CPUFreq interface"
+	depends on PPC_750GX_DUAL_PLL_IF
+	default n
+	help
+	  Include code to provide CPUFreq driver API.
+
+config PPC_750GX_DUAL_PLL_IF_SYSFS
+	bool "Include sysfs interface"
+	depends on PPC_750GX_DUAL_PLL_IF
+	default n
+	help
+	  Include code to provide sysfs interface.
+
 endmenu