i.MX revise code in speed.c

PATCH New Andrew Dyer 1 participant 1 message Aug 26, 2008 Arm i.MX and Layerscape

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Andrew Dyer

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2008-08-26 22:35 UTC #0 lore raw

PATCH 1/1 i.MX revise code in speed.c

This patch is for testing/comment - I have run it on our i.MX system, but don't have an mx1ads, scb9328, or mx1fs2 board to play with.

1) pull common code for PLL calculations out of each function

2) add get_coreclk() to fetch the arm core frequency (we use for printing core clock speed in checkboard() ), not currently used in targets supported in git

3) use the frequencies of the board oscillators and register settings to determine internal clocks rather than a #define

---
 cpu/arm920t/cpu.c         |    2 +-
 cpu/arm920t/imx/speed.c   |   77 +++++++++++++++++++++++++++++++++------------
 include/common.h          |    4 ++
 include/configs/mx1ads.h  |    4 +-
 include/configs/mx1fs2.h  |    7 ++--
 include/configs/scb9328.h |   11 +-----
 6 files changed, 69 insertions(+), 36 deletions(-)

cpu/arm920t/cpu.c +1 -1

index f93bf57..821685f 100644
@@ -38,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #endif
 
 /* read co-processor 15, register #1 (control register) */
-static unsigned long read_p15_c1 (void)
+unsigned long read_p15_c1 (void)
 {
 	unsigned long value;

cpu/arm920t/imx/speed.c +57 ~~-20~~

112 lines not on this page · raw message

include/common.h +4 -0

index de3d595..a2a25d1 100644
@@ -451,6 +451,9 @@ void ft_cpu_setup(void *blob, bd_t *bd);
 void ft_pci_setup(void *blob, bd_t *bd);
 #endif
 #endif
+#ifdef CONFIG_IMX
+unsigned long read_p15_c1(void);
+#endif
 
 
 /* $(CPU)/serial.c */

@@ -512,6 +515,7 @@ ulong get_BCLK(void);
 ulong get_PERCLK1(void);
 ulong get_PERCLK2(void);
 ulong get_PERCLK3(void);
+ulong get_coreclk(void);
 #endif
 ulong	get_bus_freq  (ulong);

include/configs/mx1ads.h +2 -2

index 5125b21..84fc5ae 100644
@@ -185,7 +185,7 @@
 #define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS	1
 
-#define CONFIG_SYS_CLK_FREQ 16780000
-#define CONFIG_SYSPLL_CLK_FREQ 16000000
+#define CONFIG_OSC32_FREQ 32768
+#define CONFIG_OSC16_FREQ 16000000
 
 #endif	/* __CONFIG_H */

include/configs/mx1fs2.h +3 -4

index d527d09..5e8f7f5 100644
@@ -257,6 +257,9 @@
 #define CFG_PCDR_VAL		0x00010005
 #define CFG_GPCR_VAL		0x00000FFB
 
+#define CONFIG_OSC32_FREQ	32768
+#define CONFIG_OSC16_FREQ	16000000
+
 #define USE_16M_OSZI /* If you have one, you want to use it
 			The internal 32kHz oszillator jitters */
 #ifdef USE_16M_OSZI

@@ -264,15 +267,11 @@
 #define CFG_SPCTL0_VAL		0x04001401
 #define CFG_SPCTL1_VAL		0x0C000040
 #define CFG_CSCR_VAL		0x07030003
-#define CONFIG_SYS_CLK_FREQ	16780000
-#define CONFIG_SYSPLL_CLK_FREQ	16000000
 
 #else
 
 #define CFG_SPCTL0_VAL		0x07E716D1
 #define CFG_CSCR_VAL		0x06000003
-#define CONFIG_SYS_CLK_FREQ	16780000
-#define CONFIG_SYSPLL_CLK_FREQ	16780000
 
 #endif

include/configs/scb9328.h +2 -9

index 4ae25ad..206d9e8 100644
@@ -326,15 +326,8 @@
  */
 #define CFG_LOAD_ADDR 0x08400000
 
-#define MHZ16QUARZINUSE
-
-#ifdef MHZ16QUARZINUSE
-#define CONFIG_SYSPLL_CLK_FREQ 16000000
-#else
-#define CONFIG_SYSPLL_CLK_FREQ 16780000
-#endif
-
-#define CONFIG_SYS_CLK_FREQ 16780000
+#define CONFIG_OSC32_FREQ 32000
+#define CONFIG_OSC16_FREQ 16000000
 
 /* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */
 #define CFG_FMCR_VAL 0x00000001

Signature · 1 line

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