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FSL DDR: Remove duplicate setting of cs0_bnds register on 86xx.

PATCH New Kumar Gala 3 participants 29 messages Aug 27, 2008 – Oct 19, 2008

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Kumar Gala

author
#0 lore raw

PATCH 1/24 FSL DDR: Remove duplicate setting of cs0_bnds register on 86xx.

Signed-off-by Kumar Gala <[email protected]>
---
 cpu/mpc86xx/ddr-8641.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)
cpu/mpc86xx/ddr-8641.c +0 -1
index 932ef22..f936182 100644
@@ -35,7 +35,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 		if (i == 0) {
 			out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
-			out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
 			out_be32(&ddr->cs0_config, regs->cs[i].config);
 
 		} else if (i == 1) {
Signature · 1 line
1.5.5.1
author
#1 lore raw

PATCH 2/24 FSL DDR: Add e500 TLB helper for DDR code

Provide a helper function that board code can call to map TLBs when setting up DDR.

Signed-off-by Kumar Gala <[email protected]>
---
 cpu/mpc85xx/tlb.c     |   64 +++++++++++++++++++++++++++++++++++++++++++++++++
 include/asm-ppc/mmu.h |    1 +
 2 files changed, 65 insertions(+), 0 deletions(-)
cpu/mpc85xx/tlb.c +64 -0
index 3d15d50..7ce7a14 100644
@@ -90,3 +90,67 @@ void init_tlbs(void)
 
 	return ;
 }
+
+unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
+{
+	unsigned int tlb_size;
+	unsigned int ram_tlb_index;
+	unsigned int ram_tlb_address;
+
+	/*
+	 * Determine size of each TLB1 entry.
+	 */
+	switch (memsize_in_meg) {
+	case 16:
+	case 32:
+		tlb_size = BOOKE_PAGESZ_16M;
+		break;
+	case 64:
+	case 128:
+		tlb_size = BOOKE_PAGESZ_64M;
+		break;
+	case 256:
+	case 512:
+		tlb_size = BOOKE_PAGESZ_256M;
+		break;
+	case 1024:
+	case 2048:
+		if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx))
+			tlb_size = BOOKE_PAGESZ_1G;
+		else
+			tlb_size = BOOKE_PAGESZ_256M;
+		break;
+	default:
+		puts("DDR: only 16M, 32M, 64M, 128M, 256M, 512M, 1G"
+			" and 2G are supported.\n");
+
+		/*
+		 * The memory was not able to be mapped.
+		 * Default to a small size.
+		 */
+		tlb_size = BOOKE_PAGESZ_64M;
+		memsize_in_meg = 64;
+		break;
+	}
+
+	/*
+	 * Configure DDR TLB1 entries.
+	 * Starting at TLB1 8, use no more than 8 TLB1 entries.
+	 */
+	ram_tlb_index = 8;
+	ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
+	while (ram_tlb_address < (memsize_in_meg * 1024 * 1024)
+	      && ram_tlb_index < 16) {
+		set_tlb(1, ram_tlb_address, ram_tlb_address,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, ram_tlb_index, tlb_size, 1);
+
+		ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
+		ram_tlb_index++;
+	}
+
+	/*
+	 * Confirm that the requested amount of memory was mapped.
+	 */
+	return memsize_in_meg;
+}
include/asm-ppc/mmu.h +1 -0
index 050a7b6..8975e6c 100644
@@ -431,6 +431,7 @@ extern void set_tlb(u8 tlb, u32 epn, u64 rpn,
 extern void disable_tlb(u8 esel);
 extern void invalidate_tlb(u8 tlb);
 extern void init_tlbs(void);
+extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
 
 #define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \
 	{ .tlb = _tlb, .epn = _epn, .rpn = _rpn, .perms = _perms, \
Signature · 1 line
1.5.5.1
author
#2 lore raw

PATCH 3/24 FSL DDR: Add 85xx specific register setting

Signed-off-by Kumar Gala <[email protected]>
---
 cpu/mpc85xx/Makefile   |   19 ++++++++
 cpu/mpc85xx/ddr-gen1.c |  120 ++++++++++++++++++++++++++++++++++++++++++++++++
 cpu/mpc85xx/ddr-gen2.c |   74 +++++++++++++++++++++++++++++
 cpu/mpc85xx/ddr-gen3.c |  105 ++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 318 insertions(+), 0 deletions(-)
 create mode 100644 cpu/mpc85xx/ddr-gen1.c
 create mode 100644 cpu/mpc85xx/ddr-gen2.c
 create mode 100644 cpu/mpc85xx/ddr-gen3.c
cpu/mpc85xx/Makefile +19 -0
index d51a6dd..3a3c6a7 100644
@@ -34,6 +34,25 @@ SOBJS	= $(SOBJS-y)
 COBJS-$(CONFIG_MP) += mp.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
 
+# supports ddr1
+ifeq ($(CONFIG_FSL_DDR1),y)
+COBJS-$(CONFIG_MPC8540) += ddr-gen1.o
+COBJS-$(CONFIG_MPC8560) += ddr-gen1.o
+COBJS-$(CONFIG_MPC8541) += ddr-gen1.o
+COBJS-$(CONFIG_MPC8555) += ddr-gen1.o
+endif
+
+# supports ddr1/2
+ifeq ($(CONFIG_FSL_DDR2),y)
+COBJS-$(CONFIG_MPC8548) += ddr-gen2.o
+COBJS-$(CONFIG_MPC8568) += ddr-gen2.o
+COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
+
+# supports ddr1/2/3
+COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
+COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
+endif
+
 ifneq ($(CONFIG_FSL_DDR3),y)
 ifneq ($(CONFIG_FSL_DDR2),y)
 ifneq ($(CONFIG_FSL_DDR1),y)
cpu/mpc85xx/ddr-gen1.c new file +120 -0

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cpu/mpc85xx/ddr-gen2.c new file +74 -0

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cpu/mpc85xx/ddr-gen3.c new file +105 -0

105 lines not on this page · raw message

Signature · 1 line
1.5.5.1
author
#3 lore raw

PATCH 4/24 FSL DDR: Convert MPC8540ADS to new DDR code.

Signed-off-by Kumar Gala <[email protected]>
---
 board/freescale/mpc8540ads/Makefile     |   13 ++++--
 board/freescale/mpc8540ads/ddr.c        |   70 +++++++++++++++++++++++++++++++
 board/freescale/mpc8540ads/mpc8540ads.c |   14 ++++--
 include/configs/MPC8540ADS.h            |   53 ++++++++++-------------
 4 files changed, 110 insertions(+), 40 deletions(-)
 create mode 100644 board/freescale/mpc8540ads/ddr.c
board/freescale/mpc8540ads/Makefile +8 -5
index 2d71cbc..4c6da4d 100644
@@ -25,11 +25,14 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o law.o tlb.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
 	$(AR) $(ARFLAGS) $@ $(OBJS)
board/freescale/mpc8540ads/ddr.c new file +70 -0

70 lines not on this page · raw message

board/freescale/mpc8540ads/mpc8540ads.c +9 -5
index 4f068cc..005e4d9 100644
@@ -1,4 +1,4 @@
- /*
+/*
  * Copyright 2004 Freescale Semiconductor.
  * (C) Copyright 2002,2003, Motorola Inc.
  * Xianghua Xiao, (X.Xiao at motorola.com)

@@ -28,8 +28,9 @@
 #include <common.h>
 #include <pci.h>
 #include <asm/processor.h>
+#include <asm/mmu.h>
 #include <asm/immap_85xx.h>
-#include <spd_sdram.h>
+#include <asm/fsl_ddr_sdram.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 

@@ -82,10 +83,13 @@ initdram(int board_type)
 	}
 #endif
 
-#if defined(CONFIG_SPD_EEPROM)
-	dram_size = spd_sdram ();
+#ifdef CONFIG_SPD_EEPROM
+	dram_size = fsl_ddr_sdram();
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+
+	dram_size *= 0x100000;
 #else
-	dram_size = fixed_sdram ();
+	dram_size = fixed_sdram();
 #endif
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
include/configs/MPC8540ADS.h +23 -30

69 lines not on this page · raw message

Signature · 1 line
1.5.5.1
author
#4 lore raw

PATCH 5/24 FSL DDR: Convert MPC8560ADS to new DDR code.

From: Jon Loeliger <[email protected]>

Signed-off-by Jon Loeliger <[email protected]>
Signed-off-by Kumar Gala <[email protected]>
---
 board/freescale/mpc8560ads/Makefile     |   13 ++++--
 board/freescale/mpc8560ads/ddr.c        |   70 +++++++++++++++++++++++++++++++
 board/freescale/mpc8560ads/mpc8560ads.c |   11 ++++-
 include/configs/MPC8560ADS.h            |   52 +++++++++++------------
 4 files changed, 110 insertions(+), 36 deletions(-)
 create mode 100644 board/freescale/mpc8560ads/ddr.c
board/freescale/mpc8560ads/Makefile +8 -5
index 2d71cbc..67dbdeb 100644
@@ -25,11 +25,14 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o law.o tlb.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
 	$(AR) $(ARFLAGS) $@ $(OBJS)
board/freescale/mpc8560ads/ddr.c new file +70 -0

70 lines not on this page · raw message

board/freescale/mpc8560ads/mpc8560ads.c +8 -3
index 2c14a88..851fc57 100644
@@ -28,7 +28,9 @@
 #include <common.h>
 #include <pci.h>
 #include <asm/processor.h>
+#include <asm/mmu.h>
 #include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
 #include <ioports.h>
 #include <spd_sdram.h>
 #include <miiphy.h>

@@ -285,10 +287,13 @@ initdram(int board_type)
 	}
 #endif
 
-#if defined(CONFIG_SPD_EEPROM)
-	dram_size = spd_sdram ();
+#ifdef CONFIG_SPD_EEPROM
+	dram_size = fsl_ddr_sdram();
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+
+	dram_size *= 0x100000;
 #else
-	dram_size = fixed_sdram ();
+	dram_size = fixed_sdram();
 #endif
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
include/configs/MPC8560ADS.h +24 -28

76 lines not on this page · raw message

Signature · 1 line
1.5.5.1
author
#5 lore raw

PATCH 6/24 FSL DDR: Convert MPC8555ADS to new DDR code.

From: Jon Loeliger <[email protected]>

Signed-off-by Jon Loeliger <[email protected]>
Signed-off-by Kumar Gala <[email protected]>
---
 board/freescale/mpc8555cds/Makefile     |    1 +
 board/freescale/mpc8555cds/ddr.c        |   79 +++++++++++++++++++++++++++++++
 board/freescale/mpc8555cds/mpc8555cds.c |    8 +++-
 include/configs/MPC8555CDS.h            |   35 +++++++-------
 4 files changed, 105 insertions(+), 18 deletions(-)
 create mode 100644 board/freescale/mpc8555cds/ddr.c
board/freescale/mpc8555cds/Makefile +1 -0
index 98f1530..c19a527 100644
@@ -27,6 +27,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
 COBJS-y	+= law.o
 COBJS-y	+= tlb.o
board/freescale/mpc8555cds/ddr.c new file +79 -0

79 lines not on this page · raw message

board/freescale/mpc8555cds/mpc8555cds.c +7 -1
index 9a65101..826056a 100644
@@ -23,7 +23,9 @@
 #include <common.h>
 #include <pci.h>
 #include <asm/processor.h>
+#include <asm/mmu.h>
 #include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
 #include <ioports.h>
 #include <spd_sdram.h>
 #include <libfdt.h>

@@ -261,7 +263,10 @@ initdram(int board_type)
 		udelay(200);
 	}
 #endif
-	dram_size = spd_sdram();
+
+	dram_size = fsl_ddr_sdram();
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 	/*

@@ -269,6 +274,7 @@ initdram(int board_type)
 	 */
 	ddr_enable_ecc(dram_size);
 #endif
+
 	/*
 	 * SDRAM Initialization
 	 */
include/configs/MPC8555CDS.h +18 -17
index 85c235c..c07a725 100644
@@ -40,13 +40,6 @@
 #define CONFIG_PCI
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_DLL			/* possible DLL fix needed */
-#undef CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
-
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
-#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
-
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
 #define CONFIG_FSL_VIA

@@ -59,8 +52,6 @@
  */
 #define CONFIG_ASSUME_AMD_FLASH
 
-#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */
-
 #ifndef __ASSEMBLY__
 extern unsigned long get_clock_freq(void);
 #endif

@@ -85,24 +76,31 @@ extern unsigned long get_clock_freq(void);
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
-/*
- * DDR Setup
- */
+/* DDR Setup */
+#define CONFIG_FSL_DDR1
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#undef CONFIG_FSL_DDR_INTERACTIVE
+
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 
-#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
-/*
- * Make sure required options are set
- */
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+
+/* Make sure required options are set */
 #ifndef CONFIG_SPD_EEPROM
 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
 #endif
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
-
 /*
  * Local Bus Definitions
  */

@@ -317,6 +315,9 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
+#define CFG_64BIT_VSPRINTF	1
+#define CFG_64BIT_STRTOUL	1
+
 /*
  * I2C
  */
Signature · 1 line
1.5.5.1
author
#6 lore raw

PATCH 7/24 FSL DDR: Convert MPC8541CDS to new DDR code.

From: Jon Loeliger <[email protected]>

Signed-off-by Jon Loeliger <[email protected]>
Signed-off-by Kumar Gala <[email protected]>
---
 board/freescale/mpc8541cds/Makefile     |    1 +
 board/freescale/mpc8541cds/ddr.c        |   79 +++++++++++++++++++++++++++++++
 board/freescale/mpc8541cds/mpc8541cds.c |    6 ++-
 include/configs/MPC8541CDS.h            |   30 +++++++-----
 4 files changed, 102 insertions(+), 14 deletions(-)
 create mode 100644 board/freescale/mpc8541cds/ddr.c
board/freescale/mpc8541cds/Makefile +1 -0
index 98f1530..c19a527 100644
@@ -27,6 +27,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
 COBJS-y	+= law.o
 COBJS-y	+= tlb.o
board/freescale/mpc8541cds/ddr.c new file +79 -0

79 lines not on this page · raw message

board/freescale/mpc8541cds/mpc8541cds.c +5 -1
index 3669ba9..de3a791 100644
@@ -25,7 +25,9 @@
 #include <common.h>
 #include <pci.h>
 #include <asm/processor.h>
+#include <asm/mmu.h>
 #include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
 #include <ioports.h>
 #include <spd_sdram.h>
 #include <libfdt.h>

@@ -263,7 +265,9 @@ initdram(int board_type)
 		udelay(200);
 	}
 #endif
-	dram_size = spd_sdram();
+	dram_size = fsl_ddr_sdram();
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 	/*
include/configs/MPC8541CDS.h +17 -13
index d948d76..29dff32 100644
@@ -40,12 +40,6 @@
 #define CONFIG_PCI
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_DLL			/* possible DLL fix needed */
-#undef CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
-
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
-#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 

@@ -59,8 +53,6 @@
  */
 #define CONFIG_ASSUME_AMD_FLASH
 
-#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */
-
 #ifndef __ASSEMBLY__
 extern unsigned long get_clock_freq(void);
 #endif

@@ -85,13 +77,23 @@ extern unsigned long get_clock_freq(void);
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
-/*
- * DDR Setup
- */
+/* DDR Setup */
+#define CONFIG_FSL_DDR1
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#undef CONFIG_FSL_DDR_INTERACTIVE
+
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 
-#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
 
 /*
  * Make sure required options are set

@@ -102,7 +104,6 @@ extern unsigned long get_clock_freq(void);
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
-
 /*
  * Local Bus Definitions
  */

@@ -317,6 +318,9 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
+#define CFG_64BIT_VSPRINTF	1
+#define CFG_64BIT_STRTOUL	1
+
 /*
  * I2C
  */
Signature · 1 line
1.5.5.1
author
#7 lore raw

PATCH 8/24 FSL DDR: Convert MPC8548CDS to new DDR code.

From: Jon Loeliger <[email protected]>

Signed-off-by Jon Loeliger <[email protected]>
Signed-off-by Kumar Gala <[email protected]>
---
 board/freescale/mpc8548cds/Makefile     |    1 +
 board/freescale/mpc8548cds/ddr.c        |   80 +++++++++++++++++++++++++++++++
 board/freescale/mpc8548cds/mpc8548cds.c |    8 +++-
 include/configs/MPC8548CDS.h            |   37 ++++++++-------
 4 files changed, 108 insertions(+), 18 deletions(-)
 create mode 100644 board/freescale/mpc8548cds/ddr.c
board/freescale/mpc8548cds/Makefile +1 -0
index 98f1530..c19a527 100644
@@ -27,6 +27,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
 COBJS-y	+= law.o
 COBJS-y	+= tlb.o
board/freescale/mpc8548cds/ddr.c new file +80 -0

80 lines not on this page · raw message

board/freescale/mpc8548cds/mpc8548cds.c +7 -1
index 0b037cc..84d3850 100644
@@ -25,8 +25,10 @@
 #include <common.h>
 #include <pci.h>
 #include <asm/processor.h>
+#include <asm/mmu.h>
 #include <asm/immap_85xx.h>
 #include <asm/immap_fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
 #include <spd_sdram.h>
 #include <miiphy.h>
 #include <libfdt.h>

@@ -111,7 +113,10 @@ initdram(int board_type)
 		udelay(200);
 	}
 #endif
-	dram_size = spd_sdram();
+
+	dram_size = fsl_ddr_sdram();
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 	/*

@@ -119,6 +124,7 @@ initdram(int board_type)
 	 */
 	ddr_enable_ecc(dram_size);
 #endif
+
 	/*
 	 * SDRAM Initialization
 	 */
include/configs/MPC8548CDS.h +20 -17
index 33c5c93..ec0b4ff 100644
@@ -46,15 +46,7 @@
 
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_DLL			/* possible DLL fix needed */
-#undef CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
-
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
-
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
 #define CONFIG_FSL_VIA

@@ -67,8 +59,6 @@
  */
 #define CONFIG_ASSUME_AMD_FLASH
 
-#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */
-
 #ifndef __ASSEMBLY__
 extern unsigned long get_clock_freq(void);
 #endif

@@ -103,17 +93,27 @@ extern unsigned long get_clock_freq(void);
 #define CFG_PCI2_ADDR	(CFG_CCSRBAR+0x9000)
 #define CFG_PCIE1_ADDR	(CFG_CCSRBAR+0xa000)
 
-/*
- * DDR Setup
- */
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_DLL			/* possible DLL fix needed */
+
+#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 
-#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
-/*
- * Make sure required options are set
- */
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+
+/* Make sure required options are set */
 #ifndef CONFIG_SPD_EEPROM
 #error ("CONFIG_SPD_EEPROM is required")
 #endif

@@ -342,6 +342,9 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
+#define CFG_64BIT_VSPRINTF	1
+#define CFG_64BIT_STRTOUL	1
+
 /*
  * I2C
  */
Signature · 1 line
1.5.5.1
author
#8 lore raw

PATCH 9/24 FSL DDR: Convert MPC8568MDS to new DDR code.

From: Jon Loeliger <[email protected]>

Signed-off-by Jon Loeliger <[email protected]>
Signed-off-by Kumar Gala <[email protected]>
---
 board/freescale/mpc8568mds/Makefile     |   14 ++++--
 board/freescale/mpc8568mds/ddr.c        |   81 +++++++++++++++++++++++++++++++
 board/freescale/mpc8568mds/mpc8568mds.c |    8 +++-
 include/configs/MPC8568MDS.h            |   38 ++++++++-------
 4 files changed, 117 insertions(+), 24 deletions(-)
 create mode 100644 board/freescale/mpc8568mds/ddr.c
board/freescale/mpc8568mds/Makefile +9 -5
index ecdc4d3..d499fb3 100644
@@ -26,11 +26,15 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o bcsr.o law.o tlb.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= bcsr.o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
 	$(AR) $(ARFLAGS) $@ $(OBJS)
board/freescale/mpc8568mds/ddr.c new file +81 -0

81 lines not on this page · raw message

board/freescale/mpc8568mds/mpc8568mds.c +7 -1
index 2ccff7d..f9e35cc 100644
@@ -25,8 +25,10 @@
 #include <common.h>
 #include <pci.h>
 #include <asm/processor.h>
+#include <asm/mmu.h>
 #include <asm/immap_85xx.h>
 #include <asm/immap_fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
 #include <spd_sdram.h>
 #include <i2c.h>
 #include <ioports.h>

@@ -163,7 +165,10 @@ initdram(int board_type)
 		udelay(200);
 	}
 #endif
-	dram_size = spd_sdram();
+
+	dram_size = fsl_ddr_sdram();
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 	/*

@@ -171,6 +176,7 @@ initdram(int board_type)
 	 */
 	ddr_enable_ecc(dram_size);
 #endif
+
 	/*
 	 * SDRAM Initialization
 	 */
include/configs/MPC8568MDS.h +20 -18
index a82d528..8aeaa29 100644
@@ -41,14 +41,6 @@
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_QE			/* Enable QE */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_DLL			/* possible DLL fix needed */
-/*#define CONFIG_DDR_2T_TIMING		 Sets the 2T timing bit */
-
-/*#define CONFIG_DDR_ECC*/			/* only for ECC DDR module */
-/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/	/* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
-
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
 /*

@@ -58,8 +50,6 @@
  */
 #define CONFIG_ASSUME_AMD_FLASH
 
-#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */
-
 #ifndef __ASSEMBLY__
 extern unsigned long get_clock_freq(void);
 #endif						  /*Replace a call to get_clock_freq (after it is implemented)*/

@@ -95,24 +85,33 @@ extern unsigned long get_clock_freq(void);
 #define CFG_PCI1_ADDR           (CFG_CCSRBAR+0x8000)
 #define CFG_PCIE1_ADDR          (CFG_CCSRBAR+0xa000)
 
-/*
- * DDR Setup
- */
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_DLL			/* possible DLL fix needed */
+#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 
-#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
-/*
- * Make sure required options are set
- */
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+
+/* Make sure required options are set */
 #ifndef CONFIG_SPD_EEPROM
 #error ("CONFIG_SPD_EEPROM is required")
 #endif
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
-
 /*
  * Local Bus Definitions
  */

@@ -302,6 +301,9 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
+#define CFG_64BIT_VSPRINTF	1
+#define CFG_64BIT_STRTOUL	1
+
 /*
  * I2C
  */
Signature · 1 line
1.5.5.1
author
#9 lore raw

PATCH 10/24 FSL DDR: Convert MPC8544DS to new DDR code.

Signed-off-by Kumar Gala <[email protected]>
---
 board/freescale/mpc8544ds/Makefile    |    9 +++-
 board/freescale/mpc8544ds/ddr.c       |   80 +++++++++++++++++++++++++++++++++
 board/freescale/mpc8544ds/mpc8544ds.c |   11 +++--
 include/configs/MPC8544DS.h           |   38 ++++++++-------
 4 files changed, 113 insertions(+), 25 deletions(-)
 create mode 100644 board/freescale/mpc8544ds/ddr.c
board/freescale/mpc8544ds/Makefile +6 -3
index 3a5ea00..3997994 100644
@@ -26,10 +26,13 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o law.o tlb.o
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
board/freescale/mpc8544ds/ddr.c new file +80 -0

80 lines not on this page · raw message

board/freescale/mpc8544ds/mpc8544ds.c +7 -4
index c39ce11..4e976b7 100644
@@ -24,10 +24,11 @@
 #include <command.h>
 #include <pci.h>
 #include <asm/processor.h>
+#include <asm/mmu.h>
 #include <asm/immap_85xx.h>
 #include <asm/immap_fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
 #include <asm/io.h>
-#include <spd_sdram.h>
 #include <miiphy.h>
 #include <libfdt.h>
 #include <fdt_support.h>

@@ -38,8 +39,6 @@
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
-void sdram_init(void);
-
 int checkboard (void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);

@@ -69,7 +68,11 @@ initdram(int board_type)
 
 	puts("Initializing\n");
 
-	dram_size = spd_sdram();
+	dram_size = fsl_ddr_sdram();
+
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+
+	dram_size *= 0x100000;
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 	/*
include/configs/MPC8544DS.h +20 -18
index 9a77b7b..5738192 100644
@@ -46,15 +46,6 @@
 
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
-#undef CONFIG_DDR_DLL
-#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
-
-#define CONFIG_DDR_ECC			/* only for ECC DDR module */
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
-
-#define CONFIG_DDR_ECC_CMD
 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
 
 /*

@@ -64,8 +55,6 @@
  */
 #define CONFIG_ASSUME_AMD_FLASH
 
-#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */
-
 #ifndef __ASSEMBLY__
 extern unsigned long get_board_sys_clk(unsigned long dummy);
 #endif

@@ -101,17 +90,27 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CFG_PCIE2_ADDR		(CFG_CCSRBAR+0x9000)
 #define CFG_PCIE3_ADDR		(CFG_CCSRBAR+0xb000)
 
-/*
- * DDR Setup
- */
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+
+#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CFG_DDR_SDRAM_BASE	0x00000000
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
 
+/* I2C addresses of SPD EEPROMs */
 #define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
 
-/*
- * Make sure required options are set
- */
+/* Make sure required options are set */
 #ifndef CONFIG_SPD_EEPROM
 #error ("CONFIG_SPD_EEPROM is required")
 #endif

@@ -242,6 +241,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_OF_BOARD_SETUP		1
 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
+#define CFG_64BIT_STRTOUL		1
+#define CFG_64BIT_VSPRINTF		1
+
 /* I2C */
 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
Signature · 1 line
1.5.5.1
author
#10 lore raw

PATCH 11/24 FSL DDR: Convert socrates to new DDR code.

Signed-off-by Kumar Gala <[email protected]>
---
 board/socrates/Makefile    |   13 +++++--
 board/socrates/ddr.c       |   80 ++++++++++++++++++++++++++++++++++++++++++++
 board/socrates/sdram.c     |    5 ++-
 include/configs/socrates.h |   29 ++++++++++------
 4 files changed, 111 insertions(+), 16 deletions(-)
 create mode 100644 board/socrates/ddr.c
board/socrates/Makefile +9 -4
index a41fead..6fae601 100644
@@ -28,10 +28,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 #
 
-COBJS	:= $(BOARD).o law.o tlb.o sdram.o nand.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+COBJS-y	+= nand.o
+COBJS-y	+= sdram.o
+COBJS-$(CONFIG_FSL_DDR2) += ddr.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
board/socrates/ddr.c new file +80 -0

80 lines not on this page · raw message

board/socrates/sdram.c +4 -1
index 768fe05..12d1b8a 100644
@@ -25,6 +25,7 @@
 #include <common.h>
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
 #include <asm/processor.h>
 #include <asm/mmu.h>
 #include <spd_sdram.h>

@@ -80,7 +81,9 @@ phys_size_t initdram (int board_type)
 {
 	long dram_size = 0;
 #if defined(CONFIG_SPD_EEPROM)
-	dram_size = spd_sdram ();
+	dram_size = fsl_ddr_sdram();
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 #else
 	dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL);
 #endif
include/configs/socrates.h +18 -11
index 8a64942..15abec1 100644
@@ -93,11 +93,25 @@
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
-/*
- * DDR Setup
- */
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	*/
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+
+#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CFG_DDR_SDRAM_BASE	0x00000000
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
 
 #define CONFIG_DDR_DEFAULT_CL	30		/* CAS latency 3	*/
 

@@ -114,13 +128,6 @@
 #define CFG_DDR_CLK_CONTROL		0x03800000
 #define CFG_SDRAM_SIZE			256 /* in Megs */
 
-#define CONFIG_SPD_EEPROM	1 	/* Use SPD EEPROM for DDR setup*/
-#define SPD_EEPROM_ADDRESS	0x50		/* DDR DIMM */
-#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */
-
-/*
- * Flash on the Local Bus
- */
 /*
  * Flash on the LocalBus
  */
Signature · 1 line
1.5.5.1
author
#11 lore raw

PATCH 12/24 FSL DDR: Convert atum8548 to new DDR code.

Signed-off-by Kumar Gala <[email protected]>
---
 board/atum8548/Makefile    |    9 +++--
 board/atum8548/atum8548.c  |    8 +++-
 board/atum8548/ddr.c       |   80 ++++++++++++++++++++++++++++++++++++++++++++
 include/configs/ATUM8548.h |   64 +++++++++++++++++------------------
 4 files changed, 123 insertions(+), 38 deletions(-)
 create mode 100644 board/atum8548/ddr.c
board/atum8548/Makefile +6 -3
index d2e689f..b991308 100644
@@ -29,10 +29,13 @@ endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o law.o tlb.o
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+COBJS-$(CONFIG_FSL_DDR2) += ddr.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
board/atum8548/atum8548.c +6 -2
index 34f4599..337cf31 100644
@@ -29,7 +29,9 @@
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <asm/immap_fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
 #include <asm/io.h>
+#include <asm/mmu.h>
 #include <spd_sdram.h>
 #include <miiphy.h>
 #include <libfdt.h>

@@ -106,8 +108,10 @@ initdram(int board_type)
 	puts("Initializing\n");
 
 #if defined(CONFIG_SPD_EEPROM)
-	puts("spd_sdram\n");
-	dram_size = spd_sdram ();
+	puts("fsl_ddr_sdram\n");
+	dram_size = fsl_ddr_sdram();
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 #else
 	puts("fixed_sdram\n");
 	dram_size = fixed_sdram ();
board/atum8548/ddr.c new file +80 -0

80 lines not on this page · raw message

include/configs/ATUM8548.h +30 -32

81 lines not on this page · raw message

Signature · 1 line
1.5.5.1
author
#12 lore raw

PATCH 13/24 FSL DDR: Convert sbc8548 to new DDR code.

Signed-off-by Kumar Gala <[email protected]>
---
 board/sbc8548/Makefile    |    9 +++--
 board/sbc8548/ddr.c       |   80 +++++++++++++++++++++++++++++++++++++++++++++
 board/sbc8548/sbc8548.c   |    5 ++-
 include/configs/sbc8548.h |   31 ++++++++++-------
 4 files changed, 108 insertions(+), 17 deletions(-)
 create mode 100644 board/sbc8548/ddr.c
board/sbc8548/Makefile +6 -3
index bb96d95..9919a6e 100644
@@ -28,10 +28,13 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o law.o tlb.o
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+COBJS-$(CONFIG_FSL_DDR2) += ddr.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
board/sbc8548/ddr.c new file +80 -0

80 lines not on this page · raw message

board/sbc8548/sbc8548.c +4 -1
index 91b40e5..f31d7d6 100644
@@ -30,6 +30,7 @@
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <asm/immap_fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
 #include <spd_sdram.h>
 #include <miiphy.h>
 #include <libfdt.h>

@@ -106,7 +107,9 @@ initdram(int board_type)
 #endif
 
 #if defined(CONFIG_SPD_EEPROM)
-	dram_size = spd_sdram ();
+	dram_size = fsl_ddr_sdram();
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 #else
 	dram_size = fixed_sdram ();
 #endif
include/configs/sbc8548.h +18 -13
index b4238e5..9ef0bfd 100644
@@ -47,19 +47,11 @@
 
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#undef CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_DLL			/* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
 
-#undef CONFIG_DDR_ECC			/* only for ECC DDR module */
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
-#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */
-
 #define CONFIG_SYS_CLK_FREQ	66000000 /* SBC8548 default SYSCLK */
 
 /*

@@ -94,13 +86,26 @@
 #define CFG_PCI2_ADDR	(CFG_CCSRBAR+0x9000)
 #define CFG_PCIE1_ADDR	(CFG_CCSRBAR+0xa000)
 
-/*
- * DDR Setup
- */
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#undef CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#undef CONFIG_DDR_SPD
+#undef CONFIG_DDR_ECC			/* only for ECC DDR module */
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CFG_DDR_SDRAM_BASE	0x00000000
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
 
-#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
 
 /*
  * Make sure required options are set
Signature · 1 line
1.5.5.1
author
#13 lore raw

PATCH 14/24 FSL DDR: Convert PM854 to new DDR code.

Signed-off-by Kumar Gala <[email protected]>
---
 board/pm854/Makefile    |    9 ++++--
 board/pm854/ddr.c       |   70 +++++++++++++++++++++++++++++++++++++++++++++++
 board/pm854/pm854.c     |    6 +++-
 include/configs/PM854.h |   58 +++++++++++++++++++--------------------
 4 files changed, 109 insertions(+), 34 deletions(-)
 create mode 100644 board/pm854/ddr.c
board/pm854/Makefile +6 -3
index 2d71cbc..52a756c 100644
@@ -25,10 +25,13 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o law.o tlb.o
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+COBJS-$(CONFIG_FSL_DDR1) += ddr.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
board/pm854/ddr.c new file +70 -0

70 lines not on this page · raw message

board/pm854/pm854.c +5 -1
index 555f6c0..7dbafb9 100644
@@ -28,7 +28,9 @@
 #include <common.h>
 #include <pci.h>
 #include <asm/processor.h>
+#include <asm/mmu.h>
 #include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
 #include <spd_sdram.h>
 
 #if defined(CONFIG_DDR_ECC)

@@ -105,7 +107,9 @@ initdram(int board_type)
 #endif
 
 #if defined(CONFIG_SPD_EEPROM)
-	dram_size = spd_sdram ();
+	dram_size = fsl_ddr_sdram();
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 #else
 	dram_size = fixed_sdram ();
 #endif
include/configs/PM854.h +28 -30

72 lines not on this page · raw message

Signature · 1 line
1.5.5.1
author
#14 lore raw

PATCH 15/24 FSL DDR: Convert PM856 to new DDR code.

Signed-off-by Kumar Gala <[email protected]>
---
 board/pm856/Makefile    |    9 ++++--
 board/pm856/ddr.c       |   70 +++++++++++++++++++++++++++++++++++++++++++++++
 board/pm856/pm856.c     |    6 +++-
 include/configs/PM856.h |   58 +++++++++++++++++++--------------------
 4 files changed, 109 insertions(+), 34 deletions(-)
 create mode 100644 board/pm856/ddr.c
board/pm856/Makefile +6 -3
index 2d71cbc..52a756c 100644
@@ -25,10 +25,13 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o law.o tlb.o
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+COBJS-$(CONFIG_FSL_DDR1) += ddr.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
board/pm856/ddr.c new file +70 -0

70 lines not on this page · raw message

board/pm856/pm856.c +5 -1
index bf325f8..bd4c065 100644
@@ -28,7 +28,9 @@
 #include <common.h>
 #include <pci.h>
 #include <asm/processor.h>
+#include <asm/mmu.h>
 #include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
 #include <ioports.h>
 #include <spd_sdram.h>
 #include <miiphy.h>

@@ -260,7 +262,9 @@ initdram(int board_type)
 #endif
 
 #if defined(CONFIG_SPD_EEPROM)
-	dram_size = spd_sdram ();
+	dram_size = fsl_ddr_sdram();
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 #else
 	dram_size = fixed_sdram ();
 #endif
include/configs/PM856.h +28 -30

72 lines not on this page · raw message

Signature · 1 line
1.5.5.1
author
#15 lore raw

PATCH 16/24 FSL DDR: Convert MPC8540EVAL to new DDR code.

Signed-off-by Kumar Gala <[email protected]>
---
 board/mpc8540eval/Makefile      |   12 ++++--
 board/mpc8540eval/ddr.c         |   70 +++++++++++++++++++++++++++++++++++++++
 board/mpc8540eval/mpc8540eval.c |    6 +++-
 include/configs/MPC8540EVAL.h   |   26 ++++++++++----
 4 files changed, 102 insertions(+), 12 deletions(-)
 create mode 100644 board/mpc8540eval/ddr.c
board/mpc8540eval/Makefile +8 -4
index 325d6d5..5a68f11 100644
@@ -25,10 +25,14 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o flash.o law.o tlb.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+COBJS-y	+= flash.o
+COBJS-$(CONFIG_FSL_DDR1) += ddr.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
board/mpc8540eval/ddr.c new file +70 -0

70 lines not on this page · raw message

board/mpc8540eval/mpc8540eval.c +5 -1
index 1ac333c..7c54458 100644
@@ -25,7 +25,9 @@
 
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/mmu.h>
 #include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
 #include <spd_sdram.h>
 
 long int fixed_sdram (void);

@@ -84,7 +86,9 @@ phys_size_t initdram (int board_type)
 #endif
 
 #if defined(CONFIG_SPD_EEPROM)
-	dram_size = spd_sdram ();
+	dram_size = fsl_ddr_sdram();
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 #else
 	dram_size = fixed_sdram ();
 #endif
include/configs/MPC8540EVAL.h +19 -7
index b13c81c..1073e23 100644
@@ -39,9 +39,6 @@
 #undef  CONFIG_PCI			    /* pci ethernet support	*/
 #define CONFIG_TSEC_ENET		    /* tsec ethernet support  */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM                   /* Use SPD EEPROM for DDR setup */
-#undef  CONFIG_DDR_ECC			    /* only for ECC DDR module */
-#define CONFIG_DDR_DLL                      /* possible DLL fix needed */
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 

@@ -86,8 +83,6 @@
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory  */
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 #define CFG_SDRAM_SIZE		256             /* DDR is now 256MB     */
 
 #if defined(CONFIG_RAM_AS_FLASH)

@@ -121,10 +116,27 @@
 #undef  CFG_RAMBOOT
 #endif
 
-#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+/* DDR Setup */
+#define CONFIG_FSL_DDR1
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_DLL                      /* possible DLL fix needed */
+
+#undef  CONFIG_DDR_ECC			    /* only for ECC DDR module */
+#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CFG_DDR_SDRAM_BASE	0x00000000
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
 
-/* Here some DDR setting should be added */
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
 
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
 
 #undef CONFIG_CLOCKS_IN_MHZ
Signature · 1 line
1.5.5.1
author
#16 lore raw

PATCH 17/24 FSL DDR: Convert SBC8560 to new DDR code.

Signed-off-by Kumar Gala <[email protected]>
---
 board/sbc8560/Makefile    |    9 ++++--
 board/sbc8560/ddr.c       |   70 +++++++++++++++++++++++++++++++++++++++++++++
 board/sbc8560/sbc8560.c   |    6 +++-
 board/sbc8560/u-boot.lds  |    1 -
 include/configs/SBC8540.h |   22 ++++++++++++--
 include/configs/sbc8560.h |   28 ++++++++++++++----
 6 files changed, 122 insertions(+), 14 deletions(-)
 create mode 100644 board/sbc8560/ddr.c
board/sbc8560/Makefile +6 -3
index bb96d95..6399734 100644
@@ -28,10 +28,13 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o law.o tlb.o
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+COBJS-$(CONFIG_FSL_DDR1) += ddr.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
board/sbc8560/ddr.c new file +70 -0

70 lines not on this page · raw message

board/sbc8560/sbc8560.c +5 -1
index d9e598c..dc66170 100644
@@ -29,7 +29,9 @@
 
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/mmu.h>
 #include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
 #include <ioports.h>
 #include <spd_sdram.h>
 #include <miiphy.h>

@@ -283,7 +285,9 @@ phys_size_t initdram (int board_type)
 #endif
 
 #if defined(CONFIG_SPD_EEPROM)
-	dram_size = spd_sdram ();
+	dram_size = fsl_ddr_sdram();
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 #else
 	dram_size = fixed_sdram ();
 #endif
board/sbc8560/u-boot.lds +0 -1
index ba5ce0b..237a3b6 100644
@@ -74,7 +74,6 @@ SECTIONS
     cpu/mpc85xx/cpu_init.o (.text)
     cpu/mpc85xx/cpu.o (.text)
     cpu/mpc85xx/speed.o (.text)
-    cpu/mpc85xx/spd_sdram.o (.text)
     common/dlmalloc.o (.text)
     lib_generic/crc32.o (.text)
     lib_ppc/extable.o (.text)
include/configs/SBC8540.h +19 -3
index 6033d93..93509ee 100644
@@ -103,18 +103,34 @@
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	 */
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 #define CFG_SDRAM_SIZE		512		/* DDR is 512MB */
-#define SPD_EEPROM_ADDRESS	0x55		/*  DDR DIMM */
 
+/* DDR Setup */
+#define CONFIG_FSL_DDR1
+#undef CONFIG_FSL_DDR_INTERACTIVE
 #undef  CONFIG_DDR_ECC				/* only for ECC DDR module	*/
 #undef  CONFIG_SPD_EEPROM			/* Use SPD EEPROM for DDR setup */
+#undef  CONFIG_DDR_SPD
 
 #if defined(CONFIG_MPC85xx_REV1)
   #define CONFIG_DDR_DLL			/* possible DLL fix needed	*/
 #endif
 
+#undef  CONFIG_DDR_ECC			    /* only for ECC DDR module */
+#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CFG_DDR_SDRAM_BASE	0x00000000
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x55	/* CTLR 0 DIMM 0 */
+
 #undef CONFIG_CLOCKS_IN_MHZ
 
 #if defined(CONFIG_RAM_AS_FLASH)
include/configs/sbc8560.h +22 -6
index b244eef..99d328c 100644
@@ -97,18 +97,34 @@
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	 */
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 #define CFG_SDRAM_SIZE		512		/* DDR is 512MB */
-#define SPD_EEPROM_ADDRESS	0x55		/*  DDR DIMM */
 
-#undef  CONFIG_DDR_ECC			/* only for ECC DDR module	*/
-#undef  CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+/* DDR Setup */
+#define CONFIG_FSL_DDR1
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#undef  CONFIG_DDR_ECC				/* only for ECC DDR module	*/
+#undef  CONFIG_SPD_EEPROM			/* Use SPD EEPROM for DDR setup */
+#undef  CONFIG_DDR_SPD
 
 #if defined(CONFIG_MPC85xx_REV1)
-  #define CONFIG_DDR_DLL		/* possible DLL fix needed	*/
+  #define CONFIG_DDR_DLL			/* possible DLL fix needed	*/
 #endif
 
+#undef  CONFIG_DDR_ECC			    /* only for ECC DDR module */
+#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CFG_DDR_SDRAM_BASE	0x00000000
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x55	/* CTLR 0 DIMM 0 */
+
 #undef CONFIG_CLOCKS_IN_MHZ
 
 #if defined(CONFIG_RAM_AS_FLASH)
Signature · 1 line
1.5.5.1
author
#17 lore raw

PATCH 18/24 FSL DDR: Convert STXGP3 to new DDR code.

Signed-off-by Kumar Gala <[email protected]>
---
 board/stxgp3/Makefile    |   12 +++++--
 board/stxgp3/ddr.c       |   70 ++++++++++++++++++++++++++++++++++++++++++++++
 board/stxgp3/stxgp3.c    |    6 +++-
 board/stxgp3/u-boot.lds  |    1 -
 include/configs/stxgp3.h |   30 +++++++++++--------
 5 files changed, 100 insertions(+), 19 deletions(-)
 create mode 100644 board/stxgp3/ddr.c
board/stxgp3/Makefile +8 -4
index 325d6d5..5a68f11 100644
@@ -25,10 +25,14 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o flash.o law.o tlb.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+COBJS-y	+= flash.o
+COBJS-$(CONFIG_FSL_DDR1) += ddr.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
board/stxgp3/ddr.c new file +70 -0

70 lines not on this page · raw message

board/stxgp3/stxgp3.c +5 -1
index 218e805..c80f1b3 100644
@@ -32,7 +32,9 @@
 #include <common.h>
 #include <pci.h>
 #include <asm/processor.h>
+#include <asm/mmu.h>
 #include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
 #include <ioports.h>
 #include <asm/io.h>
 #include <spd_sdram.h>

@@ -292,7 +294,9 @@ initdram (int board_type)
 	}
 #endif
 
-	dram_size = spd_sdram ();
+	dram_size = fsl_ddr_sdram();
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 
 #if defined(CONFIG_DDR_ECC)
 	/* Initialize and enable DDR ECC.
board/stxgp3/u-boot.lds +0 -1
index 9cc4997..d5363be 100644
@@ -76,7 +76,6 @@ SECTIONS
     cpu/mpc85xx/cpu_init.o (.text)
     cpu/mpc85xx/cpu.o (.text)
     cpu/mpc85xx/speed.o (.text)
-    cpu/mpc85xx/spd_sdram.o (.text)
     common/dlmalloc.o (.text)
     lib_generic/crc32.o (.text)
     lib_ppc/extable.o (.text)
include/configs/stxgp3.h +17 -13
index 6e8213d..ea79de7 100644
@@ -47,10 +47,6 @@
 #define CONFIG_TSEC_ENET		/* tsec ethernet support*/
 #undef  CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
-#undef  CONFIG_DDR_ECC			/* only for ECC DDR module */
-#define CONFIG_DDR_DLL                  /* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 

@@ -118,19 +114,27 @@
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
+/* DDR Setup */
+#define CONFIG_FSL_DDR1
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#undef CONFIG_FSL_DDR_INTERACTIVE
 
-/*
- * DDR Setup
- */
+#undef  CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_DDR_DLL                  /* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
 
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory  */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 
-#define SPD_EEPROM_ADDRESS	0x54		/*  DDR DIMM */
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x54	/* CTLR 0 DIMM 0 */
 
 #undef CONFIG_CLOCKS_IN_MHZ
Signature · 1 line
1.5.5.1
author
#18 lore raw

PATCH 19/24 FSL DDR: Convert STXSSA to new DDR code.

Signed-off-by Kumar Gala <[email protected]>
---
 board/stxssa/Makefile    |    9 ++++--
 board/stxssa/ddr.c       |   70 ++++++++++++++++++++++++++++++++++++++++++++++
 board/stxssa/stxssa.c    |    6 +++-
 board/stxssa/u-boot.lds  |    1 -
 include/configs/stxssa.h |   30 +++++++++++--------
 5 files changed, 98 insertions(+), 18 deletions(-)
 create mode 100644 board/stxssa/ddr.c
board/stxssa/Makefile +6 -3
index e29cf95..9ab41ec 100644
@@ -25,10 +25,13 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o law.o tlb.o
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+COBJS-$(CONFIG_FSL_DDR1) += ddr.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
board/stxssa/ddr.c new file +70 -0

70 lines not on this page · raw message

board/stxssa/stxssa.c +5 -1
index 2c4b546..124e123 100644
@@ -32,7 +32,9 @@
 #include <common.h>
 #include <pci.h>
 #include <asm/processor.h>
+#include <asm/mmu.h>
 #include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
 #include <ioports.h>
 #include <asm/io.h>
 #include <spd_sdram.h>

@@ -308,7 +310,9 @@ initdram (int board_type)
 	}
 #endif
 
-	dram_size = spd_sdram ();
+	dram_size = fsl_ddr_sdram();
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 
 #if defined(CONFIG_DDR_ECC)
 	/* Initialize and enable DDR ECC.
board/stxssa/u-boot.lds +0 -1
index b0a9d68..93bedda 100644
@@ -76,7 +76,6 @@ SECTIONS
     cpu/mpc85xx/cpu_init.o (.text)
     cpu/mpc85xx/cpu.o (.text)
     cpu/mpc85xx/speed.o (.text)
-    cpu/mpc85xx/spd_sdram.o (.text)
     common/dlmalloc.o (.text)
     lib_generic/crc32.o (.text)
     lib_ppc/extable.o (.text)
include/configs/stxssa.h +17 -13
index 4f1c156..ac349df 100644
@@ -47,10 +47,6 @@
 #define CONFIG_TSEC_ENET		/* tsec ethernet support*/
 #undef CONFIG_ETHER_ON_FCC		/* cpm FCC ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
-#undef	CONFIG_DDR_ECC			/* only for ECC DDR module */
-#undef CONFIG_DDR_DLL			/* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 

@@ -131,19 +127,27 @@
 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
+/* DDR Setup */
+#define CONFIG_FSL_DDR1
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#undef CONFIG_FSL_DDR_INTERACTIVE
 
-/*
- * DDR Setup
- */
+#undef	CONFIG_DDR_ECC			/* only for ECC DDR module */
+#undef CONFIG_DDR_DLL			/* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
 
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory  */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 
-#define SPD_EEPROM_ADDRESS	0x54		/*  DDR DIMM */
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x54	/* CTLR 0 DIMM 0 */
 
 #undef CONFIG_CLOCKS_IN_MHZ
Signature · 1 line
1.5.5.1
author
#19 lore raw

PATCH 20/24 FSL DDR: Remove old SPD support from cpu/mpc85xx

All 85xx boards have been converted to the new code so we can remove the old SPD DDR setup code.

Signed-off-by Kumar Gala <[email protected]>
---
 cpu/mpc85xx/Makefile      |   12 -
 cpu/mpc85xx/spd_sdram.c   | 1154 ---------------------------------------------
 include/configs/TQM85xx.h |    4 +
 3 files changed, 4 insertions(+), 1166 deletions(-)
 delete mode 100644 cpu/mpc85xx/spd_sdram.c
cpu/mpc85xx/Makefile +0 -12
index 3a3c6a7..80b80ff 100644
@@ -35,15 +35,12 @@ COBJS-$(CONFIG_MP) += mp.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
 
 # supports ddr1
-ifeq ($(CONFIG_FSL_DDR1),y)
 COBJS-$(CONFIG_MPC8540) += ddr-gen1.o
 COBJS-$(CONFIG_MPC8560) += ddr-gen1.o
 COBJS-$(CONFIG_MPC8541) += ddr-gen1.o
 COBJS-$(CONFIG_MPC8555) += ddr-gen1.o
-endif
 
 # supports ddr1/2
-ifeq ($(CONFIG_FSL_DDR2),y)
 COBJS-$(CONFIG_MPC8548) += ddr-gen2.o
 COBJS-$(CONFIG_MPC8568) += ddr-gen2.o
 COBJS-$(CONFIG_MPC8544) += ddr-gen2.o

@@ -51,15 +48,6 @@ COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
 # supports ddr1/2/3
 COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
 COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
-endif
-
-ifneq ($(CONFIG_FSL_DDR3),y)
-ifneq ($(CONFIG_FSL_DDR2),y)
-ifneq ($(CONFIG_FSL_DDR1),y)
-COBJS-y	+= spd_sdram.o
-endif
-endif
-endif
 
 COBJS	= traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \
 	  pci.o serial_scc.o commproc.o ether_fcc.o qe_io.o \
cpu/mpc85xx/spd_sdram.c deleted +0 -1154

1,154 lines not on this page · raw message

include/configs/TQM85xx.h +4 -0
index d84554e..5e1cf95 100644
@@ -137,6 +137,10 @@
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	*/
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
 
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
 #if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
 /* TQM8540 & 8560 need DLL-override */
 #define CONFIG_DDR_DLL				/* DLL fix needed	*/
Signature · 1 line
1.5.5.1
author
#20 lore raw

PATCH 21/24 mpc85xx: Add support for the MPC8572DS reference board

Signed-off-by Kumar Gala <[email protected]>
---
 MAKEALL                               |    1 +
 Makefile                              |    3 +
 board/freescale/mpc8572ds/Makefile    |   54 +++
 board/freescale/mpc8572ds/config.mk   |   32 ++
 board/freescale/mpc8572ds/ddr.c       |   81 +++++
 board/freescale/mpc8572ds/law.c       |   41 +++
 board/freescale/mpc8572ds/mpc8572ds.c |  573 ++++++++++++++++++++++++++++++++
 board/freescale/mpc8572ds/tlb.c       |   85 +++++
 board/freescale/mpc8572ds/u-boot.lds  |  145 +++++++++
 cpu/mpc85xx/cpu.c                     |    2 +-
 cpu/mpc85xx/pci.c                     |    2 +-
 include/configs/MPC8572DS.h           |  576 +++++++++++++++++++++++++++++++++
 12 files changed, 1593 insertions(+), 2 deletions(-)
 create mode 100644 board/freescale/mpc8572ds/Makefile
 create mode 100644 board/freescale/mpc8572ds/config.mk
 create mode 100644 board/freescale/mpc8572ds/ddr.c
 create mode 100644 board/freescale/mpc8572ds/law.c
 create mode 100644 board/freescale/mpc8572ds/mpc8572ds.c
 create mode 100644 board/freescale/mpc8572ds/tlb.c
 create mode 100644 board/freescale/mpc8572ds/u-boot.lds
 create mode 100644 include/configs/MPC8572DS.h
MAKEALL +1 -0
index e807063..fba5d21 100755
@@ -354,6 +354,7 @@ LIST_85xx="		\
 	MPC8555CDS	\
 	MPC8560ADS	\
 	MPC8568MDS	\
+	MPC8572DS	\
 	PM854		\
 	PM856		\
 	sbc8540		\
Makefile +3 -0
index 89fea72..95f4c33 100644
@@ -2265,6 +2265,9 @@ MPC8555CDS_config:	unconfig
 MPC8568MDS_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale
 
+MPC8572DS_config:       unconfig
+	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8572ds freescale
+
 PM854_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854
board/freescale/mpc8572ds/Makefile new file +54 -0

54 lines not on this page · raw message

board/freescale/mpc8572ds/config.mk new file +32 -0
new file mode 100644
index 0000000..5b32186
@@ -0,0 +1,32 @@
+#
+# Copyright 2007-2008 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8572ds board
+#
+ifndef TEXT_BASE
+TEXT_BASE = 0xeff80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8572=1
board/freescale/mpc8572ds/ddr.c new file +81 -0

81 lines not on this page · raw message

board/freescale/mpc8572ds/law.c new file +41 -0

41 lines not on this page · raw message

board/freescale/mpc8572ds/mpc8572ds.c new file +573 -0

573 lines not on this page · raw message

board/freescale/mpc8572ds/tlb.c new file +85 -0

85 lines not on this page · raw message

board/freescale/mpc8572ds/u-boot.lds new file +145 -0

145 lines not on this page · raw message

cpu/mpc85xx/cpu.c +1 -1
index bde8e56..5c2231d 100644
@@ -154,7 +154,7 @@ int checkcpu (void)
 #endif
 	clkdiv = lcrr & 0x0f;
 	if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
-#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544)
+#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || defined(CONFIG_MPC8572)
 		/*
 		 * Yes, the entire PQ38 family use the same
 		 * bit-representation for twice the clock divider values.
cpu/mpc85xx/pci.c +1 -1
index a5060cd..fdc4c83 100644
@@ -29,7 +29,7 @@
 #include <asm/cpm_85xx.h>
 #include <pci.h>
 
-#if defined(CONFIG_PCI)
+#if defined(CONFIG_PCI) && !defined(CONFIG_FSL_PCI_INIT)
 
 static struct pci_controller *pci_hose;
include/configs/MPC8572DS.h new file +576 -0

576 lines not on this page · raw message

Signature · 1 line
1.5.5.1
author
#21 lore raw

PATCH 22/24 mpc85xx: Add support for the MPC8536

The MPC8536 Adds SDHC and SATA controllers to the PQ3 family. We also have SERDES init code for the 8536.

Signed-off-by Kumar Gala <[email protected]>
Signed-off-by Srikanth Srinivasan <[email protected]>
Signed-off-by Dejan Minic <[email protected]>
Signed-off-by Jason Jin <[email protected]>
Signed-off-by Dave Liu <[email protected]>
---
 cpu/mpc85xx/Makefile          |    1 +
 cpu/mpc85xx/cpu.c             |    8 ++-
 cpu/mpc85xx/cpu_init.c        |    7 ++
 cpu/mpc85xx/mpc8536_serdes.c  |  180 +++++++++++++++++++++++++++++++++++++++++
 cpu/mpc85xx/speed.c           |    4 +
 drivers/misc/fsl_law.c        |    2 +-
 include/asm-ppc/global_data.h |    6 +-
 include/asm-ppc/immap_85xx.h  |   11 +++
 include/asm-ppc/processor.h   |    2 +
 include/pci_ids.h             |    2 +
 10 files changed, 218 insertions(+), 5 deletions(-)
 create mode 100644 cpu/mpc85xx/mpc8536_serdes.c
cpu/mpc85xx/Makefile +1 -0
index 80b80ff..627e61b 100644
@@ -49,6 +49,7 @@ COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
 COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
 COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
 
+COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
 COBJS	= traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \
 	  pci.o serial_scc.o commproc.o ether_fcc.o qe_io.o \
 	  $(COBJS-y)
cpu/mpc85xx/cpu.c +7 -1
index 5c2231d..2fe3cea 100644
@@ -36,6 +36,8 @@ DECLARE_GLOBAL_DATA_PTR;
 struct cpu_type cpu_type_list [] = {
 	CPU_TYPE_ENTRY(8533, 8533),
 	CPU_TYPE_ENTRY(8533, 8533_E),
+	CPU_TYPE_ENTRY(8536, 8536),
+	CPU_TYPE_ENTRY(8536, 8536_E),
 	CPU_TYPE_ENTRY(8540, 8540),
 	CPU_TYPE_ENTRY(8541, 8541),
 	CPU_TYPE_ENTRY(8541, 8541_E),

@@ -89,6 +91,9 @@ int checkcpu (void)
 	svr = get_svr();
 	ver = SVR_SOC_VER(svr);
 	major = SVR_MAJ(svr);
+#ifdef CONFIG_MPC8536
+	major &= 0x7; /* the msb of this nibble is a mfg code */
+#endif
 	minor = SVR_MIN(svr);
 
 	puts("CPU:   ");

@@ -154,7 +159,8 @@ int checkcpu (void)
 #endif
 	clkdiv = lcrr & 0x0f;
 	if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
-#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || defined(CONFIG_MPC8572)
+#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \
+    defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536)
 		/*
 		 * Yes, the entire PQ38 family use the same
 		 * bit-representation for twice the clock divider values.
cpu/mpc85xx/cpu_init.c +7 -0
index 4feb751..783c5ba 100644
@@ -37,6 +37,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_MPC8536
+extern void fsl_serdes_init(void);
+#endif
+
 #ifdef CONFIG_QE
 extern qe_iop_conf_t qe_iop_conf_tab[];
 extern void qe_config_iopin(u8 port, u8 pin, int dir,

@@ -240,6 +244,9 @@ void cpu_init_f (void)
 	/* Config QE ioports */
 	config_qe_ioports();
 #endif
+#if defined(CONFIG_MPC8536)
+	fsl_serdes_init();
+#endif
 
 }
cpu/mpc85xx/mpc8536_serdes.c new file +180 -0

180 lines not on this page · raw message

cpu/mpc85xx/speed.c +4 -0
index 699441b..1cda1e3 100644
@@ -110,6 +110,10 @@ int get_clocks (void)
 #endif
 	gd->i2c2_clk = gd->i2c1_clk;
 
+#if defined(CONFIG_MPC8536)
+	gd->sdhc_clk = gd->bus_clk / 2;
+#endif
+
 #if defined(CONFIG_CPM2)
 	gd->vco_out = 2*sys_info.freqSystemBus;
 	gd->cpm_clk = gd->vco_out / 2;
drivers/misc/fsl_law.c +1 -1
index e4e5c31..2e94614 100644
@@ -38,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;
       defined(CONFIG_MPC8568) || \
       defined(CONFIG_MPC8641) || defined(CONFIG_MPC8610)
 #define FSL_HW_NUM_LAWS 10
-#elif defined(CONFIG_MPC8572)
+#elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572)
 #define FSL_HW_NUM_LAWS 12
 #else
 #error FSL_HW_NUM_LAWS not defined for this platform
include/asm-ppc/global_data.h +3 -3
index be2ce24..c09b07d 100644
@@ -70,9 +70,6 @@ typedef	struct	global_data {
 #if defined(CONFIG_MPC8315)
 	u32 tdm_clk;
 #endif
-#if defined(CONFIG_MPC837X)
-	u32 sdhc_clk;
-#endif
 	u32 core_clk;
 	u32 enc_clk;
 	u32 lbiu_clk;

@@ -89,6 +86,9 @@ typedef	struct	global_data {
 	u32  mem_sec_clk;
 #endif /* CONFIG_MPC8360 */
 #endif
+#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8536)
+	u32 sdhc_clk;
+#endif
 #if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
 	u32 i2c1_clk;
 	u32 i2c2_clk;
include/asm-ppc/immap_85xx.h +11 -0
index 113ba48..559d6ea 100644
@@ -1560,6 +1560,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORDEVSR_SGMII2_DIS	0x10000000
 #define MPC85xx_PORDEVSR_SGMII3_DIS	0x08000000
 #define MPC85xx_PORDEVSR_SGMII4_DIS	0x04000000
+#define MPC85xx_PORDEVSR_SRDS2_IO_SEL   0x38000000
 #define MPC85xx_PORDEVSR_IO_SEL		0x00380000
 #define MPC85xx_PORDEVSR_PCI2_ARB	0x00040000
 #define MPC85xx_PORDEVSR_PCI1_ARB	0x00020000

@@ -1653,13 +1654,23 @@ typedef struct ccsr_gur {
 #define CFG_MPC85xx_PCIX_ADDR	(CFG_IMMR + CFG_MPC85xx_PCIX_OFFSET)
 #define CFG_MPC85xx_PCIX2_OFFSET	(0x9000)
 #define CFG_MPC85xx_PCIX2_ADDR	(CFG_IMMR + CFG_MPC85xx_PCIX2_OFFSET)
+#define CFG_MPC85xx_SATA1_OFFSET	(0x18000)
+#define CFG_MPC85xx_SATA1_ADDR	(CFG_IMMR + CFG_MPC85xx_SATA1_OFFSET)
+#define CFG_MPC85xx_SATA2_OFFSET	(0x19000)
+#define CFG_MPC85xx_SATA2_ADDR	(CFG_IMMR + CFG_MPC85xx_SATA2_OFFSET)
 #define CFG_MPC85xx_L2_OFFSET	(0x20000)
 #define CFG_MPC85xx_L2_ADDR	(CFG_IMMR + CFG_MPC85xx_L2_OFFSET)
 #define CFG_MPC85xx_DMA_OFFSET	(0x21000)
 #define CFG_MPC85xx_DMA_ADDR	(CFG_IMMR + CFG_MPC85xx_DMA_OFFSET)
+#define CFG_MPC85xx_ESDHC_OFFSET	(0x2e000)
+#define CFG_MPC85xx_ESDHC_ADDR	(CFG_IMMR + CFG_MPC85xx_ESDHC_OFFSET)
 #define CFG_MPC85xx_PIC_OFFSET	(0x40000)
 #define CFG_MPC85xx_PIC_ADDR	(CFG_IMMR + CFG_MPC85xx_PIC_OFFSET)
 #define CFG_MPC85xx_CPM_OFFSET	(0x80000)
 #define CFG_MPC85xx_CPM_ADDR	(CFG_IMMR + CFG_MPC85xx_CPM_OFFSET)
+#define CFG_MPC85xx_SERDES1_OFFSET	(0xE3000)
+#define CFG_MPC85xx_SERDES1_ADDR	(CFG_IMMR + CFG_MPC85xx_SERDES2_OFFSET)
+#define CFG_MPC85xx_SERDES2_OFFSET	(0xE3100)
+#define CFG_MPC85xx_SERDES2_ADDR	(CFG_IMMR + CFG_MPC85xx_SERDES2_OFFSET)
 
 #endif /*__IMMAP_85xx__*/
include/asm-ppc/processor.h +2 -0
index dce4717..e07e5d3 100644
@@ -926,6 +926,8 @@
 
 #define SVR_8533	0x803400
 #define SVR_8533_E	0x803C00
+#define SVR_8536	0x803700
+#define SVR_8536_E	0x803F00
 #define SVR_8540	0x803000
 #define SVR_8541	0x807200
 #define SVR_8541_E	0x807A00
include/pci_ids.h +2 -0
index 165456b..ae642b1 100644
@@ -2057,6 +2057,8 @@
 #define PCI_DEVICE_ID_MICROGATE_SCA	0x0030
 
 #define PCI_VENDOR_ID_FREESCALE		0x1957
+#define PCI_DEVICE_ID_MPC8536E		0x0050
+#define PCI_DEVICE_ID_MPC8536		0x0051
 #define PCI_DEVICE_ID_MPC8548E		0x0012
 #define PCI_DEVICE_ID_MPC8548		0x0013
 #define PCI_DEVICE_ID_MPC8543E		0x0014
Signature · 1 line
1.5.5.1
author
#22 lore raw

PATCH 23/24 mpc85xx: Add support for the MPC8536DS reference board

Signed-off-by Kumar Gala <[email protected]>
Signed-off-by Srikanth Srinivasan <[email protected]>
Signed-off-by Dejan Minic <[email protected]>
Signed-off-by Jason Jin <[email protected]>
Signed-off-by Dave Liu <[email protected]>
Signed-off-by Kumar Gala <[email protected]>
---
 MAKEALL                               |    1 +
 Makefile                              |    3 +
 board/freescale/mpc8536ds/Makefile    |   54 +++
 board/freescale/mpc8536ds/config.mk   |   32 ++
 board/freescale/mpc8536ds/ddr.c       |   79 ++++
 board/freescale/mpc8536ds/law.c       |   43 +++
 board/freescale/mpc8536ds/mpc8536ds.c |  653 +++++++++++++++++++++++++++++++++
 board/freescale/mpc8536ds/tlb.c       |   71 ++++
 board/freescale/mpc8536ds/u-boot.lds  |  145 ++++++++
 include/configs/MPC8536DS.h           |  594 ++++++++++++++++++++++++++++++
 10 files changed, 1675 insertions(+), 0 deletions(-)
 create mode 100644 board/freescale/mpc8536ds/Makefile
 create mode 100644 board/freescale/mpc8536ds/config.mk
 create mode 100644 board/freescale/mpc8536ds/ddr.c
 create mode 100644 board/freescale/mpc8536ds/law.c
 create mode 100644 board/freescale/mpc8536ds/mpc8536ds.c
 create mode 100644 board/freescale/mpc8536ds/tlb.c
 create mode 100644 board/freescale/mpc8536ds/u-boot.lds
 create mode 100644 include/configs/MPC8536DS.h
MAKEALL +1 -0
index fba5d21..e382947 100755
@@ -346,6 +346,7 @@ LIST_83xx="		\
 
 LIST_85xx="		\
 	ATUM8548	\
+	MPC8536DS	\
 	MPC8540ADS	\
 	MPC8540EVAL	\
 	MPC8541CDS	\
Makefile +3 -0
index 95f4c33..c43e2c3 100644
@@ -2206,6 +2206,9 @@ TQM834x_config:	unconfig
 ATUM8548_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548
 
+MPC8536DS_config:       unconfig
+	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8536ds freescale
+
 MPC8540ADS_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads freescale
board/freescale/mpc8536ds/Makefile new file +54 -0

54 lines not on this page · raw message

board/freescale/mpc8536ds/config.mk new file +32 -0
new file mode 100644
index 0000000..9775ff4
@@ -0,0 +1,32 @@
+#
+# Copyright 2008 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8536ds board
+#
+ifndef TEXT_BASE
+TEXT_BASE = 0xeff80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8536=1
board/freescale/mpc8536ds/ddr.c new file +79 -0

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board/freescale/mpc8536ds/law.c new file +43 -0

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board/freescale/mpc8536ds/mpc8536ds.c new file +653 -0

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board/freescale/mpc8536ds/tlb.c new file +71 -0

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board/freescale/mpc8536ds/u-boot.lds new file +145 -0

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include/configs/MPC8536DS.h new file +594 -0

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Signature · 1 line
1.5.5.1
author
#23 lore raw

PATCH 24/24 mpc85xx: remove redudant code with lib_ppc/interrupts.c

For some reason we duplicated the majority of code in lib_ppc/interrupts.c not show how that happened, but there is no good reason for it.

Use the interrupt_init_cpu() and timer_interrupt_cpu() since its why they exist.

Signed-off-by Kumar Gala <[email protected]>
---
 cpu/mpc85xx/interrupts.c |  109 +++++-----------------------------------------
 1 files changed, 12 insertions(+), 97 deletions(-)
cpu/mpc85xx/interrupts.c +12 -97
index 4fe1fac..06d4d8b 100644
@@ -31,64 +31,20 @@
 #include <watchdog.h>
 #include <command.h>
 #include <asm/processor.h>
-#include <ppc_asm.tmpl>
 
-unsigned decrementer_count;		/* count value for 1e6/HZ microseconds */
-
-static __inline__ unsigned long get_msr(void)
-{
-	unsigned long msr;
-
-	asm volatile("mfmsr %0" : "=r" (msr) :);
-	return msr;
-}
-
-static __inline__ void set_msr(unsigned long msr)
-{
-	asm volatile("mtmsr %0" : : "r" (msr));
-	asm volatile("isync");
-}
-
-static __inline__ unsigned long get_dec (void)
-{
-	unsigned long val;
-
-	asm volatile ("mfdec %0":"=r" (val):);
-
-	return val;
-}
-
-
-static __inline__ void set_dec (unsigned long val)
-{
-	if (val)
-		asm volatile ("mtdec %0"::"r" (val));
-}
-
-void enable_interrupts (void)
-{
-	set_msr (get_msr() | MSR_EE);
-}
-
-/* returns flag if MSR_EE was set before */
-int disable_interrupts (void)
-{
-	ulong msr = get_msr();
-	set_msr (msr & ~MSR_EE);
-	return ((msr & MSR_EE) != 0);
-}
-
-int interrupt_init (void)
+int interrupt_init_cpu(unsigned long *decrementer_count)
 {
 	volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR);
 
 	pic->gcr = MPC85xx_PICGCR_RST;
-	while (pic->gcr & MPC85xx_PICGCR_RST);
+	while (pic->gcr & MPC85xx_PICGCR_RST)
+		;
 	pic->gcr = MPC85xx_PICGCR_M;
-	decrementer_count = get_tbclk() / CFG_HZ;
+
+	*decrementer_count = get_tbclk() / CFG_HZ;
+
+	/* PIE is same as DIE, dec interrupt enable */
 	mtspr(SPRN_TCR, TCR_PIE);
-	set_dec (decrementer_count);
-	set_msr (get_msr () | MSR_EE);
 
 #ifdef CONFIG_INTERRUPTS
 	pic->iivpr1 = 0x810001;	/* 50220 enable ecm interrupts */

@@ -123,9 +79,7 @@ int interrupt_init (void)
 	return (0);
 }
 
-/*
- * Install and free a interrupt handler. Not implemented yet.
- */
+/* Install and free a interrupt handler. Not implemented yet. */
 
 void
 irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)

@@ -139,55 +93,16 @@ irq_free_handler(int vec)
 	return;
 }
 
-/****************************************************************************/
-
-
-volatile ulong timestamp = 0;
-
-/*
- * timer_interrupt - gets called when the decrementer overflows,
- * with interrupts disabled.
- * Trivial implementation - no need to be really accurate.
- */
-void timer_interrupt(struct pt_regs *regs)
+void timer_interrupt_cpu(struct pt_regs *regs)
 {
-	timestamp++;
-	set_dec (decrementer_count);
+	/* PIS is same as DIS, dec interrupt status */
 	mtspr(SPRN_TSR, TSR_PIS);
-#if defined(CONFIG_WATCHDOG)
-	if ((timestamp % 1000) == 0)
-		reset_85xx_watchdog();
-#endif /* CONFIG_WATCHDOG */
-}
-
-void reset_timer (void)
-{
-	timestamp = 0;
-}
-
-ulong get_timer (ulong base)
-{
-	return (timestamp - base);
-}
-
-void set_timer (ulong t)
-{
-	timestamp = t;
 }
 
 #if defined(CONFIG_CMD_IRQ)
-
-/*******************************************************************************
- *
- * irqinfo - print information about PCI devices,not implemented.
- *
- */
-int
-do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+/* irqinfo - print information about PCI devices,not implemented. */
+int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-	printf ("\nInterrupt-unsupported:\n");
-
 	return 0;
 }
-
 #endif
Signature · 1 line
1.5.5.1
#24 lore raw

PATCH 19/24 FSL DDR: Convert STXSSA to new DDR code.

In reply to Kumar Gala

Dear Kumar,

Quoted 9 lines · In message <[email protected]> you…
Signed-off-by Kumar Gala <[email protected]>
---
 board/stxssa/Makefile    |    9 ++++--
 board/stxssa/ddr.c       |   70 ++++++++++++++++++++++++++++++++++++++++++++++
 board/stxssa/stxssa.c    |    6 +++-
 board/stxssa/u-boot.lds  |    1 -
 include/configs/stxssa.h |   30 +++++++++++--------
 5 files changed, 98 insertions(+), 18 deletions(-)
 create mode 100644 board/stxssa/ddr.c

How much of flexibility can be expected from the new DDR code? When you submitted this patch, I verified that it works in the standard configuration (with a 256 MB RAM module). Should it also work with other configurations, say, with a 512 MB or a 1 GB module?

If I try it out, booting hangs here:

	U-Boot 2008.10-rc3-00009-gf7a35a6 (Oct 18 2008 - 18:21:52)

	CPU:   8541E, Version: 1.1, (0x807a0011)
	Core:  E500, Version: 2.0, (0x80200020)
	Clock Configuration:
	       CPU: 660 MHz, CCB: 264 MHz,
	       DDR: 132 MHz (264 MT/s data rate), LBC:  66 MHz
	CPM:   264 Mhz
	L1:    D-cache 32 kB enabled
	       I-cache 32 kB enabled
	Board: Silicon Tx GPPP SSA Board
	I2C:   ready
	DRAM:  512 MB

or:

	U-Boot 2008.10-rc3-00009-gf7a35a6 (Oct 18 2008 - 18:21:52)

	CPU:   8541E, Version: 1.1, (0x807a0011)
	Core:  E500, Version: 2.0, (0x80200020)
	Clock Configuration:
	       CPU: 660 MHz, CCB: 264 MHz,
	       DDR: 132 MHz (264 MT/s data rate), LBC:  66 MHz
	CPM:   264 Mhz
	L1:    D-cache 32 kB enabled
	       I-cache 32 kB enabled
	Board: Silicon Tx GPPP SSA Board
	I2C:   ready
	DRAM:   1 GB

I.e., the size gets detected correctly, but then it hangs.

I know that the old code did not support other memory configurations; should these work now with the new DDR code?

Best regards,

Wolfgang Denk

Signature · 9 lines
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Everyone who comes in here wants three things:
        1. They want it quick.
        2. They want it good.
        3. They want it cheap.
I tell 'em to pick two and call me back.
- sign on the back wall of a small printing company in Delaware
author
#25 lore raw

PATCH 19/24 FSL DDR: Convert STXSSA to new DDR code.

Quoted 15 lines · Wolfgang Denk

Dear Kumar,

In message <[email protected]

Quoted 11 lines

you wrote:

Signed-off-by Kumar Gala <[email protected]>

---
board/stxssa/Makefile | 9 ++++--
board/stxssa/ddr.c | 70 ++++++++++++++++++++++++++++++++++++
++++++++++

board/stxssa/stxssa.c    |    6 +++-
board/stxssa/u-boot.lds  |    1 -
include/configs/stxssa.h |   30 +++++++++++--------
5 files changed, 98 insertions(+), 18 deletions(-)

create mode 100644 board/stxssa/ddr.c

Quoted 4 lines

How much of flexibility can be expected from the new DDR code? When you submitted this patch, I verified that it works in the standard configuration (with a 256 MB RAM module). Should it also work with other configurations, say, with a 512 MB or a 1 GB module?

It might, however I'm guessing you still need board tweaks for the timings associated with the different modules you are trying to use.

- k

Applied
#26 lore raw

PATCH 1/24 FSL DDR: Remove duplicate setting of cs0_bnds register on 86xx.

In reply to Kumar Gala

Dear Kumar Gala,

Quoted 4 lines · In message <[email protected]> you…
Signed-off-by Kumar Gala <[email protected]>
---
 cpu/mpc86xx/ddr-8641.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

Applied.

Jon, I hope it is OK that I pulled this in directly.

Best regards,

Wolfgang Denk

Signature · 5 lines
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
I'm a soldier, not a diplomat.  I can only tell the truth.
	-- Kirk, "Errand of Mercy", stardate 3198.9
#27 lore raw

PATCH 1/24 FSL DDR: Remove duplicate setting of cs0_bnds register on 86xx.

Quoted 11 lines · Wolfgang Denk

Dear Kumar Gala,

Quoted 4 lines · In message <[email protected]> you…
Signed-off-by Kumar Gala <[email protected]>
---
 cpu/mpc86xx/ddr-8641.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

Applied.

Jon, I hope it is OK that I pulled this in directly.

Absolutely! No problem at all.

And, Thank you!

jdl

author
#28 lore raw

PATCH 1/24 FSL DDR: Remove duplicate setting of cs0_bnds register on 86xx.

In reply to Wolfgang Denk
Quoted 9 lines · Wolfgang Denk

Dear Kumar Gala,

In message <1219817457-7432-1-git-send-email-

Quoted 4 lines · galak at kernel.crashing.org> you wrote:
Signed-off-by Kumar Gala <[email protected]>

---
cpu/mpc86xx/ddr-8641.c | 1 -

1 files changed, 0 insertions(+), 1 deletions(-)
Quoted 7 lines

Applied.

Jon, I hope it is OK that I pulled this in directly.

Best regards,

Wolfgang Denk

Thanks for grabbing this one, andy should have gotten all the others.

- k