New i386 board (includes code relocation)

new file mode 100644
index 0000000..a3e4677
@@ -0,0 +1,149 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Grandegger, DENX Software Engineering, wg at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <command.h>
+#include <linux/ctype.h>
+#include <asm/ic/sc520.h>
+#include <asm/ic/ssi.h>
+#include <watchdog.h>
+#include <asm/io.h>
+
+#include "fpga.h"
+
+static u8 fpga_init(void);
+static u8 fpga_write(void *buf, size_t bsize);
+static u8 fpga_finalise(void);
+static void fpga_close(void);
+
+
+int fpga_load(int devnum, void *buf, size_t bsize )
+{
+	u8 ret = FPGA_SUCCESS;
+
+	WATCHDOG_RESET();
+
+	ret = fpga_init();
+
+	if (ret == FPGA_SUCCESS) {
+		ret = fpga_write(buf, bsize);
+	}
+
+	if (ret == FPGA_SUCCESS) {
+		ret = fpga_finalise();
+	}
+
+        fpga_close();
+
+	WATCHDOG_RESET();
+
+	return ret;
+}
+
+
+static u8 fpga_init(void)
+{
+	u8 ret = FPGA_FAIL_INIT;
+	u16 state = 0x0000;
+
+	/*
+	 * Drop then raise the FPGA's program bit
+	 */
+	writew(CFG_FPGA_PROGRAM_PIO_BIT, CFG_FPGA_PIO_CLR);
+	udelay(CFG_FPGA_PROGRAM_BIT_DROP_TIME * 1000);
+	writew(CFG_FPGA_PROGRAM_PIO_BIT, CFG_FPGA_PIO_SET);
+
+	reset_timer();
+
+	while (get_timer(0) < CFG_FPGA_MAX_INIT_TIME) {
+		/*
+		 * Check if the FPGA has raised its initialized bit
+		 */
+		state = readw(CFG_FPGA_PIO_DATA);
+
+		if (state & CFG_FPGA_INIT_PIO_BIT) {
+			ret = FPGA_SUCCESS;
+			goto Done;
+		}
+
+		udelay (10);
+	}
+
+Done:
+	return ret;
+}
+
+
+static u8 fpga_write(void *buf, size_t bsize)
+{
+	u8 *ptr = (u8 *) buf;
+
+	/*
+	 * Stream the buffer to the FPGA using the SSI
+	 */
+	ssi_set_interface(CFG_FPGA_SSI_DATA_RATE, 0, 0, 0);
+
+	/*
+	 * TODO: Can ssi_tx_byte() fail (port busy)?
+	 */
+	while (bsize--)
+		ssi_tx_byte (*ptr);
+
+	return FPGA_SUCCESS;
+}
+
+
+static u8 fpga_finalise(void)
+{
+	u8 ret = FPGA_FAIL_FINALISE;
+	u16 state = 0x0000;
+
+	reset_timer();
+
+	while (get_timer(0) < CFG_FPGA_MAX_FINALISE_TIME) {
+		state = readw(CFG_FPGA_PIO_DATA);
+
+		if (state & CFG_FPGA_DONE_PIO_BIT) {
+			ret = FPGA_SUCCESS;
+			goto Done;
+		}
+
+		udelay (10);
+	}
+
+Done:
+	return ret;
+}
+
+static void fpga_close(void)
+{
+	u16 dirs = readw(CFG_FPGA_PIO_DIRECTION);
+
+	/*
+	 * Set the program pin of the FPGA to be an input (high impedance)
+	 */
+	dirs &= ~CFG_FPGA_PROGRAM_PIO_BIT;
+
+	writew(dirs, CFG_FPGA_PIO_DIRECTION);
+}

new file mode 100644
index 0000000..a4db321
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ at gmail.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef _FPGA_H_
+#define _FPGA_H_
+
+#define FPGA_SUCCESS		0
+#define FPGA_FAIL_INIT		1
+#define FPGA_FAIL_FINALISE	2
+#define FPGA_FAIL_START		3
+
+
+
+int fpga_load( int devnum, void *buf, size_t bsize );
+
+#endif /* _FPGA_H_ */

new file mode 100644
index 0000000..eab612c
@@ -0,0 +1,13 @@
+/*
+ * hardware.h
+ *
+ *  Created on: 17/09/2008
+ *      Author: graeme
+ */
+
+#ifndef HARDWARE_H_
+#define HARDWARE_H_
+
+#include "hardware_defs.h"
+
+#endif /* HARDWARE_H_ */

new file mode 100644
index 0000000..2ffa008
@@ -0,0 +1,19 @@
+/*
+ * hardware.h
+ *
+ *  Created on: 11/09/2008
+ *      Author: graeme
+ */
+
+#ifndef HARDWARE_DEFS_H_
+#define HARDWARE_DEFS_H_
+
+#define LED_LATCH_ADDRESS	0x1002
+#define LED_RUN_BITMASK		0x01
+#define LED_1_BITMASK		0x02
+#define LED_2_BITMASK		0x04
+#define LED_RX_BITMASK		0x08
+#define LED_TX_BITMASK		0x10
+#define LED_ERR_BITMASK		0x20
+
+#endif /* HARDWARE_H_ */

index 640b255..a5724b6 100644
@@ -32,7 +32,7 @@
 #include <config.h>
 #include <pci.h>
 #ifdef CONFIG_SC520_SSI
-#include <ssi.h>
+#include <asm/ic/ssi.h>
 #endif
 #include <asm/io.h>
 #include <asm/pci.h>

index d99af26..047d3aa 100644
@@ -19,7 +19,7 @@
  */
 
 #define _PPC_STRING_H_		/* avoid unnecessary str/mem functions */
-#define _LINUX_STRING_H_	/* avoid unnecessary str/mem functions */
+/* #define _LINUX_STRING_H_ */	/* avoid unnecessary str/mem functions */
 
 #include <common.h>
 #include <exports.h>

index 0f7e7a5..2da01ea 100644
@@ -312,7 +312,10 @@ extern int sc520_pci_ints[];
 
 void init_sc520(void);
 unsigned long init_sc520_dram(void);
+
+#ifdef CONFIG_PCI
 void pci_sc520_init(struct pci_controller *hose);
 int pci_sc520_set_irq(int pci_pin, int irq);
+#endif
 
 #endif

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