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MIPS: call XREFILL handler when required

PATCH In review Hervé Poussineau 2 participants 3 messages Oct 6, 2008 – Oct 14, 2008

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Hervé Poussineau

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#0 lore raw

PATCH 1/1 MIPS: call XREFILL handler when required

Hi,

In TLB Load and TLB Store exceptions, we should look at the Status register to know in which mode we are. Existing code checks upper bits of the address, which is totally wrong.

Hervé

helper.c +4 -4
Index: target-mips/helper.c
===================================================================
@@ -448,12 +448,12 @@
             cause = 2;
             if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
 #if defined(TARGET_MIPS64)
-                int R = env->CP0_BadVAddr >> 62;
+                int ksu = (env->CP0_Status >> CP0St_KSU) & 3;
                 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
                 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
                 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 
-                if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
+                if ((ksu == 0 && KX) || (ksu == 1 && SX) || (ksu == 3 && UX))
                     offset = 0x080;
                 else
 #endif

@@ -464,12 +464,12 @@
             cause = 3;
             if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
 #if defined(TARGET_MIPS64)
-                int R = env->CP0_BadVAddr >> 62;
+                int ksu = (env->CP0_Status >> CP0St_KSU) & 3;
                 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
                 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
                 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 
-                if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
+                if ((ksu == 0 && KX) || (ksu == 1 && SX) || (ksu == 3 && UX))
                     offset = 0x080;
                 else
 #endif
#1 lore raw
Quoted 6 lines · Hervé Poussineau

Hi,

In TLB Load and TLB Store exceptions, we should look at the Status register to know in which mode we are.
Existing code checks upper bits of the address, which is totally wrong.

This breaks the boot of a 64-bit linux kernel.

Signature · 4 lines
  .''`.  Aurelien Jarno	            | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
 `. `'   [email protected]         | [email protected]
   `-    people.debian.org/~aurel32 | www.aurel32.net
#2 lore raw
In reply to Hervé Poussineau
Quoted 6 lines · Hervé Poussineau

Hi,

In TLB Load and TLB Store exceptions, we should look at the Status register to know in which mode we are.
Existing code checks upper bits of the address, which is totally wrong.

You are wrong. The current code is correct.

If you look at the "MIPS64 Privileged Resource Architecture document", table "4.5 Access Control as a Function of Address and Operating Mode" (page 17 in my edition), you will see that the refill vector actually depends on the address and not on the current mode.

That's why your patch doesn't allow a 64-bit linux kernel to boot.

Signature · 4 lines
  .''`.  Aurelien Jarno	            | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
 `. `'   [email protected]         | [email protected]
   `-    people.debian.org/~aurel32 | www.aurel32.net