MPC8641 memory map changes/cleanup/36-bit

PATCH New Becky Bruce 4 participants 31 messages Nov 5, 2008 – Nov 10, 2008 Kbuild

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Becky Bruce

author

2008-11-05 20:55 UTC #0 lore raw

cover MPC8641 memory map changes/cleanup/36-bit

 board/freescale/mpc8641hpcn/config.mk |    2 +-
 board/freescale/mpc8641hpcn/law.c     |   30 ++--
 cpu/mpc86xx/cpu_init.c                |    4 +
 cpu/mpc86xx/start.S                   |   90 +++++++-----
 include/configs/MPC8610HPCD.h         |    9 +
 include/configs/MPC8641HPCN.h         |  260 ++++++++++++++++++++++-----------
 include/configs/sbc8641d.h            |    9 +
 7 files changed, 267 insertions(+), 137 deletions(-)

This is the remainer of the patches required to get 36-bit physical addressing working on 8641HPCN.

This patch series consists of:
- Various cleanup patches for 8641
- Getting rid of the nonexistent second flash bank
- A new 32-bit memory map to make the layout more like 85xx
- A new 36-bit memory map and the ability to enable CONFIG_PHYS_64BIT to turn on locating devices in high physical address space.

Note: With these changes, an updated device tree is required to boot Linux; I will be pushing that to Linux shortly.

Cheers,
Becky

Becky Bruce

author

2008-11-05 20:55 UTC #1 lore raw

PATCH 1/9 mpc8641: Remove extra "0" from BR2 define

Signed-off-by Becky Bruce <[email protected]>

---
 include/configs/MPC8641HPCN.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

include/configs/MPC8641HPCN.h +1 -1

index 1401e15..779e9a8 100644
@@ -186,7 +186,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_OR1_PRELIM		0xff006ff7	/* 16MB Alternate Boot Flash area*/
 
 #define CONFIG_SYS_BR2_PRELIM		(BR_PHYS_ADDR(CF_BASE)		\
-					 | 0x000001001)	/* port size 16bit */
+					 | 0x00001001)	/* port size 16bit */
 #define CONFIG_SYS_OR2_PRELIM		0xfff06ff7	/* 1MB Compact Flash area*/
 
 #define CONFIG_SYS_BR3_PRELIM		(BR_PHYS_ADDR(PIXIS_BASE)	\

Signature · 1 line

1.5.5.1

Becky Bruce

author

2008-11-05 20:55 UTC #2 lore raw

PATCH 2/9 mpc86xx: Move setup_bats into cpu_init_f

In order to later allow for a physical relocation of the flash, setup_bats, which sets up the final BAT mapping for the board, needs to happen *after* init_laws(). Otherwise, there will be no window programmed for the flash at the new physical location at the point when we change the mmu translation.

Signed-off-by Becky Bruce <[email protected]>

---
 cpu/mpc86xx/cpu_init.c |    4 ++++
 cpu/mpc86xx/start.S    |    5 -----
 2 files changed, 4 insertions(+), 5 deletions(-)

cpu/mpc86xx/cpu_init.c +4 -0

index 06f179c..a7e6036 100644
@@ -33,6 +33,8 @@
 #include <asm/fsl_law.h>
 #include "mp.h"
 
+void setup_bats(void);
+
 DECLARE_GLOBAL_DATA_PTR;
 
 /*

@@ -57,6 +59,8 @@ void cpu_init_f(void)
 	init_laws();
 #endif
 
+	setup_bats();
+
 	/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
 	 * addresses - these have to be modified later when FLASH size
 	 * has been determined

cpu/mpc86xx/start.S +0 -5

index 48f8c5a..0d30e91 100644
@@ -272,11 +272,6 @@ in_flash:
 
 	GET_GOT			/* initialize GOT access	*/
 
-	/* setup the rest of the bats */
-	bl      setup_bats
-	sync
-
-
 	/* run low-level CPU init code	   (from Flash) */
 	bl	cpu_init_f
 	sync

Signature · 1 line

1.5.5.1

Becky Bruce

author

2008-11-05 20:55 UTC #3 lore raw

PATCH 3/9 mpc8641: only define CONFIG_ENV_SIZE once

It's currently defined twice inside in an if/else block, but both halves set the same value. Move the define outside the if.

Signed-off-by Becky Bruce <[email protected]>

---
 include/configs/MPC8641HPCN.h |    3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

include/configs/MPC8641HPCN.h +1 -2

index 779e9a8..8c85881 100644
@@ -522,12 +522,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
     #define CONFIG_ENV_IS_IN_FLASH	1
     #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x60000)
     #define CONFIG_ENV_SECT_SIZE		0x10000	/* 64K(one sector) for env */
-    #define CONFIG_ENV_SIZE		0x2000
 #else
     #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
     #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
-    #define CONFIG_ENV_SIZE		0x2000
 #endif
+#define CONFIG_ENV_SIZE		0x2000
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

Signature · 1 line

1.5.5.1

Becky Bruce

author

2008-11-05 20:55 UTC #4 lore raw

PATCH 4/9 mpc8641: Drop imaginary second flash bank, map 8MB

There's a lot of setup and foo for the second flash bank. The problem is, this board doesn't actually have one. Clean this up. Also, the flash is 8M in size. Get rid of the confusing aliased overmapping, and just map 8M.

Signed-off-by Becky Bruce <[email protected]>

---
 board/freescale/mpc8641hpcn/law.c |    2 +-
 include/configs/MPC8641HPCN.h     |   41 ++++++++++++------------------------
 2 files changed, 15 insertions(+), 28 deletions(-)

board/freescale/mpc8641hpcn/law.c +1 -1

index 1ad186c..8ec5238 100644
@@ -58,7 +58,7 @@ struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 #endif
 	SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
-	SET_LAW((CONFIG_SYS_FLASH_BASE & 0xfe000000), LAW_SIZE_32M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

include/configs/MPC8641HPCN.h +14 ~~-27~~

65 lines not on this page · raw message

Signature · 1 line

1.5.5.1

Becky Bruce

author

2008-11-05 20:55 UTC #5 lore raw

PATCH 5/9 mpc8641: make DIAG_ADDR == FLASH_BASE

Currently, that's what it is, but it's hardcoded.

Signed-off-by Becky Bruce <[email protected]>

---
 include/configs/MPC8641HPCN.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

include/configs/MPC8641HPCN.h +1 -1

index d77f0fc..0a6d5f9 100644
@@ -40,7 +40,7 @@
 #define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
 
 #ifdef RUN_DIAG
-#define CONFIG_SYS_DIAG_ADDR	     0xff800000
+#define CONFIG_SYS_DIAG_ADDR	     CONFIG_SYS_FLASH_BASE
 #endif
 
 #define CONFIG_SYS_RESET_ADDRESS    0xfff00100

Signature · 1 line

1.5.5.1

Becky Bruce

author

2008-11-05 20:55 UTC #6 lore raw

PATCH 6/9 mpc86xx: Use SRR0/1/rfi to enable address translation, not blr

Using a mtmsr/blr means that you have to be executing at the same virtual address once you enable translation. This is unnecessarily restrictive, and is not really how this is usually done. Change it to use the more common mtspr SRR0/SRR1 and rfi method.

Signed-off-by Becky Bruce <[email protected]>

---
 cpu/mpc86xx/start.S |   19 ++++++++-----------
 1 files changed, 8 insertions(+), 11 deletions(-)

cpu/mpc86xx/start.S +8 ~~-11~~

index 0d30e91..7e36801 100644
@@ -244,9 +244,15 @@ in_flash:
 	 */
 
 	/* enable address translation */
-	bl	enable_addr_trans
-	sync
+	mfmsr	r5
+	ori	r5, r5, (MSR_IR | MSR_DR)
+	lis	r3,addr_trans_enabled at h
+	ori	r3, r3, addr_trans_enabled at l
+	mtspr	SPRN_SRR0,r3
+	mtspr	SPRN_SRR1,r5
+	rfi
 
+addr_trans_enabled:
 	/* enable and invalidate the data cache */
 /*	bl	l1dcache_enable */
 	bl	dcache_enable

@@ -423,15 +429,6 @@ tlblp:
 	blt tlblp
 	blr
 
-	.globl enable_addr_trans
-enable_addr_trans:
-	/* enable address translation */
-	mfmsr	r5
-	ori	r5, r5, (MSR_IR | MSR_DR)
-	mtmsr	r5
-	isync
-	blr
-
 	.globl disable_addr_trans
 disable_addr_trans:
 	/* disable address translation */

Signature · 1 line

1.5.5.1

Becky Bruce

author

2008-11-05 20:55 UTC #7 lore raw

PATCH 7/9 mpc86xx: Change early FLASH mapping to 1M at CONFIG_MONITOR_BASE_EARLY

We define CONFIG_MONITOR_BASE_EARLY to define the initial location
of the bootpage in flash. Use this to create an early mapping
definition for the FLASH, and change the early_bats code to use this.

This change facilitates the relocation of the flash since the early mappings are no longer tied to the final location of the flash.

Signed-off-by Becky Bruce <[email protected]>

---
 cpu/mpc86xx/start.S           |   20 ++++++++++----------
 include/configs/MPC8610HPCD.h |    9 +++++++++
 include/configs/MPC8641HPCN.h |   12 +++++++++++-
 include/configs/sbc8641d.h    |    9 +++++++++
 4 files changed, 39 insertions(+), 11 deletions(-)

cpu/mpc86xx/start.S +10 ~~-10~~

index 7e36801..60af3dd 100644
@@ -217,8 +217,8 @@ boot_warm:
 	/*
 	 * Calculate absolute address in FLASH and jump there
 	 *------------------------------------------------------*/
-	lis	r3, CONFIG_SYS_MONITOR_BASE at h
-	ori	r3, r3, CONFIG_SYS_MONITOR_BASE at l
+	lis	r3, CONFIG_SYS_MONITOR_BASE_EARLY at h
+	ori	r3, r3, CONFIG_SYS_MONITOR_BASE_EARLY at l
 	addi	r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
 	mtlr	r3
 	blr

@@ -398,19 +398,19 @@ early_bats:
 	isync
 
 	/* IBAT 6 */
-	lis	r4, CONFIG_SYS_IBAT6L at h
-	ori     r4, r4, CONFIG_SYS_IBAT6L at l
-	lis	r3, CONFIG_SYS_IBAT6U at h
-	ori     r3, r3, CONFIG_SYS_IBAT6U at l
+	lis	r4, CONFIG_SYS_IBAT6L_EARLY at h
+	ori     r4, r4, CONFIG_SYS_IBAT6L_EARLY at l
+	lis	r3, CONFIG_SYS_IBAT6U_EARLY at h
+	ori     r3, r3, CONFIG_SYS_IBAT6U_EARLY at l
 	mtspr   IBAT6L, r4
 	mtspr   IBAT6U, r3
 	isync
 
 	/* DBAT 6 */
-	lis	r4, CONFIG_SYS_DBAT6L at h
-	ori     r4, r4, CONFIG_SYS_DBAT6L at l
-	lis	r3, CONFIG_SYS_DBAT6U at h
-	ori     r3, r3, CONFIG_SYS_DBAT6U at l
+	lis	r4, CONFIG_SYS_DBAT6L_EARLY at h
+	ori     r4, r4, CONFIG_SYS_DBAT6L_EARLY at l
+	lis	r3, CONFIG_SYS_DBAT6U_EARLY at h
+	ori     r3, r3, CONFIG_SYS_DBAT6U_EARLY at l
 	mtspr   DBAT6L, r4
 	mtspr   DBAT6U, r3
 	isync

include/configs/MPC8610HPCD.h +9 -0

index 4486763..f2fe4a6 100644
@@ -187,6 +187,7 @@
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
 
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI

@@ -419,6 +420,14 @@
 #define CONFIG_SYS_IBAT6L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
 
+/* Map the last 1M of flash where we're running from reset */
+#define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U_EARLY	(TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
+
 /*
  * BAT7		4M	Cache-inhibited, guarded
  * 0xe800_0000	4M	PIXIS

include/configs/MPC8641HPCN.h +11 -1

index 0a6d5f9..4925057 100644
@@ -206,7 +206,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #undef	CONFIG_SYS_FLASH_CHECKSUM
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE		TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
 
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI

@@ -497,6 +498,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 				 | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
 
+/* Map the last 1M of flash where we're running from reset */
+#define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U_EARLY	(TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
+
+/* Leave BAT7 free here - it is used for various things later */
 #define CONFIG_SYS_DBAT7L 0x00000000
 #define CONFIG_SYS_DBAT7U 0x00000000
 #define CONFIG_SYS_IBAT7L 0x00000000

include/configs/sbc8641d.h +9 -0

index e8216ea..45d8179 100644
@@ -231,6 +231,7 @@
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
 
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI

@@ -463,6 +464,14 @@
 #define CONFIG_SYS_IBAT6L	((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
 
+/* Map the last 1M of flash where we're running from reset */
+#define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U_EARLY	(TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
+
 #define CONFIG_SYS_DBAT7L	0x00000000
 #define CONFIG_SYS_DBAT7U	0x00000000
 #define CONFIG_SYS_IBAT7L	0x00000000

Signature · 1 line

1.5.5.1

Becky Bruce

author

2008-11-05 20:55 UTC #8 lore raw

PATCH 8/9 mpc8641: Change 32-bit memory map

The memory map on the 8641hpcn is modified to look more like the 85xx boards; this is a step towards a more standardized layout going forward. As part of this change, we now relocate the flash.

The regions for some of the mappings were far larger than they needed to be. I have reduced the mappings to match the actual sizes supported by the hardware.

In addition I have removed the comments at the head of the BAT blocks in the config file, rather than updating them. These get horribly out of date, and it's a simple matter to look at the defines to see what they are set to since everything is right here in the same file.

Signed-off-by Becky Bruce <[email protected]>

---
 board/freescale/mpc8641hpcn/config.mk |    2 +-
 board/freescale/mpc8641hpcn/law.c     |   23 ++++++----
 cpu/mpc86xx/start.S                   |    2 +-
 include/configs/MPC8641HPCN.h         |   76 +++++++++++++++++----------------
 4 files changed, 54 insertions(+), 49 deletions(-)

board/freescale/mpc8641hpcn/config.mk +1 -1

index f778dcb..487a766 100644
@@ -25,7 +25,7 @@
 # default CCSRBAR is at 0xff700000
 # assume U-Boot is less than 0.5MB
 #
-TEXT_BASE = 0xfff00000
+TEXT_BASE = 0xeff00000
 
 PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
 PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float

board/freescale/mpc8641hpcn/law.c +13 ~~-10~~

index 8ec5238..669a091 100644
@@ -31,17 +31,20 @@
  * LAW(Local Access Window) configuration:
  *
  * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * if PCI
  * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
  * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
- * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
- * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
- * 0xe300_0000     0xe3ff_ffff     PCI2 IO                 16M
- * 0xf800_0000     0xf80f_ffff     CCSRBAR                 1M
- * 0xf810_0000     0xf81f_ffff     PIXIS                   1M
- * 0xfe00_0000     0xffff_ffff     FLASH (boot bank)       32M
+ * else if RIO
+ * 0x8000_0000     0x9fff_ffff     RapidIO                 512M
+ * endif
+ * 0xffc0_0000     0xffc0_ffff     PCI1 IO                 64K
+ * 0xffc1_0000     0xffc1_ffff     PCI2 IO                 64K
+ * 0xffe0_0000     0xffef_ffff     CCSRBAR                 1M
+ * 0xffdf_0000     0xffe0_0000     PIXIS, CF               64K
+ * 0xef80_0000     0xefff_ffff     FLASH (boot bank)       8M
  *
  * Notes:
- *    CCSRBAR don't need a configured Local Access Window.
+ *    CCSRBAR doesn't need a configured Local Access Window.
  *    If flash is 8M at default position (last 8M), no LAW needed.
  */

@@ -52,12 +55,12 @@ struct law_entry law_table[] = {
 #ifdef CONFIG_PCI
 	SET_LAW(CONFIG_SYS_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
 	SET_LAW(CONFIG_SYS_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2),
 #elif defined(CONFIG_RIO)
 	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 #endif
-	SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
+	SET_LAW(PIXIS_BASE, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
 };

cpu/mpc86xx/start.S +1 -1

index 60af3dd..0aa8a4f 100644
@@ -285,7 +285,7 @@ addr_trans_enabled:
 #ifdef	RUN_DIAG
 
 	/* Load PX_AUX register address in r4 */
-	lis	r4, 0xf810
+	lis	r4, PIXIS_BASE at h
 	ori	r4, r4, 0x6
 	/* Load contents of PX_AUX in r3 bits 24 to 31*/
 	lbz	r3, 0(r4)

include/configs/MPC8641HPCN.h +39 ~~-37~~

172 lines not on this page · raw message

Signature · 1 line

1.5.5.1

Becky Bruce

author

2008-11-05 20:55 UTC #9 lore raw

PATCH 9/9 mpc8641: Support 36-bit physical addressing

This patch creates a memory map with all the devices in 36-bit physical space, in addition to the 32-bit map. The CCSR relocation is moved (again, sorry) to allow for the physical address to be 36 bits - this requires translation to be enabled. With 36-bit physical addressing enabled, we are no longer running with VA=PA translations. This means we have to distinguish between the two in the config file. The existing region name is used to indicate the virtual address, and a _PHYS variety is created to represent the physical address.

Large physical addressing is not enabled by default. Set CONFIG_PHYS_64BIT in the config file to turn this on.

Signed-off-by Becky Bruce <[email protected]>

---
 board/freescale/mpc8641hpcn/law.c |   13 ++--
 cpu/mpc86xx/start.S               |   44 ++++++++---
 include/configs/MPC8641HPCN.h     |  164 +++++++++++++++++++++++++++++--------
 3 files changed, 168 insertions(+), 53 deletions(-)

board/freescale/mpc8641hpcn/law.c +7 -6

index 669a091..bd357b8 100644
@@ -31,12 +31,13 @@
  * LAW(Local Access Window) configuration:
  *
  * 0x0000_0000     0x7fff_ffff     DDR                     2G
- * if PCI
+ * if PCI (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
  * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
  * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
- * else if RIO
+ * else if RIO (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
  * 0x8000_0000     0x9fff_ffff     RapidIO                 512M
  * endif
+ * (prepend 0xf_0000_0000 if CONFIG_PHYS_64BIT)
  * 0xffc0_0000     0xffc0_ffff     PCI1 IO                 64K
  * 0xffc1_0000     0xffc1_ffff     PCI2 IO                 64K
  * 0xffe0_0000     0xffef_ffff     CCSRBAR                 1M

@@ -53,15 +54,15 @@ struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
 #endif
 #ifdef CONFIG_PCI
-	SET_LAW(CONFIG_SYS_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
 	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1),
 	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2),
 #elif defined(CONFIG_RIO)
 	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 #endif
-	SET_LAW(PIXIS_BASE, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
+	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

cpu/mpc86xx/start.S +33 ~~-11~~

73 lines not on this page · raw message

include/configs/MPC8641HPCN.h +128 ~~-36~~

301 lines not on this page · raw message

Signature · 1 line

1.5.5.1

Kumar Gala

2008-11-05 21:42 UTC #10 lore raw

PATCH 9/9 mpc8641: Support 36-bit physical addressing

Quoted 14 lines · Becky Bruce

This patch creates a memory map with all the devices in 36-bit physical space, in addition to the 32-bit map. The CCSR relocation is moved (again, sorry) to allow for the physical address to be 36 bits - this requires translation to be enabled. With 36-bit physical addressing enabled, we are no longer running with VA=PA translations. This means we have to distinguish between the two in the config file. The existing region name is used to indicate the virtual address, and a _PHYS variety is created to represent the physical address.
Large physical addressing is not enabled by default. Set CONFIG_PHYS_64BIT in the config file to turn this on.

Quoted 7 lines

Signed-off-by Becky Bruce <[email protected]>

---

board/freescale/mpc8641hpcn/law.c |   13 ++--
cpu/mpc86xx/start.S               |   44 ++++++++---
include/configs/MPC8641HPCN.h     |  164 ++++++++++++++++++++++++++++ 
+--------
3 files changed, 168 insertions(+), 53 deletions(-)

Can we add something to the top level Makefile like the following:

MPC8641HPCN_36BIT_config \
MPC8641HPCN_config: unconfig

         @mkdir -p $(obj)include
         @if [ "$(findstring _36BIT_,$@)" ] ; then \
                 $(XECHO) -n "... I Rock " ; \
                 echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/ 
config.h ;\
         fi ;
         @$(MKCONFIG) -a MPC8641HPCN ppc mpc86xx mpc8641hpcn freescale

(also add this to MAKEALL)

The name could be better.

- k

Becky Bruce

author

2008-11-06 19:04 UTC #11 lore raw

PATCH 1/1 toplevel Makefile: Add MPC8641HPCN_36BIT target

This will enable CONFIG_PHYS_36BIT for MPC8641HPCN.

Signed-off-by Becky Bruce <[email protected]>

---
 Makefile |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)

Makefile +7 -1

index 983a3cd..09e671d 100644
@@ -2436,8 +2436,14 @@ TQM8560_config:		unconfig
 MPC8610HPCD_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8610hpcd freescale
 
+MPC8641HPCN_36BIT_config \
 MPC8641HPCN_config:    unconfig
-	@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn freescale
+	@mkdir -p $(obj)include
+	@if [ "$(findstring _36BIT_,$@)" ] ; then \
+		echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \
+		$(XECHO) "... enabling 36-bit physical addressing." ; \
+	fi
+	@$(MKCONFIG) -a MPC8641HPCN ppc mpc86xx mpc8641hpcn freescale
 
 sbc8641d_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc86xx sbc8641d

Signature · 1 line

1.5.6.5

Scott Wood

2008-11-06 21:06 UTC #12 lore raw

PATCH 1/1 toplevel Makefile: Add MPC8641HPCN_36BIT target

Quoted 17 lines · Becky Bruce

This will enable CONFIG_PHYS_36BIT for MPC8641HPCN.

Signed-off-by Becky Bruce <[email protected]>

---
 Makefile |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)

Makefile +1 -0

index 983a3cd..09e671d 100644
@@ -2436,8 +2436,14 @@ TQM8560_config:		unconfig
 MPC8610HPCD_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8610hpcd freescale
 
+MPC8641HPCN_36BIT_config \
 MPC8641HPCN_config:    unconfig

Makefile TQM8560_config: unconfig · line 2449

Quoted 10 lines

Makefile +6 -1

-	@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn freescale
+	@mkdir -p $(obj)include
+	@if [ "$(findstring _36BIT_,$@)" ] ; then \
+		echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \
+		$(XECHO) "... enabling 36-bit physical addressing." ; \
+	fi
+	@$(MKCONFIG) -a MPC8641HPCN ppc mpc86xx mpc8641hpcn freescale
 
 sbc8641d_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc86xx sbc8641d

When would you ever not turn this on?

-Scott

Becky Bruce

author

2008-11-06 21:40 UTC #13 lore raw

PATCH 1/1 toplevel Makefile: Add MPC8641HPCN_36BIT target

Quoted 18 lines · Scott Wood

Quoted 17 lines · Becky Bruce
This will enable CONFIG_PHYS_36BIT for MPC8641HPCN.
Signed-off-by Becky Bruce <[email protected]>
---
Makefile | 8 +++++++-
1 files changed, 7 insertions(+), 1 deletions(-)
Makefile +0 -0
index 983a3cd..09e671d 100644
@@ -2436,8 +2436,14 @@ TQM8560_config:		unconfig
MPC8610HPCD_config: unconfig
	@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8610hpcd freescale
+MPC8641HPCN_36BIT_config \
MPC8641HPCN_config: unconfig
Makefile +2 -1
-	@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn freescale
+	@mkdir -p $(obj)include
+	@if [ "$(findstring _36BIT_,$@)" ] ; then \

Quoted 9 lines

Quoted 6 lines

Makefile +4 -0

+		echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \
+		$(XECHO) "... enabling 36-bit physical addressing." ; \
+	fi
+	@$(MKCONFIG) -a MPC8641HPCN ppc mpc86xx mpc8641hpcn freescale
 sbc8641d_config:	unconfig

	@$(MKCONFIG) $(@:_config=) ppc mpc86xx sbc8641d

When would you ever not turn this on?

We don't want PHYS_64BIT on unconditionally. It has the effect of moving all the devices into high physical memory, which means you need a different Linux/dts. I expect the normal case to be that it is off. Just those few customers that actually want to do this will use the PHYS_64BIT version.

Cheers,
B

Scott Wood

2008-11-06 21:59 UTC #14 lore raw

PATCH 1/1 toplevel Makefile: Add MPC8641HPCN_36BIT target

Quoted 3 lines · Becky Bruce

We don't want PHYS_64BIT on unconditionally. It has the effect of moving all the devices into high physical memory, which means you need a different Linux/dts.

Another reason we should really be packaging the device trees with u-boot.

Quoted 3 lines

I expect the normal case to be that it is off.
Just those few customers that actually want to do this will use the PHYS_64BIT version.

OK, though ideally it could be chosen dynamically based on how much memory there is (in u-boot) or #address-cells (in linux).

-Scott

Becky Bruce

author

2008-11-06 22:07 UTC #15 lore raw

PATCH 1/1 toplevel Makefile: Add MPC8641HPCN_36BIT target

Quoted 8 lines · Scott Wood

Quoted 3 lines · Becky Bruce
We don't want PHYS_64BIT on unconditionally. It has the effect of moving all the devices into high physical memory, which means you need a different Linux/dts.
Another reason we should really be packaging the device trees with u- boot.

Quoted 7 lines

Quoted 3 lines
I expect the normal case to be that it is off. Just those few customers that actually want to do this will use the PHYS_64BIT version.
OK, though ideally it could be chosen dynamically based on how much memory there is (in u-boot) or #address-cells (in linux).

Well, in an ideal world, I'd have an IOMMU ;-) I left this build-time configurable because turning on PHYS_64BIT makes u-boot bigger, and there are always people who shout about that. There are also scenarios where you want to run with it enabled, and you don't have a lot of RAM. And, last but not least, I want to be consistent with linux, where 36-bit is a build-time configurable thing. Going to 36- bit requires that you know what you're doing - you need a 36b enabled kernel and .dts in order to boot - I don't want u-boot silently turning it on. At least not for a while.

-Becky

Becky Bruce

author

2008-11-06 23:37 UTC #16 lore raw

PATCH v2 9/9 mpc8641: Support 36-bit physical addressing

In reply to Becky Bruce

Large physical addressing is not enabled by default. Set CONFIG_PHYS_64BIT in the config file to turn this on.

Signed-off-by Becky Bruce <[email protected]>

---
 board/freescale/mpc8641hpcn/law.c |   13 ++--
 cpu/mpc86xx/start.S               |   44 ++++++++---
 doc/README.mpc8641hpcn            |   24 ++++++
 include/configs/MPC8641HPCN.h     |  164 +++++++++++++++++++++++++++++--------
 4 files changed, 192 insertions(+), 53 deletions(-)

board/freescale/mpc8641hpcn/law.c +7 -6

index 669a091..bd357b8 100644
@@ -31,12 +31,13 @@
  * LAW(Local Access Window) configuration:
  *
  * 0x0000_0000     0x7fff_ffff     DDR                     2G
- * if PCI
+ * if PCI (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
  * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
  * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
- * else if RIO
+ * else if RIO (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
  * 0x8000_0000     0x9fff_ffff     RapidIO                 512M
  * endif
+ * (prepend 0xf_0000_0000 if CONFIG_PHYS_64BIT)
  * 0xffc0_0000     0xffc0_ffff     PCI1 IO                 64K
  * 0xffc1_0000     0xffc1_ffff     PCI2 IO                 64K
  * 0xffe0_0000     0xffef_ffff     CCSRBAR                 1M

@@ -53,15 +54,15 @@ struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
 #endif
 #ifdef CONFIG_PCI
-	SET_LAW(CONFIG_SYS_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
 	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1),
 	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2),
 #elif defined(CONFIG_RIO)
 	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 #endif
-	SET_LAW(PIXIS_BASE, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
+	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

cpu/mpc86xx/start.S +33 ~~-11~~

73 lines not on this page · raw message

doc/README.mpc8641hpcn +24 -0

index 24b39f1..dbdf244 100644
@@ -113,6 +113,9 @@ To Flash U-boot into the alternative bank (0xEF800000 - 0xEFBFFFFF):
 -------------
 NOTE:  RIO and PCI are mutually exclusive, so they share an address
 
+For 32-bit u-boot, devices are mapped so that the virtual address ==
+the physical address, and the map looks liks this:
+
 	Memory Range			Device		Size
 	------------			------		----
 	0x0000_0000	0x7fff_ffff	DDR		2G

@@ -127,6 +130,27 @@ NOTE:  RIO and PCI are mutually exclusive, so they share an address
 	0xffc1_0000	0xffc1_ffff	PCI2/PEX2 IO	64K
 	0xef80_0000	0xefff_ffff	Flash		8M
 
+For 36-bit-enabled u-boot, the virtual map is the same as for 32-bit.
+However, the physical map is altered to reside in 36-bit space, as follows.
+Addresses are no longer mapped with VA == PA.  All accesses from 
+software use the VA; the PA is only used for setting up windows
+and mappings. Note that the low 32 bits are the same as the VA above;
+only the top 4 bits vary:
+
+	Memory Range			Device		Size
+	------------			------		----
+	0x0_0000_0000	0x0_7fff_ffff	DDR		2G
+	0xc_8000_0000	0xc_9fff_ffff	RIO MEM		512M		
+	0xc_8000_0000	0xc_9fff_ffff	PCI1/PEX1 MEM	512M
+	0xc_a000_0000	0xc_bfff_ffff	PCI2/PEX2 MEM	512M
+	0xf_ffe0_0000	0xf_ffef_ffff	CCSR		1M
+	0xf_ffdf_0000	0xf_ffdf_7fff	PIXIS		8K
+	0xf_ffdf_8000	0xf_ffdf_ffff	CF		8K
+	0x0_f840_0000	0xf_f840_3fff	Stack space	32K
+	0xf_ffc0_0000	0xf_ffc0_ffff	PCI1/PEX1 IO	64K
+	0xf_ffc1_0000	0xf_ffc1_ffff	PCI2/PEX2 IO	64K
+	0xf_ef80_0000	0xf_efff_ffff	Flash		8M
+
 5. pixis_reset command
 --------------------
 A new command, "pixis_reset", is introduced to reset mpc8641hpcn board

include/configs/MPC8641HPCN.h +128 ~~-36~~

301 lines not on this page · raw message

Signature · 1 line

1.5.6.5

Scott Wood

2008-11-06 19:28 UTC #17 lore raw

PATCH 8/9 mpc8641: Change 32-bit memory map

In reply to Becky Bruce

Quoted 8 lines · Becky Bruce

The memory map on the 8641hpcn is modified to look more like the 85xx boards; this is a step towards a more standardized layout going forward. As part of this change, we now relocate the flash.
The regions for some of the mappings were far larger than they needed to be. I have reduced the mappings to match the actual sizes supported by the hardware.

Was this causing any actual problems? It seems to be inviting gratuitous breakage if the device tree isn't updated at the same time, or for any OSes not using the device tree.

-Scott

Becky Bruce

author

2008-11-06 22:12 UTC #18 lore raw

PATCH 8/9 mpc8641: Change 32-bit memory map

Quoted 9 lines · Scott Wood

Quoted 7 lines · Becky Bruce
The memory map on the 8641hpcn is modified to look more like the 85xx boards; this is a step towards a more standardized layout going forward. As part of this change, we now relocate the flash.
The regions for some of the mappings were far larger than they needed to be. I have reduced the mappings to match the actual sizes supported by the hardware.

Quoted 4 lines

Was this causing any actual problems? It seems to be inviting gratuitous breakage if the device tree isn't updated at the same time, or for any OSes not using the device tree.

Was it causing any problems for anybody running it? Only minor stuff. Was it causing maintenance to be a god-awful nightmare? Definitely. The map for 86xx was a real mess, and really needed to be cleaned up - trying to make sense of the previous code was a real pain, and the whole structure of it was very fragile - any attempt to make a change resulted in random breakage because it was such a house of cards (which I ran into repeatedly while doing the 36b stuff). The decision to change the map was also made for ease of code maintenance
- having a similar map to 85xx makes it much easier now to port the 36b changes over to that platform which is the next major task. The boot sequences for the 2 platforms are also a lot more similar now, so I'm hoping that a little bit of pain now will save us a lot more pain in the future.

I agree that there's potential for breakage, but in the case of Linux, which is the vast majority of u-boot users, I think it's minimal. For the non-linux cases, changing an OS to accomodate the new map should be a minor task.

The device tree changes are in hand, and as soon as this goes into the u-boot tree, I will push those to Linux.

We *do* need a comment in the release notes for this revision of u- boot that the map for 8641 has changed so it doesn't catch anyone by surprise.

-B

Scott Wood

2008-11-06 22:16 UTC #19 lore raw

PATCH 8/9 mpc8641: Change 32-bit memory map

Quoted 2 lines · Becky Bruce

We *do* need a comment in the release notes for this revision of u-boot that the map for 8641 has changed so it doesn't catch anyone by surprise.

How about a runtime check in the board fdt code to print a warning if it finds an old device tree? Unfortunately, using new dts with old u-boot isn't as easy to detect.

-Scott

Becky Bruce

author

2008-11-06 22:24 UTC #20 lore raw

PATCH 8/9 mpc8641: Change 32-bit memory map

Quoted 8 lines · Scott Wood

Quoted 3 lines · Becky Bruce
We *do* need a comment in the release notes for this revision of u- boot that the map for 8641 has changed so it doesn't catch anyone by surprise.
How about a runtime check in the board fdt code to print a warning if it finds an old device tree? Unfortunately, using new dts with old u-boot isn't as easy to detect.

Where exactly were you thinking this would go? I'm not sure what to detect - I could pretty easily do a rudimentary check, like checking if the CCSR location in the .dts is the same as the one u-boot has, but there's always the possiblity that someone has hacked their u-boot to put the CCSR in the same spot.

-B

Scott Wood

2008-11-06 22:26 UTC #21 lore raw

PATCH 8/9 mpc8641: Change 32-bit memory map

Quoted 6 lines · Becky Bruce

Quoted 3 lines · Scott Wood
How about a runtime check in the board fdt code to print a warning if it finds an old device tree? Unfortunately, using new dts with old u-boot isn't as easy to detect.
Where exactly were you thinking this would go?

ft_board_setup()

Quoted 5 lines

I'm not sure what to
detect - I could pretty easily do a rudimentary check, like checking if the CCSR location in the .dts is the same as the one u-boot has, but there's always the possiblity that someone has hacked their u-boot to put the CCSR in the same spot.

Well then they can hack the warning out. :-)

-Scott

Becky Bruce

author

2008-11-07 19:45 UTC #22 lore raw

PATCH 1/1 mpc8641: Try to detect old .dts files

Since we've changed the memory map of the board, be nice and add some checking to try to catch out-of-date .dts files. We do this by checking the CCSRBAR location in the .dts and comparing it to the CCSRBAR location in u-boot. If they don't match, a warning msg is printed. This isn't foolproof, but it's simple and will catch most of the cases where an out-of-date .dts is present, including all of the cases where a new u-boot is used with an old standard MPC8641 .dts file as supplied with Linux.

Signed-off-by Becky Bruce <[email protected]>

---
 board/freescale/mpc8641hpcn/mpc8641hpcn.c |   27 +++++++++++++++++++++++++++
 include/configs/MPC8641HPCN.h             |    3 +++
 2 files changed, 30 insertions(+), 0 deletions(-)

board/freescale/mpc8641hpcn/mpc8641hpcn.c +27 -0

index d6a0a56..1f9f2a3 100644
@@ -254,6 +254,10 @@ extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
 void
 ft_board_setup(void *blob, bd_t *bd)
 {
+	int off;
+	u64 *tmp;
+	u32 *addrcells;
+
 	ft_cpu_setup(blob, bd);
 
 #ifdef CONFIG_PCI1

@@ -262,6 +266,29 @@ ft_board_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_PCI2
 	ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
 #endif
+
+	/*
+	 * Warn if it looks like the device tree doesn't match u-boot.
+	 * This is just an estimation, based on the location of CCSR,
+	 * which is defined by the "reg" property in the soc node.
+	 */
+	off = fdt_path_offset(blob, "/soc8641");
+	addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
+	tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
+
+	if (tmp) {
+		u64 addr;
+		if (addrcells && (*addrcells == 2))
+			addr = *tmp;
+		else
+			addr = *(u32 *)tmp;
+
+		if (addr != CONFIG_SYS_CCSRBAR_PHYS)
+			printf("WARNING: The CCSRBAR address in your .dts "
+			       "does not match the address of the CCSR "
+			       "in u-boot.  This means your .dts might "
+			       "be old.\n");
+	}
 }
 #endif

include/configs/MPC8641HPCN.h +3 -0

index c84ae5e..69b4c44 100644
@@ -115,8 +115,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0xf
+#define CONFIG_SYS_CCSRBAR_PHYS		(CONFIG_SYS_CCSRBAR_PHYS_LOW \
+					 | ((u64)CONFIG_SYS_CCSRBAR_PHYS_HIGH << 32))
 #else
 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0x0
+#define CONFIG_SYS_CCSRBAR_PHYS		CONFIG_SYS_CCSRBAR_PHYS_LOW
 #endif
 
 #define CONFIG_SYS_PCI1_ADDR		(CONFIG_SYS_CCSRBAR+0x8000)

Signature · 1 line

1.5.6.5

Scott Wood

2008-11-10 22:58 UTC #23 lore raw

PATCH 1/1 mpc8641: Try to detect old .dts files

board/freescale/mpc8641hpcn/mpc8641hpcn.c ft_board_setup(void *blob, bd_t *bd) · line 284

Quoted 6 lines · Becky Bruce

board/freescale/mpc8641hpcn/mpc8641hpcn.c +6 -0

+	if (tmp) {
+		u64 addr;
+		if (addrcells && (*addrcells == 2))
+			addr = *tmp;
+		else
+			addr = *(u32 *)tmp;

If #address-cells is missing (not that it ever should be), the default is 2, not 1.

-Scott

Becky Bruce

author

2008-11-10 23:09 UTC #24 lore raw

PATCH 1/1 mpc8641: Try to detect old .dts files

Quoted 10 lines · Scott Wood

board/freescale/mpc8641hpcn/mpc8641hpcn.c ft_board_setup(void *blob, bd_t *bd) · line 284
Quoted 6 lines · Becky Bruce
board/freescale/mpc8641hpcn/mpc8641hpcn.c +6 -0
+	if (tmp) {
+		u64 addr;
+		if (addrcells && (*addrcells == 2))
+			addr = *tmp;
+		else
+			addr = *(u32 *)tmp;
If #address-cells is missing (not that it ever should be), the default is 2, not 1.

I'll post a follow-up; Jon has already picked this up in his tree.

Thanks!
-B

Jon Loeliger

2008-11-06 22:30 UTC #25 lore raw

PATCH 8/9 mpc8641: Change 32-bit memory map

In reply to Scott Wood

Quoted 9 lines · Scott Wood

Quoted 2 lines · Becky Bruce
We *do* need a comment in the release notes for this revision of u-boot that the map for 8641 has changed so it doesn't catch anyone by surprise.
How about a runtime check in the board fdt code to print a warning if it finds an old device tree? Unfortunately, using new dts with old u-boot isn't as easy to detect.
-Scott

For the record, and admittedly not quite an answer to your issue at all, though I feel it would mitigate the pain dramatically, I have a version of the DTS file that uses my new expression language to completely abstract out the 32/36-bit differences and compile a DTB for either with the single flip of a -DUSE_36_BIT handed to the dtc command line.

Even if no one cares.

jdl

Becky Bruce

author

2008-11-06 22:39 UTC #26 lore raw

PATCH 8/9 mpc8641: Change 32-bit memory map

Quoted 24 lines · Jon Loeliger

Quoted 6 lines · Scott Wood
Quoted 4 lines · Becky Bruce
We *do* need a comment in the release notes for this revision of u- boot
that the map for 8641 has changed so it doesn't catch anyone by surprise.
Quoted 7 lines
How about a runtime check in the board fdt code to print a warning if it
finds an old device tree? Unfortunately, using new dts with old u- boot
isn't as easy to detect.
-Scott
For the record, and admittedly not quite an answer to your issue at all, though I feel it would mitigate the pain dramatically, I have a version of the DTS file that uses my new expression language to completely abstract out the 32/36-bit differences and compile a DTB for either with the single flip of a -DUSE_36_BIT handed to the dtc command line.

Quoted 1 line

Even if no one cares.

I think that's something we need to talk about..... what are the plans for switching over to the new language?

I'll push a simple patch to change the 32-bit memory map, but when we go 36-bit in Linux, this might make sense.

-B

Becky Bruce

author

2008-11-06 23:36 UTC #27 lore raw

PATCH v2 8/9 mpc8641: Change 32-bit memory map

The memory map on the 8641hpcn is modified to look more like the 85xx boards; this is a step towards a more standardized layout going forward. As part of this change, we now relocate the flash.

The regions for some of the mappings were far larger than they needed to be. I have reduced the mappings to match the actual sizes supported by the hardware.

Documentation has been changed to reflect the new map, as this change is user visible, and affects the OS which runs post-uboot.

Signed-off-by Becky Bruce <[email protected]>

---
 board/freescale/mpc8641hpcn/config.mk |    2 +-
 board/freescale/mpc8641hpcn/law.c     |   23 ++++++----
 cpu/mpc86xx/start.S                   |    2 +-
 doc/README.mpc8641hpcn                |   40 +++++++++--------
 include/configs/MPC8641HPCN.h         |   76 +++++++++++++++++----------------
 5 files changed, 75 insertions(+), 68 deletions(-)

board/freescale/mpc8641hpcn/config.mk +1 -1

index f778dcb..487a766 100644
@@ -25,7 +25,7 @@
 # default CCSRBAR is at 0xff700000
 # assume U-Boot is less than 0.5MB
 #
-TEXT_BASE = 0xfff00000
+TEXT_BASE = 0xeff00000
 
 PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
 PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float

board/freescale/mpc8641hpcn/law.c +13 ~~-10~~

index 8ec5238..669a091 100644
@@ -31,17 +31,20 @@
  * LAW(Local Access Window) configuration:
  *
  * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * if PCI
  * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
  * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
- * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
- * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
- * 0xe300_0000     0xe3ff_ffff     PCI2 IO                 16M
- * 0xf800_0000     0xf80f_ffff     CCSRBAR                 1M
- * 0xf810_0000     0xf81f_ffff     PIXIS                   1M
- * 0xfe00_0000     0xffff_ffff     FLASH (boot bank)       32M
+ * else if RIO
+ * 0x8000_0000     0x9fff_ffff     RapidIO                 512M
+ * endif
+ * 0xffc0_0000     0xffc0_ffff     PCI1 IO                 64K
+ * 0xffc1_0000     0xffc1_ffff     PCI2 IO                 64K
+ * 0xffe0_0000     0xffef_ffff     CCSRBAR                 1M
+ * 0xffdf_0000     0xffe0_0000     PIXIS, CF               64K
+ * 0xef80_0000     0xefff_ffff     FLASH (boot bank)       8M
  *
  * Notes:
- *    CCSRBAR don't need a configured Local Access Window.
+ *    CCSRBAR doesn't need a configured Local Access Window.
  *    If flash is 8M at default position (last 8M), no LAW needed.
  */

@@ -52,12 +55,12 @@ struct law_entry law_table[] = {
 #ifdef CONFIG_PCI
 	SET_LAW(CONFIG_SYS_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
 	SET_LAW(CONFIG_SYS_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2),
 #elif defined(CONFIG_RIO)
 	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 #endif
-	SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
+	SET_LAW(PIXIS_BASE, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
 };

cpu/mpc86xx/start.S +1 -1

index 60af3dd..0aa8a4f 100644
@@ -285,7 +285,7 @@ addr_trans_enabled:
 #ifdef	RUN_DIAG
 
 	/* Load PX_AUX register address in r4 */
-	lis	r4, 0xf810
+	lis	r4, PIXIS_BASE at h
 	ori	r4, r4, 0x6
 	/* Load contents of PX_AUX in r3 bits 24 to 31*/
 	lbz	r3, 0(r4)

doc/README.mpc8641hpcn +21 ~~-19~~

index 2c3c703..24b39f1 100644
@@ -79,51 +79,53 @@ Switches:
 
 3. Flash U-Boot
 ---------------
-The flash range 0xFF800000 to 0xFFFFFFFF can be divided into 2 halves.
+The flash range 0xEF800000 to 0xEFFFFFFF can be divided into 2 halves.
 It is possible to use either half to boot using u-boot.  Switch 5 bit 2
 is used for this purpose.
 
-0xFF800000 to 0xFFBFFFFF - 4MB
-0xFFC00000 to 0xFFFFFFFF - 4MB
-When this bit is 0, U-Boot is at 0xFFF00000.
-When this bit is 1, U-Boot is at 0xFFB00000.
+0xEF800000 to 0xEFBFFFFF - 4MB
+0xEFC00000 to 0xEFFFFFFF - 4MB
+When this bit is 0, U-Boot is at 0xEFF00000.
+When this bit is 1, U-Boot is at 0xEFB00000.
 
 Use the above mentioned flash commands to program the other half, and
 use switch 5, bit 2 to alternate between the halves.  Note: The booting
-version of U-Boot will always be at 0xFFF00000.
+version of U-Boot will always be at 0xEFF00000.
 
-To Flash U-Boot into the booting bank (0xFFC00000 - 0xFFFFFFFF):
+To Flash U-Boot into the booting bank (0xEFC00000 - 0xEFFFFFFF):
 
 	tftp 1000000 u-boot.bin
 	protect off all
-	erase fff00000 +$filesize
-	cp.b 1000000 fff00000 $filesize
+	erase eff00000 +$filesize
+	cp.b 1000000 eff00000 $filesize
 
 or use tftpflash command:
 	run tftpflash
 
-To Flash U-boot into the alternative bank (0xFF800000 - 0xFFBFFFFF):
+To Flash U-boot into the alternative bank (0xEF800000 - 0xEFBFFFFF):
 
 	tftp 1000000 u-boot.bin
-	erase ffb00000 +$filesize
-	cp.b 1000000 ffb00000 $filesize
+	erase efb00000 +$filesize
+	cp.b 1000000 efb00000 $filesize
 
 
 4. Memory Map
 -------------
+NOTE:  RIO and PCI are mutually exclusive, so they share an address
 
 	Memory Range			Device		Size
 	------------			------		----
 	0x0000_0000	0x7fff_ffff	DDR		2G
+	0x8000_0000	0x9fff_ffff	RIO MEM		512M		
 	0x8000_0000	0x9fff_ffff	PCI1/PEX1 MEM	512M
-	0xa000_0000	0xafff_ffff	PCI2/PEX2 MEM	512M
-	0xf800_0000	0xf80f_ffff	CCSR		1M
-	0xf810_0000	0xf81f_ffff	PIXIS		1M
+	0xa000_0000	0xbfff_ffff	PCI2/PEX2 MEM	512M
+	0xffe0_0000	0xffef_ffff	CCSR		1M
+	0xffdf_0000	0xffdf_7fff	PIXIS		8K
+	0xffdf_8000	0xffdf_ffff	CF		8K
 	0xf840_0000	0xf840_3fff	Stack space	32K
-	0xe200_0000	0xe2ff_ffff	PCI1/PEX1 IO	16M
-	0xe300_0000	0xe3ff_ffff	PCI2/PEX2 IO	16M
-	0xfe00_0000	0xfeff_ffff	Flash(alternate)16M
-	0xff00_0000	0xffff_ffff	Flash(boot bank)16M
+	0xffc0_0000	0xffc0_ffff	PCI1/PEX1 IO	64K
+	0xffc1_0000	0xffc1_ffff	PCI2/PEX2 IO	64K
+	0xef80_0000	0xefff_ffff	Flash		8M
 
 5. pixis_reset command
 --------------------

include/configs/MPC8641HPCN.h +39 ~~-37~~

172 lines not on this page · raw message

Signature · 1 line

1.5.6.5

Jon Loeliger

2008-11-06 20:04 UTC #28 lore raw

PATCH 8/9 mpc8641: Change 32-bit memory map

In reply to Becky Bruce

Quoted 15 lines · Becky Bruce

The memory map on the 8641hpcn is modified to look more like the 85xx boards; this is a step towards a more standardized layout going forward. As part of this change, we now relocate the flash.
The regions for some of the mappings were far larger than they needed to be. I have reduced the mappings to match the actual sizes supported by the hardware.
In addition I have removed the comments at the head of the BAT blocks in the config file, rather than updating them. These get horribly out of date, and it's a simple matter to look at the defines to see what they are set to since everything is right here in the same file.

Quoted 7 lines

Signed-off-by Becky Bruce <[email protected]>

---
 board/freescale/mpc8641hpcn/config.mk |    2 +-
 board/freescale/mpc8641hpcn/law.c     |   23 ++++++----
 cpu/mpc86xx/start.S                   |    2 +-
 include/configs/MPC8641HPCN.h         |   76 +++++++++++++++++----------------
 4 files changed, 54 insertions(+), 49 deletions(-)

Does this affect any flash addresses mentioned in
the README.mpc86xx too?

jdl

Becky Bruce

author

2008-11-06 22:14 UTC #29 lore raw

PATCH 8/9 mpc8641: Change 32-bit memory map

Quoted 25 lines · Jon Loeliger

Quoted 15 lines · Becky Bruce
The memory map on the 8641hpcn is modified to look more like the 85xx boards; this is a step towards a more standardized layout going forward. As part of this change, we now relocate the flash.
The regions for some of the mappings were far larger than they needed to be. I have reduced the mappings to match the actual sizes supported by the hardware.
In addition I have removed the comments at the head of the BAT blocks in the config file, rather than updating them. These get horribly out of date, and it's a simple matter to look at the defines to see what they are set to since everything is right here in the same file.
Quoted 8 lines
Signed-off-by Becky Bruce <[email protected]>
---
board/freescale/mpc8641hpcn/config.mk |    2 +-
board/freescale/mpc8641hpcn/law.c     |   23 ++++++----
cpu/mpc86xx/start.S                   |    2 +-
include/configs/MPC8641HPCN.h         |   76 ++++++++++++++++ 
+----------------
4 files changed, 54 insertions(+), 49 deletions(-)

Quoted 2 lines

Does this affect any flash addresses mentioned in
the README.mpc86xx too?

Yes, it does. It affects a lot of stuff in that file which I was, until now, unaware of. Will fix. Thanks!
-Becky

Becky Bruce

author

2008-11-06 23:41 UTC #30 lore raw

PATCH 8/9 mpc8641: Change 32-bit memory map

In reply to Jon Loeliger

Quoted 25 lines · Jon Loeliger

Quoted 15 lines · Becky Bruce
The memory map on the 8641hpcn is modified to look more like the 85xx boards; this is a step towards a more standardized layout going forward. As part of this change, we now relocate the flash.
The regions for some of the mappings were far larger than they needed to be. I have reduced the mappings to match the actual sizes supported by the hardware.
In addition I have removed the comments at the head of the BAT blocks in the config file, rather than updating them. These get horribly out of date, and it's a simple matter to look at the defines to see what they are set to since everything is right here in the same file.
Quoted 8 lines
Signed-off-by Becky Bruce <[email protected]>
---
board/freescale/mpc8641hpcn/config.mk |    2 +-
board/freescale/mpc8641hpcn/law.c     |   23 ++++++----
cpu/mpc86xx/start.S                   |    2 +-
include/configs/MPC8641HPCN.h         |   76 ++++++++++++++++ 
+----------------
4 files changed, 54 insertions(+), 49 deletions(-)

Quoted 2 lines

Does this affect any flash addresses mentioned in
the README.mpc86xx too?

I resubmitted the last 2 patches, now with the appropriate documentation updates. That is the only change.

-Becky