OMAP3: Fix multiline comment style

Index: u-boot-arm/include/asm-arm/arch-omap3/omap3.h
===================================================================
@@ -110,11 +110,11 @@
 
 #define CPU_3430	0x3430
 
-/* 343x real hardware:
+/*
+ * 343x real hardware:
  *  ES1     = rev 0
- */
-
-/* 343x code defines:
+ *
+ * 343x code defines:
  * ES1     = 0+1 = 1
  * ES1     = 1+1 = 1
  */

Index: u-boot-arm/cpu/arm_cortexa8/cpu.c
===================================================================
@@ -186,8 +186,10 @@ void l2cache_enable()
 		__asm__ __volatile__("mov %0, r12":"=r"(j));
 		__asm__ __volatile__("mov %0, r0":"=r"(i));
 
-		/* GP Device ROM code API usage here */
-		/* r12 = AUXCR Write function and r0 value */
+		/*
+		 * GP Device ROM code API usage here
+		 * r12 = AUXCR Write function and r0 value
+		 */
 		__asm__ __volatile__("mov r12, #0x3");
 		__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
 		__asm__ __volatile__("orr r0, r0, #0x2");

@@ -214,8 +216,10 @@ void l2cache_disable()
 		__asm__ __volatile__("mov %0, r12":"=r"(j));
 		__asm__ __volatile__("mov %0, r0":"=r"(i));
 
-		/* GP Device ROM code API usage here */
-		/* r12 = AUXCR Write function and r0 value */
+		/*
+		 * GP Device ROM code API usage here
+		 * r12 = AUXCR Write function and r0 value
+		 */
 		__asm__ __volatile__("mov r12, #0x3");
 		__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
 		__asm__ __volatile__("bic r0, r0, #0x2");

Index: u-boot-arm/cpu/arm_cortexa8/omap3/sys_info.c
===================================================================
@@ -63,7 +63,9 @@ u32 get_cpu_type(void)
 u32 get_cpu_rev(void)
 {
 	u32 cpuid = 0;
-	/* On ES1.0 the IDCODE register is not exposed on L4
+
+	/*
+	 * On ES1.0 the IDCODE register is not exposed on L4
 	 * so using CPU ID to differentiate
 	 * between ES2.0 and ES1.0.
 	 */

90 lines not on this page · raw message

Index: u-boot-arm/cpu/arm_cortexa8/omap3/clock.c
===================================================================
@@ -131,7 +131,8 @@ void prcm_init(void)
 
 	xip_safe = is_running_in_sram();
 
-	/* Gauge the input clock speed and find out the sys_clkin_sel
+	/*
+	 * Gauge the input clock speed and find out the sys_clkin_sel
 	 * value corresponding to the input clock.
 	 */
 	osc_clk = get_osc_clk_speed();

@@ -148,7 +149,8 @@ void prcm_init(void)
 		clk_index = sys_clkin_sel;
 	}
 
-	/* The DPLL tables are defined according to sysclk value and
+	/*
+	 * The DPLL tables are defined according to sysclk value and
 	 * silicon revision. The clk_index value will be used to get
 	 * the values for that input sysclk from the DPLL param table
 	 * and sil_index will get the values for that SysClk for the

@@ -166,12 +168,15 @@ void prcm_init(void)
 	/* Moving it to the right sysclk and ES rev base */
 	dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
 	if (xip_safe) {
-		/* CORE DPLL */
-		/* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
+		/*
+		 * CORE DPLL
+		 * sr32(CM_CLKSEL2_EMU) set override to work when asleep
+		 */
 		sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
 		wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
 
-		/* For OMAP3 ES1.0 Errata 1.50, default value directly doesnt
+		/*
+		 * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't
 		 * work. write another value and then default value.
 		 */
 		sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1);	/* m3x2 */

@@ -191,8 +196,10 @@ void prcm_init(void)
 
 		wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
 	} else if (is_running_in_flash()) {
-		/* if running from flash, jump to small relocated code
-		   area in SRAM. */
+		/*
+		 * if running from flash, jump to small relocated code
+		 * area in SRAM.
+		 */
 		p0 = readl(CM_CLKEN_PLL);
 		sr32((u32) &p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
 		sr32((u32) &p0, 4, 4, dpll_param_p->fsel);	/* FREQSEL */

@@ -225,7 +232,8 @@ void prcm_init(void)
 	/* Moving it to the right sysclk base */
 	dpll_param_p = dpll_param_p + clk_index;
 
-	/* Errata 1.50 Workaround for OMAP3 ES1.0 only
+	/*
+	 * Errata 1.50 Workaround for OMAP3 ES1.0 only
 	 * If using default divisors, write default divisor + 1
 	 * and then the actual divisor value
 	 */

Index: u-boot-arm/cpu/arm_cortexa8/omap3/interrupts.c
===================================================================
@@ -177,8 +177,10 @@ int interrupt_init(void)
 {
 	int32_t val;
 
-	/* Start the counter ticking up */
-	/* reload value on overflow */
+	/*
+	 * Start the counter ticking up
+	 * reload value on overflow
+	 */
 	*((int32_t *) (CONFIG_SYS_TIMERBASE + TLDR)) = TIMER_LOAD_VAL;
 	/* mask to enable timer */
 	val = (CONFIG_SYS_PVT << 2) | BIT5 | BIT1 | BIT0;

Index: u-boot-arm/cpu/arm_cortexa8/omap3/mem.c
===================================================================
@@ -32,7 +32,8 @@
 #include <asm/arch/sys_proto.h>
 #include <command.h>
 
-/* Only One NAND allowed on board at a time.
+/*
+ * Only One NAND allowed on board at a time.
  * The GPMC CS Base for the same
  */
 unsigned int boot_flash_base;

@@ -250,7 +251,8 @@ void gpmc_init(void)
 	config &= (~0xf00);
 	writel(config, gpmc_base + OFFS(GPMC_CONFIG));
 
-	/* Disable the GPMC0 config set by ROM code
+	/*
+	 * Disable the GPMC0 config set by ROM code
 	 * It conflicts with our MPDB (both at 0x08000000)
 	 */
 	writel(0, gpmc_cs_base + OFFS(GPMC_CONFIG7));

Index: u-boot-arm/drivers/mtd/nand/omap_gpmc.c
===================================================================
@@ -43,7 +43,8 @@ static void omap_nand_hwcontrol(struct m
 {
 	register struct nand_chip *this = mtd->priv;
 
-	/* Point the IO_ADDR to DATA and ADDRESS registers instead
+	/*
+	 * Point the IO_ADDR to DATA and ADDRESS registers instead
 	 * of chip address
 	 */
 	switch (ctrl) {

@@ -70,8 +71,10 @@ static void omap_nand_hwcontrol(struct m
  */
 static void omap_hwecc_init(struct nand_chip *chip)
 {
-	/* Init ECC Control Register */
-	/* Clear all ECC | Enable Reg1 */
+	/*
+	 * Init ECC Control Register
+	 * Clear all ECC | Enable Reg1
+	 */
 	writel(ECCCLEAR | ECCRESULTREG1, gpmc_base + OFFS(GPMC_ECC_CONTROL));
 	writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL,
 	       gpmc_base + OFFS(GPMC_ECC_SIZE_CONFIG));

@@ -183,7 +186,8 @@ static int omap_calculate_ecc(struct mtd
 	ecc_code[1] = (val >> 16) & 0xFF;
 	ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
 
-	/* Stop reading anymore ECC vals and clear old results
+	/*
+	 * Stop reading anymore ECC vals and clear old results
 	 * enable will be called if more reads are required
 	 */
 	writel(0x000, gpmc_base + OFFS(GPMC_ECC_CONFIG));

@@ -207,7 +211,8 @@ static void omap_enable_hwecc(struct mtd
 		/* Clear the ecc result registers, select ecc reg as 1 */
 		writel(ECCCLEAR | ECCRESULTREG1,
 		       gpmc_base + OFFS(GPMC_ECC_CONTROL));
-		/* Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes
+		/*
+		 * Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes
 		 * tell all regs to generate size0 sized regs
 		 * we just have a single ECC engine for all CS
 		 */

@@ -222,7 +227,7 @@ static void omap_enable_hwecc(struct mtd
 	}
 }
 
-/**
+/*
  * omap_nand_switch_ecc - switch the ECC operation b/w h/w ecc and s/w ecc.
  * The default is to come up on s/w ecc
  *

@@ -290,14 +295,16 @@ int board_nand_init(struct nand_chip *na
 	int32_t gpmc_config = 0;
 	cs = 0;
 
-	/* xloader/Uboot's gpmc configuration would have configured GPMC for
+	/*
+	 * xloader/Uboot's gpmc configuration would have configured GPMC for
 	 * nand type of memory. The following logic scans and latches on to the
 	 * first CS with NAND type memory.
 	 * TBD: need to make this logic generic to handle multiple CS NAND
 	 * devices.
 	 */
 	while (cs < GPMC_MAX_CS) {
-		/* Each GPMC set for a single CS is at offset 0x30
+		/*
+		 * Each GPMC set for a single CS is@offset 0x30
 		 * - already remapped for us
 		 */
 		gpmc_cs_base = (void __iomem *)(GPMC_CONFIG_CS0_BASE +

Index: u-boot-arm/include/configs/omap3_beagle.h
===================================================================
@@ -179,7 +179,8 @@
 
 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0) /* default load address */
 
-/* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
+/*
+ * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
  * 32KHz clk, or from external sig. This rate is divided by a local divisor.
  */
 #define V_PVT                    7

Index: u-boot-arm/board/omap3/evm/evm.c
===================================================================
@@ -101,9 +101,11 @@ static int setup_net_chip(void)
 	(*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0164)) = 0x00000FCF;
 	(*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0168)) = 0x00000f6c;
 
-	/* Configure PIN MUX registers */
-	/* Enable GPMC Pin Mux Registers */
-	/* Enable GPMC_CLK Pin in CONTROL_PADCONF_gpmc_ncs7 register */
+	/*
+	 * Configure PIN MUX registers
+	 * Enable GPMC Pin Mux Registers
+	 * Enable GPMC_CLK Pin in CONTROL_PADCONF_gpmc_ncs7 register
+	 */
 	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0xBC)) |= 0x00180000;
 	/* Enable CS5 Pin in CONTROL_PADCONF_gpmc_ncs5 register */
 	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0xB8)) |= 0x00000018;

@@ -115,8 +117,10 @@ static int setup_net_chip(void)
 	/* Enable gpmc_nbe0_cle in CONTROL_PADCONF_GPMC_NWE register */
 	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC4)) |= 0x00180000;
 
-	/* Enable gpmc_nbe1 in CONTROL_PADCONF_GPMC_NBE1 register and
-	configuring the mux mode to 0 */
+	/*
+	 * Enable gpmc_nbe1 in CONTROL_PADCONF_GPMC_NBE1 register and
+	 * configuring the mux mode to 0
+	 */
 	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC8)) |= 0x00000018;
 	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC8)) &= 0xFFFFFFF8;
 	/* Enable d15 in CONTROL_PADCONF_GPMC_D15 register */

@@ -155,20 +159,26 @@ static int setup_net_chip(void)
 	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x78)) &= 0xFFFFFFF8;
 
 #if defined(CPU_3430_ES1) || defined(CPU_3430_ES2)
-	/* GPIO 64 configuration in CONTROL_PADCONF_GPMC_WAIT2
-	register mux mode is 4. */
+	/*
+	 * GPIO 64 configuration in CONTROL_PADCONF_GPMC_WAIT2
+	 * register mux mode is 4.
+	 */
 	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0xD0)) |= 0x00000018;
 	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0xD0)) &= 0xFFFFFFF8;
 	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0xD0)) |= 0x00000004;
 
-	/* Configure GPIO 176 in CONTROL_PADCONF_MCSPI1_CS1
-	register for ethernet ISR mux mode is 4 */
+	/*
+	 * Configure GPIO 176 in CONTROL_PADCONF_MCSPI1_CS1
+	 * register for ethernet ISR mux mode is 4
+	 */
 	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x1D0)) |= 0x00180000;
 	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x1D0)) &= 0xFFF8FFFF;
 	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x1D0)) |= 0x00040000;
 
-	/* Enable Clock for GPIO 1-6 module in CM_FCLKEN_PER
-	and CM_ICLKEN_PER registers */
+	/*
+	 * Enable Clock for GPIO 1-6 module in CM_FCLKEN_PER
+	 * and CM_ICLKEN_PER registers
+	 */
 	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x5000)) |= 0x0003E800;
 	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x5010)) |= 0x0003E800;
 

Index: u-boot-arm/include/configs/omap3_evm.h
===================================================================
@@ -189,7 +189,8 @@
 
 #define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load address */
 
-/* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
+/*
+ * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
  * 32KHz clk, or from external sig. This rate is divided by a local divisor.
  */
 #define V_PVT			7

Index: u-boot-arm/include/configs/omap3_overo.h
===================================================================
@@ -170,7 +170,8 @@
 
 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0) /* default load address */
 
-/* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
+/*
+ * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
  * 32KHz clk, or from external sig. This rate is divided by a local divisor.
  */
 #define V_PVT                    7