sh: SH7201, cpu support
PATCH 1/1 sh: SH7201, cpu support
From: Peter Griffin <[email protected]>
sh: SH7201, cpu support
This patch adds support for the SH7201 processor subtype.
Signed-off-by Peter Griffin <[email protected]>
---
arch/sh/Kconfig +4 -0
@@ -182,6 +182,10 @@ config CPU_SUBTYPE_SH7619 select CPU_SH2 # SH-2A Processor Support +config CPU_SUBTYPE_SH7201 + bool "Support SH7201 processor" + select CPU_SH2A + select CPU_HAS_FPU config CPU_SUBTYPE_SH7203 bool "Support SH7203 processor"
arch/sh/boards/Kconfig +0 -0
arch/sh/include/asm/processor.h +1 -1
@@ -18,7 +18,7 @@ enum cpu_type {CPU_SH7619 ,/* SH-2A types */ -CPU_SH7203 ,CPU_SH7206 ,CPU_SH7263 ,CPU_MXG , +CPU_SH7201 ,CPU_SH7203 ,CPU_SH7206 ,CPU_SH7263 ,CPU_MXG ,/* SH-3 types */ CPU_SH7705, CPU_SH7706, CPU_SH7707,
arch/sh/kernel/cpu/sh2a/Makefile +1 -0
@@ -10,6 +10,7 @@ obj-$(CONFIG_SH_FPU) += fpu.o obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o +obj-$(CONFIG_CPU_SUBTYPE_SH7201) += setup-sh7201.o clock-sh7201.o obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o obj-$(CONFIG_CPU_SUBTYPE_MXG) += setup-mxg.o clock-sh7206.o
arch/sh/kernel/cpu/sh2a/clock-sh7201.c new file +86 -0
86 lines not on this page · raw message
arch/sh/kernel/cpu/sh2a/probe.c +5 -1
@@ -18,7 +18,11 @@ int __init detect_cpu_and_cache_system(void)/* All SH-2A CPUs have support for 16 and 32-bit opcodes.. */ boot_cpu_data.flags |=CPU_HAS_OP32 ; -#if defined(CONFIG_CPU_SUBTYPE_SH7203 ) +#if defined(CONFIG_CPU_SUBTYPE_SH7201 ) + boot_cpu_data.type =CPU_SH7201 ; +/* SH7201 has an FPU.. */ + boot_cpu_data.flags |=CPU_HAS_FPU ; +#elif defined(CONFIG_CPU_SUBTYPE_SH7203 ) boot_cpu_data.type =CPU_SH7203 ;/* SH7203 has an FPU.. */ boot_cpu_data.flags |=CPU_HAS_FPU ;
arch/sh/kernel/cpu/sh2a/setup-sh7201.c new file +331 -0
331 lines not on this page · raw message
arch/sh/kernel/setup.c +1 -0
@@ -417,6 +419,7 @@ void __init setup_arch(char **cmdline_p) }static const char *cpu_name[] = { + [CPU_SH7201 ] ="SH7201" , [CPU_SH7203 ] ="SH7203" , [CPU_SH7263 ] ="SH7263" , [CPU_SH7206 ] ="SH7206" , [CPU_SH7619 ] ="SH7619" , [CPU_SH7705 ] ="SH7705" , [CPU_SH7706 ] ="SH7706" ,
arch/sh/kernel/timers/timer-mtu2.c +5 -0
@@ -34,7 +34,12 @@#define MTU2_TIER_1 0xfffe4384#define MTU2_TSR_1 0xfffe4385#define MTU2_TCNT_1 0xfffe4386/* 16-bit counter */ + +#if defined (CONFIG_CPU_SUBTYPE_SH7201 ) +#define MTU2_TGRA_1 0xfffe4388 +#else #define MTU2_TGRA_1 0xfffe438a +#endif #define STBCR3 0xfffe0408
drivers/serial/sh-sci.h +20 -2
@@ -135,11 +135,18 @@# define SCSCR_INIT (port) 0x3a/* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ #elif defined(CONFIG_CPU_SUBTYPE_SH7203 ) || \ defined(CONFIG_CPU_SUBTYPE_SH7206 ) || \ - defined(CONFIG_CPU_SUBTYPE_SH7263 ) + defined(CONFIG_CPU_SUBTYPE_SH7263 ) || \ + defined(CONFIG_CPU_SUBTYPE_SH7201 )# define SCSPTR0 0xfffe8020/* 16 bit SCIF */ # define SCSPTR1 0xfffe8820/* 16 bit SCIF */ # define SCSPTR2 0xfffe9020/* 16 bit SCIF */ # define SCSPTR3 0xfffe9820/* 16 bit SCIF */ +#if defined(CONFIG_CPU_SUBTYPE_SH7201 ) +# define SCSPTR4 0xfffeA020/* 16 bit SCIF */ +# define SCSPTR5 0xfffeA820/* 16 bit SCIF */ +# define SCSPTR6 0xfffeB020/* 16 bit SCIF */ +# define SCSPTR7 0xfffeB820/* 16 bit SCIF */ +#endif # define SCSCR_INIT (port) 0x38/* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ #elif defined(CONFIG_CPU_SUBTYPE_SH7619 )# define SCSPTR0 0xf8400020/* 16 bit SCIF */
@@ -666,7 +673,8 @@ static inline int sci_rxd_in(struct uart_port *port) }#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \ defined(CONFIG_CPU_SUBTYPE_SH7206) || \ - defined(CONFIG_CPU_SUBTYPE_SH7263) + defined(CONFIG_CPU_SUBTYPE_SH7263) || \ + defined(CONFIG_CPU_SUBTYPE_SH7201)static inline int sci_rxd_in (struct uart_port *port) {if (port->mapbase =0xfffe8000 )
@@ -677,6 +685,16 @@ static inline int sci_rxd_in(struct uart_port *port)return ctrl_inw (SCSPTR2 ) &0x0001 ?1 :0 ;/* SCIF */ if (port->mapbase =0xfffe9800 )return ctrl_inw (SCSPTR3 ) &0x0001 ?1 :0 ;/* SCIF */ +#if defined(CONFIG_CPU_SUBTYPE_SH7201 ) +if (port->mapbase =0xfffeA000 ) +return ctrl_inw (SCSPTR0 ) &0x0001 ?1 :0 ;/* SCIF */ +if (port->mapbase =0xfffeA800 ) +return ctrl_inw (SCSPTR1 ) &0x0001 ?1 :0 ;/* SCIF */ +if (port->mapbase =0xfffeB000 ) +return ctrl_inw (SCSPTR2 ) &0x0001 ?1 :0 ;/* SCIF */ +if (port->mapbase =0xfffeB800 ) +return ctrl_inw (SCSPTR3 ) &0x0001 ?1 :0 ;/* SCIF */ +#endif return 1; }#elif defined(CONFIG_CPU_SUBTYPE_SH7619)