powerpc updates to kvm-userspace

@@ -2,9 +2,6 @@
  * QEMU PowerPC 4xx embedded processors shared devices emulation
  *
  * Copyright (c) 2007 Jocelyn Mayer
- *
- * Copyright 2008 IBM Corp.
- * Authors: Hollis Blanchard <[email protected]>
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal

@@ -29,8 +26,6 @@
 #include "ppc4xx.h"
 #include "sysemu.h"
 #include "qemu-log.h"
-#include "pci.h"
-#include "bswap.h"
 
 //#define DEBUG_MMIO
 //#define DEBUG_UNASSIGNED

@@ -537,369 +532,3 @@ qemu_irq *ppcuic_init (CPUState *env, qe
 
     return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
 }
-
-
-
-
-#define PCIC0_CFGADDR       0x0
-#define PCIC0_CFGDATA       0x4
-
-#define PCIL0_PMM0LA        0x0
-#define PCIL0_PMM0MA        0x4
-#define PCIL0_PMM0PCILA     0x8
-#define PCIL0_PMM0PCIHA     0xc
-#define PCIL0_PMM1LA        0x10
-#define PCIL0_PMM1MA        0x14
-#define PCIL0_PMM1PCILA     0x18
-#define PCIL0_PMM1PCIHA     0x1c
-#define PCIL0_PMM2LA        0x20
-#define PCIL0_PMM2MA        0x24
-#define PCIL0_PMM2PCILA     0x28
-#define PCIL0_PMM2PCIHA     0x2c
-#define PCIL0_PTM1MS        0x30
-#define PCIL0_PTM1LA        0x34
-#define PCIL0_PTM2MS        0x38
-#define PCIL0_PTM2LA        0x3c
-#define PCI_REG_SIZE        0x40
-
-#define PPC44x_PCI_MA_MASK   0xfffff000
-#define PPC44x_PCI_MA_ENABLE 0x1
-
-
-static uint32_t pci4xx_cfgaddr_read4(void *opaque, target_phys_addr_t addr)
-{
-    ppc4xx_pci_t *ppc4xx_pci = opaque;
-    return cpu_to_le32(ppc4xx_pci->pcic0_cfgaddr);
-}
-
-static CPUReadMemoryFunc *pci4xx_cfgaddr_read[] = {
-    &pci4xx_cfgaddr_read4,
-    &pci4xx_cfgaddr_read4,
-    &pci4xx_cfgaddr_read4,
-};
-
-static void pci4xx_cfgaddr_write4(void *opaque, target_phys_addr_t addr,
-                                  uint32_t value)
-{
-    ppc4xx_pci_t *ppc4xx_pci = opaque;
-
-    value = le32_to_cpu(value);
-
-    ppc4xx_pci->pcic0_cfgaddr = value & ~0x3;
-}
-
-static CPUWriteMemoryFunc *pci4xx_cfgaddr_write[] = {
-    &pci4xx_cfgaddr_write4,
-    &pci4xx_cfgaddr_write4,
-    &pci4xx_cfgaddr_write4,
-};
-
-static uint32_t pci4xx_cfgdata_read1(void *opaque, target_phys_addr_t addr)
-{
-    ppc4xx_pci_t *ppc4xx_pci = opaque;
-    int offset = addr & 0x3;
-    uint32_t cfgaddr = ppc4xx_pci->pcic0_cfgaddr;
-    uint32_t value;
-
-    if (!(cfgaddr & (1<<31)))
-        return 0xffffffff;
-
-    value = pci_data_read(ppc4xx_pci->bus, cfgaddr | offset, 1);
-
-    return value;
-}
-
-static uint32_t pci4xx_cfgdata_read2(void *opaque, target_phys_addr_t addr)
-{
-    ppc4xx_pci_t *ppc4xx_pci = opaque;
-    int offset = addr & 0x3;
-    uint32_t cfgaddr = ppc4xx_pci->pcic0_cfgaddr;
-    uint32_t value;
-
-    if (!(cfgaddr & (1<<31)))
-        return 0xffffffff;
-
-    value = pci_data_read(ppc4xx_pci->bus, cfgaddr | offset, 2);
-
-    return cpu_to_le16(value);
-}
-
-static uint32_t pci4xx_cfgdata_read4(void *opaque, target_phys_addr_t addr)
-{
-    ppc4xx_pci_t *ppc4xx_pci = opaque;
-    int offset = addr & 0x3;
-    uint32_t cfgaddr = ppc4xx_pci->pcic0_cfgaddr;
-    uint32_t value;
-
-    if (!(cfgaddr & (1<<31)))
-        return 0xffffffff;
-
-    value = pci_data_read(ppc4xx_pci->bus, cfgaddr | offset, 4);
-
-    return cpu_to_le32(value);
-}
-
-static CPUReadMemoryFunc *pci4xx_cfgdata_read[] = {
-    &pci4xx_cfgdata_read1,
-    &pci4xx_cfgdata_read2,
-    &pci4xx_cfgdata_read4,
-};
-
-static void pci4xx_cfgdata_write1(void *opaque, target_phys_addr_t addr,
-                                  uint32_t value)
-{
-    ppc4xx_pci_t *ppc4xx_pci = opaque;
-    int offset = addr & 0x3;
-
-    pci_data_write(ppc4xx_pci->bus, ppc4xx_pci->pcic0_cfgaddr | offset,
-                   value, 1);
-}
-
-static void pci4xx_cfgdata_write2(void *opaque, target_phys_addr_t addr,
-                                  uint32_t value)
-{
-    ppc4xx_pci_t *ppc4xx_pci = opaque;
-    int offset = addr & 0x3;
-
-    value = le16_to_cpu(value);
-
-    pci_data_write(ppc4xx_pci->bus, ppc4xx_pci->pcic0_cfgaddr | offset,
-                   value, 2);
-}
-
-static void pci4xx_cfgdata_write4(void *opaque, target_phys_addr_t addr,
-                                  uint32_t value)
-{
-    ppc4xx_pci_t *ppc4xx_pci = opaque;
-    int offset = addr & 0x3;
-
-    value = le32_to_cpu(value);
-
-    pci_data_write(ppc4xx_pci->bus, ppc4xx_pci->pcic0_cfgaddr | offset,
-                   value, 4);
-}
-
-static CPUWriteMemoryFunc *pci4xx_cfgdata_write[] = {
-    &pci4xx_cfgdata_write1,
-    &pci4xx_cfgdata_write2,
-    &pci4xx_cfgdata_write4,
-};
-
-static void pci_reg_write4(void *opaque, target_phys_addr_t addr,
-                           uint32_t value)
-{
-    struct ppc4xx_pci_t *pci = opaque;
-    unsigned long offset = addr - pci->registers;
-
-    value = le32_to_cpu(value);
-
-    switch (offset) {
-    case PCIL0_PMM0LA:
-        pci->pmm[0].la = value;
-        break;
-    case PCIL0_PMM1LA:
-        pci->pmm[0].la = value;
-        break;
-    case PCIL0_PMM2LA:
-        pci->pmm[0].la = value;
-        break;
-    default:
-        //printf("  unhandled PCI internal register 0x%lx\n", offset);
-        break;
-    }
-}
-
-static uint32_t pci_reg_read4(void *opaque, target_phys_addr_t addr)
-{
-    struct ppc4xx_pci_t *pci = opaque;
-    unsigned long offset = addr - pci->registers;
-    uint32_t value;
-
-    switch (offset) {
-    case PCIL0_PMM0LA:
-        value = pci->pmm[0].la;
-        break;
-    case PCIL0_PMM0MA:
-        value = pci->pmm[0].ma;
-        break;
-    case PCIL0_PMM0PCIHA:
-        value = pci->pmm[0].pciha;
-        break;
-    case PCIL0_PMM0PCILA:
-        value = pci->pmm[0].pcila;
-        break;
-
-    case PCIL0_PMM1LA:
-        value = pci->pmm[1].la;
-        break;
-    case PCIL0_PMM1MA:
-        value = pci->pmm[1].ma;
-        break;
-    case PCIL0_PMM1PCIHA:
-        value = pci->pmm[1].pciha;
-        break;
-    case PCIL0_PMM1PCILA:
-        value = pci->pmm[1].pcila;
-        break;
-
-    case PCIL0_PMM2LA:
-        value = pci->pmm[2].la;
-        break;
-    case PCIL0_PMM2MA:
-        value = pci->pmm[2].ma;
-        break;
-    case PCIL0_PMM2PCIHA:
-        value = pci->pmm[2].pciha;
-        break;
-    case PCIL0_PMM2PCILA:
-        value = pci->pmm[2].pcila;
-        break;
-
-    case PCIL0_PTM1MS:
-        value = pci->ptm[0].ms;
-        break;
-    case PCIL0_PTM1LA:
-        value = pci->ptm[0].la;
-        break;
-    case PCIL0_PTM2MS:
-        value = pci->ptm[1].ms;
-        break;
-    case PCIL0_PTM2LA:
-        value = pci->ptm[1].la;
-        break;
-
-    default:
-        //printf("  read from invalid PCI internal register 0x%lx\n", offset);
-        value = 0;
-    }
-
-    value = cpu_to_le32(value);
-
-    return value;
-}
-
-static CPUReadMemoryFunc *pci_reg_read[] = {
-    &pci_reg_read4,
-    &pci_reg_read4,
-    &pci_reg_read4,
-};
-
-static CPUWriteMemoryFunc *pci_reg_write[] = {
-    &pci_reg_write4,
-    &pci_reg_write4,
-    &pci_reg_write4,
-};
-
-static uint32_t pci_int_ack_read4(void *opaque, target_phys_addr_t addr)
-{
-    printf("%s\n", __func__);
-    return 0;
-}
-
-static CPUReadMemoryFunc *pci_int_ack_read[] = {
-    &pci_int_ack_read4,
-    &pci_int_ack_read4,
-    &pci_int_ack_read4,
-};
-
-static void pci_special_write4(void *opaque, target_phys_addr_t addr,
-                               uint32_t value)
-{
-    printf("%s\n", __func__);
-}
-
-static CPUWriteMemoryFunc *pci_special_write[] = {
-    &pci_special_write4,
-    &pci_special_write4,
-    &pci_special_write4,
-};
-
-static int bamboo_pci_map_irq(PCIDevice *pci_dev, int irq_num)
-{
-    int slot = pci_dev->devfn >> 3;
-
-#if 0
-    printf("### %s: devfn %x irq %d -> %d\n", __func__,
-           pci_dev->devfn, irq_num, slot+1);
-#endif
-
-    /* All pins from each slot are tied to a single board IRQ (2-5) */
-    return slot + 1;
-}
-
-static void bamboo_pci_set_irq(qemu_irq *pic, int irq_num, int level)
-{
-#if 0
-    printf("### %s: PCI irq %d, UIC irq %d\n", __func__, irq_num, 30 - irq_num);
-#endif
-
-    /* Board IRQs 2-5 are connected to UIC IRQs 28-25 */
-    qemu_set_irq(pic[30-irq_num], level);
-}
-
-/* XXX Needs some abstracting for boards other than Bamboo. */
-ppc4xx_pci_t *ppc4xx_pci_init(CPUState *env, qemu_irq *pic,
-                              target_phys_addr_t config_space,
-                              target_phys_addr_t int_ack,
-                              target_phys_addr_t special_cycle,
-                              target_phys_addr_t registers)
-{
-    ppc4xx_pci_t *pci;
-    PCIDevice *d;
-    int index;
-
-    pci = qemu_mallocz(sizeof(ppc4xx_pci_t));
-    if (!pci)
-        return NULL;
-
-    pci->config_space = config_space;
-    pci->registers = registers;
-    pci->pic = pic;
-
-    pci->bus = pci_register_bus(bamboo_pci_set_irq, bamboo_pci_map_irq,
-                                pic, 0, 4);
-    d = pci_register_device(pci->bus, "host bridge", sizeof(PCIDevice),
-                            0, NULL, NULL);
-    d->config[0x00] = 0x14; // vendor_id
-    d->config[0x01] = 0x10;
-    d->config[0x02] = 0x7f; // device_id
-    d->config[0x03] = 0x02;
-    d->config[0x0a] = 0x80; // class_sub = other bridge type
-    d->config[0x0b] = 0x06; // class_base = PCI_bridge
-
-    /* CFGADDR */
-    index = cpu_register_io_memory(0, pci4xx_cfgaddr_read,
-                                   pci4xx_cfgaddr_write, pci);
-    if (index < 0)
-        goto free;
-    cpu_register_physical_memory(config_space, 4, index);
-
-    /* CFGDATA */
-    index = cpu_register_io_memory(0, pci4xx_cfgdata_read,
-                                   pci4xx_cfgdata_write, pci);
-    if (index < 0)
-        goto free;
-    cpu_register_physical_memory(config_space + 4, 4, index);
-
-    /* "Special cycle" and interrupt acknowledge */
-    index = cpu_register_io_memory(0, pci_int_ack_read,
-                                   pci_special_write, pci);
-    if (index < 0)
-        goto free;
-    cpu_register_physical_memory(int_ack, 4, index);
-
-    /* Internal registers */
-    index = cpu_register_io_memory(0, pci_reg_read, pci_reg_write, pci);
-    if (index < 0)
-        goto free;
-    cpu_register_physical_memory(registers, PCI_REG_SIZE, index);
-
-    /* XXX register_savevm() */
-
-    return pci;
-
-free:
-    printf("%s error\n", __func__);
-    qemu_free(pci);
-    return NULL;
-}

@@ -19,6 +19,7 @@
 #include "ppc440.h"
 #include "qemu-kvm.h"
 #include "device_tree.h"
+#include "virtio-blk.h"
 
 #define BINARY_DEVICE_TREE_FILE "bamboo.dtb"
 

@@ -31,7 +31,7 @@ extern kvm_context_t kvm_context;
 
 void cpu_reset(CPUState *env)
 {
-	memset(env->breakpoints, 0, sizeof(env->breakpoints));
+	memset(env, 0, offsetof(CPUPPCState, breakpoints));
 	cpu_ppc_reset(env);
 }
 

@@ -13,6 +13,7 @@
 #include "hw.h"
 #include "hw/isa.h"
 #include "ppc440.h"
+#include "pci.h"
 
 #define PPC440EP_PCI_CONFIG 0xeec00000
 #define PPC440EP_PCI_INTACK 0xeed00000

@@ -29,12 +30,12 @@ void ppc440ep_init(CPUState *env,
 		target_phys_addr_t ram_sizes[PPC440_MAX_RAM_SLOTS],
 		int nbanks,
 		qemu_irq **picp,
-		ppc4xx_pci_t **pcip,
+		PCIBus **pcibusp,
 		int do_init)
 {
 	ppc4xx_mmio_t *mmio;
 	qemu_irq *pic, *irqs;
-	ppc4xx_pci_t *pci;
+	PCIBus *pcibus;
 	int i;
 
 	ppc_dcr_init(env, NULL, NULL);

@@ -59,14 +60,14 @@ void ppc440ep_init(CPUState *env,
 	ppc405_sdram_init(env, pic[14], nbanks, ram_bases, ram_sizes, do_init);
 
 	/* PCI */
-	pci = ppc4xx_pci_init(env, pic,
+	pcibus = ppc4xx_pci_init(env, pic,
 	                      PPC440EP_PCI_CONFIG,
 	                      PPC440EP_PCI_INTACK,
 	                      PPC440EP_PCI_SPECIAL,
 	                      PPC440EP_PCI_REGS);
-	if (!pci)
+	if (!pcibus)
 		printf("couldn't create PCI controller!\n");
-	*pcip = pci;
+	*pcibusp = pcibus;
 
 	isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN);
 

@@ -20,6 +20,7 @@
 #include "sysemu.h"
 #include "exec-all.h"
 #include "boards.h"
+#include "pci.h"
 
 #define PPC440_MAX_RAM_SLOTS 4
 

@@ -28,7 +29,7 @@ void ppc440ep_init(CPUState *env,
 		target_phys_addr_t ram_sizes[PPC440_MAX_RAM_SLOTS],
 		int nbanks,
 		qemu_irq **picp,
-		ppc4xx_pci_t **pcip,
+		PCIBus **pcip,
 		int do_init);
 
 #endif

@@ -37,7 +37,7 @@ void bamboo_init(ram_addr_t ram_size, in
 	target_phys_addr_t ram_sizes[PPC440_MAX_RAM_SLOTS];
 	NICInfo *nd;
 	qemu_irq *pic;
-	ppc4xx_pci_t *pci;
+	PCIBus *pcibus;
 	CPUState *env;
     uint64_t elf_entry;
     uint64_t elf_lowaddr;

@@ -102,7 +102,7 @@ void bamboo_init(ram_addr_t ram_size, in
 
 	/* call init */
 	printf("Calling function ppc440_init\n");
-	ppc440ep_init(env, ram_bases, ram_sizes, nbanks, &pic, &pci, 1);
+	ppc440ep_init(env, ram_bases, ram_sizes, nbanks, &pic, &pcibus, 1);
 	printf("Done calling ppc440_init\n");
 
 	/* load kernel with uboot loader */

@@ -197,12 +197,12 @@ void bamboo_init(ram_addr_t ram_size, in
 		env->nip = entry;
 	}
 
-	if (pci) {
+	if (pcibus) {
 		int unit_id = 0;
 
 		/* Add virtio block devices. */
 		while ((i = drive_get_index(IF_VIRTIO, 0, unit_id)) != -1) {
-			virtio_blk_init(pci->bus, 0x1AF4, 0x1001,
+			virtio_blk_init(pcibus, 0x1AF4, 0x1001,
 				drives_table[i].bdrv);
 			unit_id++;
 		}

@@ -212,7 +212,7 @@ void bamboo_init(ram_addr_t ram_size, in
 			nd = &nd_table[i];
 			if (!nd->model)
 				nd->model = "virtio";
-			pci_nic_init(pci->bus, nd, -1);
+			pci_nic_init(pcibus, nd, -1);
 		}
 	}