Aspeed AST2400 BMC support

Hello!

These patches add basic support for the Aspeed AST2400 SoC, a popular BMC device that is also the target for our OpenBMC[1] efforts.

This series have been boot tested on a Palmetto; an OpenPower dev board that uses the ast2400 as it's BMC, as well as Qemu (-M palmetto-bmc on 2.6-rc1).

Cheers,

Joel

[1] https://lwn.net/Articles/683320/

Benjamin Herrenschmidt (1):
irqchip: Add irq controller for Aspeed

Joel Stanley (8):
doc/devicetree: Add Aspeed and Tyan to vendor-prefixes doc/devicetree: Add Aspeed VIC bindings doc/devicetree: Add Aspeed clock bindings clocksource/moxart: Generalise timer for use on other socs drivers/clk: Add Aspeed clock driver
arm/dts: Add aspeed device trees
arm: Add Aspeed AST2400 machine
arm/configs: Add aspeed defconfig

 .../devicetree/bindings/clock/aspeed-clock.txt     |  44 ++++
 .../interrupt-controller/aspeed,ast2400-vic.txt    |  24 +++
 .../bindings/timer/moxa,moxart-timer.txt           |   4 +-
 .../devicetree/bindings/vendor-prefixes.txt        |   2 +
 MAINTAINERS                                        |   8 +
 arch/arm/Kconfig                                   |   2 +
 arch/arm/Makefile                                  |   1 +
 arch/arm/boot/dts/Makefile                         |   3 +
 arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts      |  21 ++
 arch/arm/boot/dts/ast2400.dtsi                     | 152 +++++++++++++
 arch/arm/configs/aspeed_defconfig                  |  86 ++++++++
 arch/arm/mach-aspeed/Kconfig                       |  19 ++
 arch/arm/mach-aspeed/Makefile                      |   3 +
 arch/arm/mach-aspeed/aspeed.c                      |  80 +++++++
 arch/arm/mach-aspeed/ast2400.h                     | 117 ++++++++++
 drivers/clk/Makefile                               |   1 +
 drivers/clk/clk-aspeed.c                           | 106 +++++++++
 drivers/clocksource/Kconfig                        |   6 +
 drivers/clocksource/Makefile                       |   2 +-
 drivers/clocksource/moxart_timer.c                 |  90 ++++++--
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-aspeed-vic.c                   | 238 +++++++++++++++++++++
 22 files changed, 987 insertions(+), 23 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/aspeed-clock.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt
 create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
 create mode 100644 arch/arm/boot/dts/ast2400.dtsi
 create mode 100644 arch/arm/configs/aspeed_defconfig
 create mode 100644 arch/arm/mach-aspeed/Kconfig
 create mode 100644 arch/arm/mach-aspeed/Makefile
 create mode 100644 arch/arm/mach-aspeed/aspeed.c
 create mode 100644 arch/arm/mach-aspeed/ast2400.h
 create mode 100644 drivers/clk/clk-aspeed.c
 create mode 100644 drivers/irqchip/irq-aspeed-vic.c

2.7.4

ASPEED Technology Inc is a fabless IC-design company. Their web site is http://www.aspeedtech.com/.

Tyan is a manufactuer of server and workstation platforms.

---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 2 ++
 1 file changed, 2 insertions(+)

index 86740d4a270d..192843189ceb 100644
@@ -29,6 +29,7 @@ arm	ARM Ltd.
 armadeus	ARMadeus Systems SARL
 artesyn	Artesyn Embedded Technologies Inc.
 asahi-kasei	Asahi Kasei Corp.
+aspeed	ASPEED Technology Inc.
 atlas	Atlas Scientific LLC
 atmel	Atmel Corporation
 auo	AU Optronics Corporation

@@ -250,6 +251,7 @@ tplink	TP-LINK Technologies Co., Ltd.
 tronfy	Tronfy
 tronsmart	Tronsmart
 truly	Truly Semiconductors Limited
+tyan	Tyan Computer Corporation
 upisemi	uPI Semiconductor Corp.
 urt	United Radiant Technology Corporation
 usi	Universal Scientific Industrial Co., Ltd.

2.7.4

---
 .../interrupt-controller/aspeed,ast2400-vic.txt    | 24 ++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt

new file mode 100644
index 000000000000..10ed0c20ee6f
@@ -0,0 +1,24 @@
+Aspeed Vectored Interrupt Controller
+
+These bindings are for the Aspeed AST2400 interrupt controller register layout.
+The SoC has an legacy register layout, but this driver does not support that
+mode of operation.
+
+Required properties:
+
+- compatible : should be "aspeed,ast2400-vic".
+
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 1.
+- valid-sources : bitmask of valid irq sources
+
+Example:
+
+ vic: interrupt-controller {
+      compatible = "aspeed,ast2400-new-vic";
+      interrupt-controller;
+      #interrupt-cells = <1>;
+      valid-sources = < 0xffffffff 0x0007ffff>;
+      reg = <0x1e6c0080 0x80>;
+ };

2.7.4

---
 .../devicetree/bindings/clock/aspeed-clock.txt     | 44 ++++++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/aspeed-clock.txt

new file mode 100644
index 000000000000..4259f0986739
@@ -0,0 +1,44 @@
+Device Tree Clock bindings for the Aspeed AST2400
+
+Aspeed SoCs have a fixed frequency input osciallator is usd to create the PLL
+and APB clocks. We can determine these frequencies by reading registers that
+are set according to strapping bits.
+
+PLL:
+
+Required properties:
+- compatible : Must be "aspeed,ast2400-pll-clock"
+- #clock-cells : Should be 0
+- reg : Should contain registers location and length
+- clocks : Should contain phandle + clock-specifier for the input clock
+
+Optional properties:
+- clock-output-names : Should contain clock name
+
+
+APB:
+
+Required properties:
+- compatible : Must be "aspeed,ast2400-apb-clock"
+- #clock-cells : Should be 0
+- reg : Should contain registers location and length
+- clocks : Should contain phandle + clock-specifier for the the pll
+
+Optional properties:
+- clock-output-names : Should contain clock name
+
+
+For example:
+
+	clk_hpll: clk_hpll {
+		compatible = "aspeed,ast2400-pll-clock";
+		#clock-cells = <0>;
+		reg = <0x1e6e2008 0x4>;
+	};
+
+	clk_apb: clk_apb at 1e6e2008 {
+		#clock-cells = <0>;
+		compatible = "aspeed,ast2400-apb-clock";
+		reg = <0x1e6e2008 0x4>;
+		clocks = <&clk_hpll>;
+	};

2.7.4

The moxart timer IP is shared with another soc made by Aspeed. Generalise the registers that differ so the same driver can be used for both.

As we now depend on CLKSRC_MMIO, create a Kconfig symbol for the driver so we can express this dependency.

---
 .../bindings/timer/moxa,moxart-timer.txt           |  4 +-
 drivers/clocksource/Kconfig                        |  6 ++
 drivers/clocksource/Makefile                       |  2 +-
 drivers/clocksource/moxart_timer.c                 | 90 +++++++++++++++++-----
 4 files changed, 79 insertions(+), 23 deletions(-)

index da2d510cae47..4569757142f8 100644
@@ -2,7 +2,9 @@ MOXA ART timer
 
 Required properties:
 
-- compatible : Must be "moxa,moxart-timer"
+- compatible : Must be one of
+     - "moxa,moxart-timer"
+     - "aspeed,ast2400-timer"
 - reg : Should contain registers location and length
 - interrupts : Should contain the timer interrupt number
 - clocks : Should contain phandle for the clock that drives the counter

index c346be650892..b14ac4db6961 100644
@@ -411,4 +411,10 @@ config CLKSRC_ST_LPC
 	  Enable this option to use the Low Power controller timer
 	  as clocksource.
 
+config MOXART_TIMER
+	def_bool ARCH_MOXART || ARCH_ASPEED
+	depends on ARM && OF
+	select CLKSRC_OF
+	select CLKSRC_MMIO
+
 endmenu

index dc2b8997f6e6..14fe8172c174 100644
@@ -22,7 +22,7 @@ obj-$(CONFIG_ORION_TIMER)	+= time-orion.o
 obj-$(CONFIG_ARCH_BCM2835)	+= bcm2835_timer.o
 obj-$(CONFIG_ARCH_CLPS711X)	+= clps711x-timer.o
 obj-$(CONFIG_ARCH_ATLAS7)	+= timer-atlas7.o
-obj-$(CONFIG_ARCH_MOXART)	+= moxart_timer.o
+obj-$(CONFIG_MOXART_TIMER)	+= moxart_timer.o
 obj-$(CONFIG_ARCH_MXS)		+= mxs_timer.o
 obj-$(CONFIG_CLKSRC_PXA)	+= pxa_timer.o
 obj-$(CONFIG_ARCH_PRIMA2)	+= timer-prima2.o

2.7.4

From: Benjamin Herrenschmidt <[email protected]>

---
 drivers/irqchip/Makefile         |   1 +
 drivers/irqchip/irq-aspeed-vic.c | 238 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 239 insertions(+)
 create mode 100644 drivers/irqchip/irq-aspeed-vic.c

index b03cfcbbac6b..ec82e6e15a38 100644
@@ -65,3 +65,4 @@ obj-$(CONFIG_INGENIC_IRQ)		+= irq-ingenic.o
 obj-$(CONFIG_IMX_GPCV2)			+= irq-imx-gpcv2.o
 obj-$(CONFIG_PIC32_EVIC)		+= irq-pic32-evic.o
 obj-$(CONFIG_MVEBU_ODMI)		+= irq-mvebu-odmi.o
+obj-$(CONFIG_ARCH_ASPEED)		+= irq-aspeed-vic.o

2.7.4

A simple driver to create fixed rate clock devices for the host pll and peripheral clock.

---
 drivers/clk/Makefile     |   1 +
 drivers/clk/clk-aspeed.c | 106 +++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 107 insertions(+)
 create mode 100644 drivers/clk/clk-aspeed.c

index 46869d696e4d..b375d10a9423 100644
@@ -84,3 +84,4 @@ obj-$(CONFIG_X86)			+= x86/
 obj-$(CONFIG_ARCH_ZX)			+= zte/
 obj-$(CONFIG_ARCH_ZYNQ)			+= zynq/
 obj-$(CONFIG_H8300)		+= h8300/
+obj-$(CONFIG_ARCH_ASPEED)		+= clk-aspeed.o

2.7.4

A common device tree, and a board specific dts for the Palmetto OpenPower developemnt machine which was used for testing.

---
 arch/arm/boot/dts/Makefile                    |   3 +
 arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts |  21 ++++
 arch/arm/boot/dts/ast2400.dtsi                | 152 ++++++++++++++++++++++++++
 3 files changed, 176 insertions(+)
 create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
 create mode 100644 arch/arm/boot/dts/ast2400.dtsi

index 95c1923ce6fa..0600a7f58e8a 100644
@@ -839,6 +839,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
 	mt8127-moose.dtb \
 	mt8135-evbp1.dtb
 dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
+dtb-$(CONFIG_ARCH_ASPEED) += aspeed-bmc-opp-palmetto.dtb \
+	aspeed-bmc-opp-barreleye.dtb \
+	aspeed-bmc-opp-firestone.dtb
 endif
 
 dtstree		:= $(srctree)/$(src)

new file mode 100644
index 000000000000..5caa7a1b55d2
@@ -0,0 +1,21 @@
+/dts-v1/;
+
+#include "ast2400.dtsi"
+
+/ {
+	model = "Palmetto BMC";
+	compatible = "tyan,palmetto-bmc", "aspeed,ast2400";
+
+	chosen {
+		stdout-path = &uart5;
+		bootargs = "console=ttyS4,38400";
+	};
+
+	memory {
+		reg = < 0x40000000 0x10000000 >;
+	};
+};
+
+&uart5 {
+	status = "okay";
+};

2.7.4

The Apseed AST2400 is a common Baseboard Management Controller (BMC) system on chip containing an ARM9 core, off-chip DDR RAM and support for a large number of peripherals.

This patch dds basic support for the ast2400, capable of booting to a prompt in QEMU (-M palmetto-bmc) or on an Palmetto OpenPower development machine.

---
 MAINTAINERS                    |   8 +++
 arch/arm/Kconfig               |   2 +
 arch/arm/Makefile              |   1 +
 arch/arm/mach-aspeed/Kconfig   |  19 +++++++
 arch/arm/mach-aspeed/Makefile  |   3 ++
 arch/arm/mach-aspeed/aspeed.c  |  80 ++++++++++++++++++++++++++++
 arch/arm/mach-aspeed/ast2400.h | 117 +++++++++++++++++++++++++++++++++++++++++
 7 files changed, 230 insertions(+)
 create mode 100644 arch/arm/mach-aspeed/Kconfig
 create mode 100644 arch/arm/mach-aspeed/Makefile
 create mode 100644 arch/arm/mach-aspeed/aspeed.c
 create mode 100644 arch/arm/mach-aspeed/ast2400.h

index 61a323a6b2cf..d0a1962f7753 100644
@@ -975,6 +975,14 @@ F:	arch/arm/mach-artpec
 F:	arch/arm/boot/dts/artpec6*
 F:	drivers/clk/clk-artpec6.c
 
+ARM/ASPEED MACHINE SUPPORT
+M:	Joel Stanley <[email protected]>
+S:	Maintained
+F:	arch/arm/mach-aspeed/
+F:	arch/arm/boot/dts/aspeed-*
+F:	arch/arm/boot/dts/ast2400.dtsi
+F:	drivers/*/*aspeed*
+
 ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT
 M:	Nicolas Ferre <[email protected]>
 M:	Alexandre Belloni <[email protected]>

index cdfa6c2b7626..c4512f6b77f6 100644
@@ -775,6 +775,8 @@ source "arch/arm/mach-meson/Kconfig"
 
 source "arch/arm/mach-moxart/Kconfig"
 
+source "arch/arm/mach-aspeed/Kconfig"
+
 source "arch/arm/mach-mv78xx0/Kconfig"
 
 source "arch/arm/mach-imx/Kconfig"

index 8c3ce2ac44c4..8ab09fb78e1c 100644
@@ -184,6 +184,7 @@ machine-$(CONFIG_ARCH_LPC32XX)		+= lpc32xx
 machine-$(CONFIG_ARCH_MESON)		+= meson
 machine-$(CONFIG_ARCH_MMP)		+= mmp
 machine-$(CONFIG_ARCH_MOXART)		+= moxart
+machine-$(CONFIG_ARCH_ASPEED)		+= aspeed
 machine-$(CONFIG_ARCH_MV78XX0)		+= mv78xx0
 machine-$(CONFIG_ARCH_MVEBU)		+= mvebu
 machine-$(CONFIG_ARCH_MXC)		+= imx

new file mode 100644
index 000000000000..9437015222b1
@@ -0,0 +1,19 @@
+menuconfig ARCH_ASPEED
+	bool "ASpeed BMC SoCs" if ARCH_MULTI_V5
+	select CPU_ARM926T
+	select OF
+	select SRAM
+	help
+	  Say Y here if you want to run your kernel on hardware with an
+	  ASpeed BMC SoC.
+
+if ARCH_ASPEED
+
+config MACH_OPP_PALMETTO_BMC
+	bool "OpenPower Palmetto"
+	depends on ARCH_ASPEED
+	help
+	  Say Y here if you intend to run this kernel on the BMC
+	  of an OpenPower "Palmetto" eval board
+
+endif

new file mode 100644
index 000000000000..3a4f025dd520
@@ -0,0 +1,3 @@
+# Object file lists.
+
+obj-$(CONFIG_ARCH_ASPEED)	+= aspeed.o

2.7.4

---
 arch/arm/configs/aspeed_defconfig | 86 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 86 insertions(+)
 create mode 100644 arch/arm/configs/aspeed_defconfig

new file mode 100644
index 000000000000..eb6f413dac50
@@ -0,0 +1,86 @@
+CONFIG_KERNEL_XZ=y
+CONFIG_SYSVIPC=y
+CONFIG_USELIB=y
+CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_RD_LZ4 is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_BPF_SYSCALL=y
+# CONFIG_SHMEM is not set
+# CONFIG_AIO is not set
+CONFIG_EMBEDDED=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+CONFIG_CC_STACKPROTECTOR_STRONG=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLOCK is not set
+# CONFIG_ARCH_MULTI_V7 is not set
+CONFIG_ARCH_ASPEED=y
+CONFIG_MACH_OPP_PALMETTO_BMC=y
+CONFIG_DEBUG_RODATA=y
+CONFIG_AEABI=y
+CONFIG_UACCESS_WITH_MEMCPY=y
+CONFIG_SECCOMP=y
+# CONFIG_ATAGS is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_KEXEC=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_RUNTIME_UARTS=6
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_FIRMWARE_MEMMAP=y
+CONFIG_FANOTIFY=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_PAGE_POISONING=y
+CONFIG_DEBUG_KMEMLEAK=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_WQ_WATCHDOG=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_SCHED_STACK_END_CHECK=y
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y
+# CONFIG_FTRACE is not set
+CONFIG_MEMTEST=y
+CONFIG_UBSAN=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_UART_8250=y
+CONFIG_DEBUG_UART_PHYS=0x1e784000
+CONFIG_DEBUG_UART_VIRT=0xe8784000
+CONFIG_EARLY_PRINTK=y
+CONFIG_DEBUG_SET_MODULE_RONX=y
+# CONFIG_XZ_DEC_X86 is not set
+# CONFIG_XZ_DEC_POWERPC is not set
+# CONFIG_XZ_DEC_IA64 is not set
+# CONFIG_XZ_DEC_SPARC is not set

2.7.4

Hello!

These patches add basic support for the Aspeed AST2400 SoC, a popular BMC device that is also the target for our OpenBMC[1] efforts.

This series has been boot tested on a Palmetto OpenPower dev board that uses the ast2400 as it's BMC, as well as Qemu (-M palmetto-bmc on 2.6-rc1).

Version two brings support for the AST2500. It's similar to the 2400, but with an ARM11 replacing the ARM9. I've boot tested it in Qemu and on the Aspeed AST2500 edk.

Cheers,

Joel

[1] https://lwn.net/Articles/683320/

Benjamin Herrenschmidt (1):
irqchip: Add irq controller for Aspeed

Joel Stanley (10):
doc/devicetree: Add Aspeed and Tyan to vendor-prefixes doc/devicetree: Add Aspeed VIC bindings doc/devicetree: Add Aspeed clock bindings clocksource/moxart: Generalise timer for use on other socs
clk: Add driver for Aspeed fourth gen SoCs
clk: Add driver for Aspeed fifth gen SoCs arm/dts: Add Aspeed ast2400 device tree
arm/dst: Add Aspeed ast2500 device tree
arm: Add Aspeed machine
arm/configs: Add aspeed defconfig

 .../devicetree/bindings/clock/aspeed-clock.txt     | 137 ++++++++++++
 .../interrupt-controller/aspeed,ast2400-vic.txt    |  24 +++
 .../bindings/timer/moxa,moxart-timer.txt           |   4 +-
 .../devicetree/bindings/vendor-prefixes.txt        |   2 +
 MAINTAINERS                                        |   8 +
 arch/arm/Kconfig                                   |   2 +
 arch/arm/Makefile                                  |   1 +
 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/aspeed-ast2500-evb.dts           |  21 ++
 arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts      |  21 ++
 arch/arm/boot/dts/aspeed-g4.dtsi                   | 152 +++++++++++++
 arch/arm/boot/dts/aspeed-g5.dtsi                   | 156 ++++++++++++++
 arch/arm/configs/aspeed_g4_defconfig               |  86 ++++++++
 arch/arm/configs/aspeed_g5_defconfig               |  88 ++++++++
 arch/arm/mach-aspeed/Kconfig                       |  28 +++
 arch/arm/mach-aspeed/Makefile                      |   3 +
 arch/arm/mach-aspeed/aspeed.c                      |  83 +++++++
 drivers/clk/Makefile                               |   1 +
 drivers/clk/clk-aspeed-g4.c                        | 106 +++++++++
 drivers/clk/clk-aspeed-g5.c                        | 189 ++++++++++++++++
 drivers/clocksource/Kconfig                        |   6 +
 drivers/clocksource/Makefile                       |   2 +-
 drivers/clocksource/moxart_timer.c                 |  90 ++++++--
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-aspeed-vic.c                   | 238 +++++++++++++++++++++
 25 files changed, 1428 insertions(+), 23 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/aspeed-clock.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt
 create mode 100644 arch/arm/boot/dts/aspeed-ast2500-evb.dts
 create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
 create mode 100644 arch/arm/boot/dts/aspeed-g4.dtsi
 create mode 100644 arch/arm/boot/dts/aspeed-g5.dtsi
 create mode 100644 arch/arm/configs/aspeed_g4_defconfig
 create mode 100644 arch/arm/configs/aspeed_g5_defconfig
 create mode 100644 arch/arm/mach-aspeed/Kconfig
 create mode 100644 arch/arm/mach-aspeed/Makefile
 create mode 100644 arch/arm/mach-aspeed/aspeed.c
 create mode 100644 drivers/clk/clk-aspeed-g4.c
 create mode 100644 drivers/clk/clk-aspeed-g5.c
 create mode 100644 drivers/irqchip/irq-aspeed-vic.c

2.7.4

ASPEED Technology Inc is a fabless IC-design company. Their web site is http://www.aspeedtech.com/.

Tyan is a manufactuer of server and workstation platforms.

---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 2 ++
 1 file changed, 2 insertions(+)

index 86740d4a270d..192843189ceb 100644
@@ -29,6 +29,7 @@ arm	ARM Ltd.
 armadeus	ARMadeus Systems SARL
 artesyn	Artesyn Embedded Technologies Inc.
 asahi-kasei	Asahi Kasei Corp.
+aspeed	ASPEED Technology Inc.
 atlas	Atlas Scientific LLC
 atmel	Atmel Corporation
 auo	AU Optronics Corporation

@@ -250,6 +251,7 @@ tplink	TP-LINK Technologies Co., Ltd.
 tronfy	Tronfy
 tronsmart	Tronsmart
 truly	Truly Semiconductors Limited
+tyan	Tyan Computer Corporation
 upisemi	uPI Semiconductor Corp.
 urt	United Radiant Technology Corporation
 usi	Universal Scientific Industrial Co., Ltd.

2.7.4

---
 .../interrupt-controller/aspeed,ast2400-vic.txt    | 24 ++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt

new file mode 100644
index 000000000000..10ed0c20ee6f
@@ -0,0 +1,24 @@
+Aspeed Vectored Interrupt Controller
+
+These bindings are for the Aspeed AST2400 interrupt controller register layout.
+The SoC has an legacy register layout, but this driver does not support that
+mode of operation.
+
+Required properties:
+
+- compatible : should be "aspeed,ast2400-vic".
+
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 1.
+- valid-sources : bitmask of valid irq sources
+
+Example:
+
+ vic: interrupt-controller {
+      compatible = "aspeed,ast2400-new-vic";
+      interrupt-controller;
+      #interrupt-cells = <1>;
+      valid-sources = < 0xffffffff 0x0007ffff>;
+      reg = <0x1e6c0080 0x80>;
+ };

2.7.4

---
 .../devicetree/bindings/clock/aspeed-clock.txt     | 137 +++++++++++++++++++++
 1 file changed, 137 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/aspeed-clock.txt

new file mode 100644
index 000000000000..91bdf34e5473
@@ -0,0 +1,137 @@
+Device Tree Clock bindings for the Aspeed SoCs
+
+Aspeed SoCs have a fixed frequency input osciallator is used to create the PLL
+and APB clocks. We can determine these frequencies by reading registers that
+are set according to strapping bits.
+
+Forth generation boards
+-----------------------
+
+eg, ast2400.
+
+CLKIN:
+ - compatible : Must be "fixed-clock"
+ - #clock-cells : Should be 0
+ - clock-frequency: 48e6, 25e6 or 24e6 depending on the input clock
+
+PLL:
+
+Required properties:
+ - compatible : Must be "aspeed,g4-hpll-clock"
+ - #clock-cells : Should be 0
+ - reg : Should contain registers location and length
+ - clocks : Should contain phandle + clock-specifier for the input clock (clkin)
+
+Optional properties:
+ - clock-output-names : Should contain clock name
+
+
+APB:
+
+Required properties:
+ - compatible : Must be "aspeed,g4-apb-clock"
+ - #clock-cells : Should be 0
+ - reg : Should contain registers location and length
+ - clocks : Should contain phandle + clock-specifier for the h-pll
+
+Optional properties:
+ - clock-output-names : Should contain clock name
+
+
+For example:
+
+	clk_clkin: clk_clkin {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <48000000>;
+	};
+
+	clk_hpll: clk_hpll {
+		compatible = "aspeed,g4-hpll-clock";
+		#clock-cells = <0>;
+		reg = <0x1e6e2008 0x4>;
+	};
+
+	clk_apb: clk_apb at 1e6e2008 {
+		#clock-cells = <0>;
+		compatible = "aspeed,g4-apb-clock";
+		reg = <0x1e6e2008 0x4>;
+		clocks = <&clk_hpll>;
+	};
+
+
+
+Fifth generation boards
+-----------------------
+
+eg, ast2500.
+
+CLKIN:
+Required properties:
+ - compatible : Must be "fixed-clock"
+ - #clock-cells : Should be 0
+ - clock-frequency: 25000000 or 24000000 depending on the input clock
+
+H-PLL:
+
+Required properties:
+ - compatible : Must be "aspeed,g5-hpll-clock"
+ - #clock-cells : Should be 0
+ - reg : Should contain registers location and length
+ - clocks : Should contain phandle + clock-specifier for the input clock (clkin)
+
+Optional properties:
+ - clock-output-names : Should contain clock name
+
+
+AHB:
+
+Required properties:
+ - compatible : Must be "aspeed,g5-ahb-clock"
+ - #clock-cells : Should be 0
+ - reg : Should contain registers location and length
+ - clocks : Should contain phandle + clock-specifier for the the h-pll
+
+Optional properties:
+ - clock-output-names : Should contain clock name
+
+APB:
+
+Required properties:
+ - compatible : Must be "aspeed,g4-apb-clock"
+ - #clock-cells : Should be 0
+ - reg : Should contain registers location and length
+ - clocks : Should contain phandle + clock-specifier for the the h-pll
+
+Optional properties:
+ - clock-output-names : Should contain clock name
+
+
+For example:
+	clk_clkin: clk_clkin at 1e6e2070 {
+		#clock-cells = <0>;
+		compatible = "aspeed,g5-clkin-clock";
+		reg = <0x1e6e2070 0x04>;
+	};
+
+	clk_hpll: clk_hpll at 1e6e2024 {
+		#clock-cells = <0>;
+		compatible = "aspeed,g5-hpll-clock";
+		reg = <0x1e6e2024 0x4>;
+		clocks = <&clk_clkin>;
+	};
+
+	clk_ahb: clk_ahb at 1e6e2070 {
+		#clock-cells = <0>;
+		compatible = "aspeed,g5-ahb-clock";
+		reg = <0x1e6e2070 0x4>;
+		clocks = <&clk_hpll>;
+	};
+
+	clk_apb: clk_apb at 1e6e2008 {
+		#clock-cells = <0>;
+		compatible = "aspeed,g5-apb-clock";
+		reg = <0x1e6e2008 0x4>;
+		clocks = <&clk_hpll>;
+	};
+

2.7.4

[+clock-related patches should include clock-maintainers and lists]

Am Donnerstag, 21. April 2016, 17:34:01 schrieb Joel Stanley:

declaring each clock individually in the dts) is still the preferred way but I don't think I can find Mike's mail from back then easily.

And I think most clock-controller implementations actually use that paradigm.

Heiko

Thanks.

Yep. I agree that's not ideal.

I can't picture how that would look. I took my lead from the moxart clock driver; is there a better example that I should follow?

Cheers,

Joel

Hi Joel,

Am Mittwoch, 27. April 2016, 18:01:00 schrieb Joel Stanley:

qcom, samsung, rockchip, hisilicon, imx, ...

I guess the design would depend on the actual layout of your clock- / system- controller - aka what else is contained there.

Heiko

I had a look here, and they appear to be much more complex than I need. The qcom directory is 41000 lines of code! The moxart driver is similar to what we do, but as you mentioned it is not arranged how you want it.

In the fourth generation parts, such as the ast2400, we have this layout:

clock rate
-----------------------------
clk_clkin 48000000

     clk_hpll       384000000
        clk_apb      48000000

clkin is the oscillator that may be running at 24, 25 or 48MHz. We can determine this from the strapping register.

The hpll divisor is controlled by strapping resistors, and indicated in the strapping register.

The apb is controlled by a register in the SCU, the Aspeed's bucket-of-bits for controlling various parts of the soc.

In our case we want don't need to adjust any clocks. We do want struct clk's so attached device drivers to know how fast they are being clocked. How do you see this laid out?

Cheers,

Joel

Am Donnerstag, 28. April 2016, 16:20:04 schrieb Joel Stanley:

I'm by no means authoritative ;-), but from what you describe below, clk- asm9260.c or clk-efm32gg.c might be going in that direction of very simple clock-controllers.

Sorry about pointing to more complex drivers for bigger socs at first :-)

I remember that from working on Samsung s3c24xx socs, the system-controller area also worked as sort of catch-all :-) .

see drivers referenced above.

One register controls most clocks so it makes sense to have one driver.

Cheers,
Ben.

The moxart timer IP is shared with another soc made by Aspeed. Generalise the registers that differ so the same driver can be used for both.

As we now depend on CLKSRC_MMIO, create a Kconfig symbol for the driver so we can express this dependency.

---
 .../bindings/timer/moxa,moxart-timer.txt           |  4 +-
 drivers/clocksource/Kconfig                        |  6 ++
 drivers/clocksource/Makefile                       |  2 +-
 drivers/clocksource/moxart_timer.c                 | 90 +++++++++++++++++-----
 4 files changed, 79 insertions(+), 23 deletions(-)

index da2d510cae47..4569757142f8 100644
@@ -2,7 +2,9 @@ MOXA ART timer
 
 Required properties:
 
-- compatible : Must be "moxa,moxart-timer"
+- compatible : Must be one of
+     - "moxa,moxart-timer"
+     - "aspeed,ast2400-timer"
 - reg : Should contain registers location and length
 - interrupts : Should contain the timer interrupt number
 - clocks : Should contain phandle for the clock that drives the counter

index c346be650892..b14ac4db6961 100644
@@ -411,4 +411,10 @@ config CLKSRC_ST_LPC
 	  Enable this option to use the Low Power controller timer
 	  as clocksource.
 
+config MOXART_TIMER
+	def_bool ARCH_MOXART || ARCH_ASPEED
+	depends on ARM && OF
+	select CLKSRC_OF
+	select CLKSRC_MMIO
+
 endmenu

index dc2b8997f6e6..14fe8172c174 100644
@@ -22,7 +22,7 @@ obj-$(CONFIG_ORION_TIMER)	+= time-orion.o
 obj-$(CONFIG_ARCH_BCM2835)	+= bcm2835_timer.o
 obj-$(CONFIG_ARCH_CLPS711X)	+= clps711x-timer.o
 obj-$(CONFIG_ARCH_ATLAS7)	+= timer-atlas7.o
-obj-$(CONFIG_ARCH_MOXART)	+= moxart_timer.o
+obj-$(CONFIG_MOXART_TIMER)	+= moxart_timer.o
 obj-$(CONFIG_ARCH_MXS)		+= mxs_timer.o
 obj-$(CONFIG_CLKSRC_PXA)	+= pxa_timer.o
 obj-$(CONFIG_ARCH_PRIMA2)	+= timer-prima2.o

2.7.4

Any idea where the IP block came from? Moxart contains a lot of licensed IP from faraday-tech. If this is one of them, we could maybe rename the driver accordingly.

Arnd

Faraday would be a good bet, given that aspeed use their ethernet mac IP.

I'll ask around.

Cheers,

Joel

In the future, please Cc the maintainers.

[ ... ]

It will be cleaner to:

1. Factor out:

	writel(TIMER1_DISABLE, base + TIMER_CR);
	writel(TIMER1_ENABLE, base + TIMER_CR);

b/drivers/clocksource/moxart_timer.c
index 19857af..aede6f1 100644

@@ -58,15 +58,25 @@
  static void __iomem *base;
  static unsigned int clock_count_per_tick;
 
-static int moxart_shutdown(struct clock_event_device *evt)
+static inline void moxart_disable(struct clock_event_device *evt)
  {
         writel(TIMER1_DISABLE, base + TIMER_CR);
+}
+
+static inline void moxart_enable(struct clock_event_device *evt)
+{
+       writel(TIMER1_ENABLE, base + TIMER_CR);
+}
+
+static int moxart_shutdown(struct clock_event_device *evt)
+{
+       moxart_disable(evt);
         return 0;
  }
 
  static int moxart_set_oneshot(struct clock_event_device *evt)
  {
-       writel(TIMER1_DISABLE, base + TIMER_CR);
+       moxart_disable(evt);
         writel(~0, base + TIMER1_BASE + REG_LOAD);
         return 0;
  }

@@ -74,7 +84,7 @@ static int moxart_set_oneshot(struct 

clock_event_device *evt)
static int moxart_set_periodic(struct clock_event_device *evt)

  {
         writel(clock_count_per_tick, base + TIMER1_BASE + REG_LOAD);
-       writel(TIMER1_ENABLE, base + TIMER_CR);
+       moxart_enable(evt);
         return 0;

}

@@ -83,12 +93,12 @@ static int moxart_clkevt_next_event(unsigned long cycles,

  {
         u32 u;

- writel(TIMER1_DISABLE, base + TIMER_CR);
+ moxart_disable(evt);

         u = readl(base + TIMER1_BASE + REG_COUNT) - cycles;
         writel(u, base + TIMER1_BASE + REG_MATCH1);

- writel(TIMER1_ENABLE, base + TIMER_CR);
+ moxart_enable(evt);

         return 0;

}

2. Encapsulate clkevt and use container_of

-static void __iomem *base;
-static unsigned int clock_count_per_tick;
+struct moxart_timer {

+       void __iomem *base;
+       unsigned int clock_count_per_tick;
+       struct clock_event_device clkevt;

+};
+
+static struct moxart_timer moxart_timer = {
+ .clkevt = {

+               .name                   = "moxart_timer",
+               .rating                 = 200,
+               .features               = CLOCK_EVT_FEAT_PERIODIC |
+                                               CLOCK_EVT_FEAT_ONESHOT,
+               .set_state_shutdown     = moxart_shutdown,
+               .set_state_periodic     = moxart_set_periodic,
+               .set_state_oneshot      = moxart_set_oneshot,
+               .tick_resume            = moxart_set_oneshot,
+               .set_next_event         = moxart_clkevt_next_event,

+ },
+};
+
+static inline struct moxart_timer *clkevt_to_moxart(struct clock_event_device *evt)
+{
+ return container_of(evt, struct moxart_timer, clkevt);
+}

static inline void moxart_disable(struct clock_event_device *evt) {
- writel(TIMER1_DISABLE, base + TIMER_CR);
+ writel(TIMER1_DISABLE, clkevt_to_moxart(evt)->base + TIMER_CR);
}

3. And finally, add 't1_disable' / 't2_disable' to the structure.

-- Daniel

  <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog

I disagree. Quite strongly in fact. These provide documentation (which isn't otherwise publicly available) and this will be handy if somebody wants to do something like add another timer etc.. in the future.

I much prefer when register definitions rather more exhaustive than trimmed to be only what's used by the driver.

Cheers,
Ben

Hey Daniel,

Thanks for the review.

Sure.

I agree with Ben; we're helping out by documenting the hardware in lieu of a public datasheet. I'd prefer to keep this here.

I considered this myself but went with the minimal change. I'm not fussed, so I will rework it as you suggest.

FTTMR010[1], but I don't have any other evidence. Would you take a patch to change the name or would you prefer leaving it as moxart?

Cheers,

Joel

[1] https://lists.nongnu.org/archive/html/qemu-devel/2013-03/msg04333.html

Ok, let's keep it.

Apparently, it could be the fttmr010 [2].

May be Jonas Jensen can confirm that.

If Jonas can confirm the moxart SoC is using the faraday timer, then it would make much more sense to rename it to timer-fttmr010.c and have the different instance of this timer to set it up with the platform specific bits.

[2]
http://git.denx.de/?p=u-boot.git;a=blob;f=include/faraday/fttmr010.h;h=2ab68d10218ed8241e5d2c916437c5918c17173d;hb=HEAD

The best I can do is infer (if that helps).

Also I can test on UC-7112-LX Plus hardware (the patch I got from Ben back in May 2015 was verified OK).

Jonas

From: Benjamin Herrenschmidt <[email protected]>

---
 drivers/irqchip/Makefile         |   1 +
 drivers/irqchip/irq-aspeed-vic.c | 238 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 239 insertions(+)
 create mode 100644 drivers/irqchip/irq-aspeed-vic.c

index b03cfcbbac6b..ec82e6e15a38 100644
@@ -65,3 +65,4 @@ obj-$(CONFIG_INGENIC_IRQ)		+= irq-ingenic.o
 obj-$(CONFIG_IMX_GPCV2)			+= irq-imx-gpcv2.o
 obj-$(CONFIG_PIC32_EVIC)		+= irq-pic32-evic.o
 obj-$(CONFIG_MVEBU_ODMI)		+= irq-mvebu-odmi.o
+obj-$(CONFIG_ARCH_ASPEED)		+= irq-aspeed-vic.o

2.7.4

A simple driver to create fixed rate clock devices from srapping registers.

---
 drivers/clk/Makefile        |   1 +
 drivers/clk/clk-aspeed-g4.c | 106 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 107 insertions(+)
 create mode 100644 drivers/clk/clk-aspeed-g4.c

index 46869d696e4d..bd28f6c95aa1 100644
@@ -84,3 +84,4 @@ obj-$(CONFIG_X86)			+= x86/
 obj-$(CONFIG_ARCH_ZX)			+= zte/
 obj-$(CONFIG_ARCH_ZYNQ)			+= zynq/
 obj-$(CONFIG_H8300)		+= h8300/
+obj-$(CONFIG_ARCH_ASPEED)		+= clk-aspeed-g4.o

2.7.4

Creates fixed clocks from the strapping registers.

---
 drivers/clk/Makefile        |   2 +-
 drivers/clk/clk-aspeed-g5.c | 189 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 190 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/clk-aspeed-g5.c

index bd28f6c95aa1..cdd4643e9ee1 100644
@@ -84,4 +84,4 @@ obj-$(CONFIG_X86)			+= x86/
 obj-$(CONFIG_ARCH_ZX)			+= zte/
 obj-$(CONFIG_ARCH_ZYNQ)			+= zynq/
 obj-$(CONFIG_H8300)		+= h8300/
-obj-$(CONFIG_ARCH_ASPEED)		+= clk-aspeed-g4.o
+obj-$(CONFIG_ARCH_ASPEED)		+= clk-aspeed-g4.o clk-aspeed-g5.o

2.7.4

A common device tree for all forth gen/ast2400 systems and a board specific dts for the Palmetto OpenPower developemnt machine which was used for testing.

---
 arch/arm/boot/dts/Makefile                    |   1 +
 arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts |  21 ++++
 arch/arm/boot/dts/aspeed-g4.dtsi              | 152 ++++++++++++++++++++++++++
 3 files changed, 174 insertions(+)
 create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
 create mode 100644 arch/arm/boot/dts/aspeed-g4.dtsi

index 95c1923ce6fa..dee3a92cbd3c 100644
@@ -839,6 +839,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
 	mt8127-moose.dtb \
 	mt8135-evbp1.dtb
 dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
+dtb-$(CONFIG_ARCH_ASPEED) += aspeed-bmc-opp-palmetto.dtb
 endif
 
 dtstree		:= $(srctree)/$(src)

new file mode 100644
index 000000000000..29015c4b70bb
@@ -0,0 +1,21 @@
+/dts-v1/;
+
+#include "aspeed-g4.dtsi"
+
+/ {
+	model = "Palmetto BMC";
+	compatible = "tyan,palmetto-bmc", "aspeed,ast2400";
+
+	chosen {
+		stdout-path = &uart5;
+		bootargs = "console=ttyS4,38400";
+	};
+
+	memory {
+		reg = < 0x40000000 0x10000000 >;
+	};
+};
+
+&uart5 {
+	status = "okay";
+};

2.7.4

This adds a common device tree for all fifth generation Aspeed systems, and a board specific device tree for the ast2500 evaluation board.

---
 arch/arm/boot/dts/Makefile               |   3 +-
 arch/arm/boot/dts/aspeed-ast2500-evb.dts |  21 +++++
 arch/arm/boot/dts/aspeed-g5.dtsi         | 156 +++++++++++++++++++++++++++++++
 3 files changed, 179 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/aspeed-ast2500-evb.dts
 create mode 100644 arch/arm/boot/dts/aspeed-g5.dtsi

index dee3a92cbd3c..98251828883f 100644
@@ -839,7 +839,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
 	mt8127-moose.dtb \
 	mt8135-evbp1.dtb
 dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
-dtb-$(CONFIG_ARCH_ASPEED) += aspeed-bmc-opp-palmetto.dtb
+dtb-$(CONFIG_ARCH_ASPEED) += aspeed-bmc-opp-palmetto.dtb \
+	aspeed-ast2500-evb.dtb
 endif
 
 dtstree		:= $(srctree)/$(src)

new file mode 100644
index 000000000000..24f2b60ed2fd
@@ -0,0 +1,21 @@
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+
+/ {
+	model = "AST2500 EVB";
+	compatible = "aspeed,ast2500";
+
+	chosen {
+		stdout-path = &uart5;
+		bootargs = "console=ttyS4,115200";
+	};
+
+	memory {
+		reg = < 0x80000000 0x10000000 >;
+	};
+};
+
+&uart5 {
+	status = "okay";
+};

2.7.4

Well caught. I've got a different part on my v1.1 board, but it is also 4Gbit.

You're correct, we are relying on uboot. There's also a tricky 'div13' register in the SCU that we are setting in our board file for these numbers to work out.

In V3 I've added a clk driver to take are of these details.

Thanks for the review. Did you manage to get these patches booting on your board?

Cheers,

Joel

Aspeed devices are a common Baseboard Management Controller (BMC) system on chip containing an ARM9 or ARM11 core, off-chip DDR RAM and support for a large number of peripherals.

This patch adds basic support for the ast2400 and ast2500 machines, capable of booting to a prompt in QEMU (-M palmetto-bmc), on an Palmetto OpenPower development machine, and on the ast2500 EVB.

---
 MAINTAINERS                   |  8 +++++
 arch/arm/Kconfig              |  2 ++
 arch/arm/Makefile             |  1 +
 arch/arm/mach-aspeed/Kconfig  | 28 +++++++++++++++
 arch/arm/mach-aspeed/Makefile |  3 ++
 arch/arm/mach-aspeed/aspeed.c | 83 +++++++++++++++++++++++++++++++++++++++++++
 6 files changed, 125 insertions(+)
 create mode 100644 arch/arm/mach-aspeed/Kconfig
 create mode 100644 arch/arm/mach-aspeed/Makefile
 create mode 100644 arch/arm/mach-aspeed/aspeed.c

index 61a323a6b2cf..d0a1962f7753 100644
@@ -975,6 +975,14 @@ F:	arch/arm/mach-artpec
 F:	arch/arm/boot/dts/artpec6*
 F:	drivers/clk/clk-artpec6.c
 
+ARM/ASPEED MACHINE SUPPORT
+M:	Joel Stanley <[email protected]>
+S:	Maintained
+F:	arch/arm/mach-aspeed/
+F:	arch/arm/boot/dts/aspeed-*
+F:	arch/arm/boot/dts/ast2400.dtsi
+F:	drivers/*/*aspeed*
+
 ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT
 M:	Nicolas Ferre <[email protected]>
 M:	Alexandre Belloni <[email protected]>

index cdfa6c2b7626..c4512f6b77f6 100644
@@ -775,6 +775,8 @@ source "arch/arm/mach-meson/Kconfig"
 
 source "arch/arm/mach-moxart/Kconfig"
 
+source "arch/arm/mach-aspeed/Kconfig"
+
 source "arch/arm/mach-mv78xx0/Kconfig"
 
 source "arch/arm/mach-imx/Kconfig"

index 8c3ce2ac44c4..8ab09fb78e1c 100644
@@ -184,6 +184,7 @@ machine-$(CONFIG_ARCH_LPC32XX)		+= lpc32xx
 machine-$(CONFIG_ARCH_MESON)		+= meson
 machine-$(CONFIG_ARCH_MMP)		+= mmp
 machine-$(CONFIG_ARCH_MOXART)		+= moxart
+machine-$(CONFIG_ARCH_ASPEED)		+= aspeed
 machine-$(CONFIG_ARCH_MV78XX0)		+= mv78xx0
 machine-$(CONFIG_ARCH_MVEBU)		+= mvebu
 machine-$(CONFIG_ARCH_MXC)		+= imx

new file mode 100644
index 000000000000..30bafc0bbd8b
@@ -0,0 +1,28 @@
+menuconfig ARCH_ASPEED
+	bool "Aspeed BMC architectures"
+	select OF
+	select SRAM
+	help
+	  Say Y here if you want to run your kernel on hardware with an
+	  ASpeed BMC SoC.
+
+if ARCH_ASPEED
+
+config MACH_AST_G4
+	bool "Aspeed SoC 4th Generation" if ARCH_MULTI_V5
+	depends on ARCH_ASPEED
+	select CPU_ARM926T
+	help
+	 Say yes if you intend to run on an Aspeed ast2400 or similar
+	 fourth generation BMCs, such as those used by OpenPower Power8
+	 systems.
+
+config MACH_AST_G5
+	bool "Aspeed SoC 5th Generation" if ARCH_MULTI_V6
+	depends on ARCH_ASPEED
+	select CPU_V6
+	help
+	 Say yes if you intend to run on an Aspeed ast2500 or similar
+	 fifth generation Aspeed BMCs.
+
+endif

new file mode 100644
index 000000000000..3a4f025dd520
@@ -0,0 +1,3 @@
+# Object file lists.
+
+obj-$(CONFIG_ARCH_ASPEED)	+= aspeed.o

2.7.4

It may or may not be already correct, you don't necessarily have a serial enabled bootloader or it might be using a UART driver that doesn't use the 'standard' divisors etc... This just sanitizes it.

This register contains misc controls. That specific bit controls a clock divisor by 13 from the main 24Mhz source, which provides a reasonably "standard" 1.84 Mhz input to the UARTs.

Cheers
Ben.

On a second thought ... if we chose to not support random crap vendor uboots, we could make it a requirement that this register is already set appropriately by the bootloader to match what's in the device-tree I suppose...

That, along with a watchdog driver, would allow us to completely remove that init code.

Joel, Jeremy, your call.

Cheers,
Ben.

Hi,

ARM Linux expects bootloader to initialize one serial port (Documentation/arm/Booting). Though mentioned as optional, recommended so far haven't seen one w/o that. And to debug at early boot stage like in assembly and where uart driver is not yet up, this helps in being able to debug w/o jtag.

Regards
afzal

I did some testing and on the palmetto we still get console with our u-boot, so I'll drop the divisor change.

Cheers,

Joel

Ok, very good. We can always add it back if we see a good reason for needing it, but I think it's better to start by adding the drivers and leave workarounds like this for later when we know if we actually require them.

Arnd

---
 arch/arm/configs/aspeed_g4_defconfig | 86 +++++++++++++++++++++++++++++++++++
 arch/arm/configs/aspeed_g5_defconfig | 88 ++++++++++++++++++++++++++++++++++++
 2 files changed, 174 insertions(+)
 create mode 100644 arch/arm/configs/aspeed_g4_defconfig
 create mode 100644 arch/arm/configs/aspeed_g5_defconfig

new file mode 100644
index 000000000000..83691bf98d09
@@ -0,0 +1,86 @@
+CONFIG_KERNEL_XZ=y
+CONFIG_SYSVIPC=y
+CONFIG_USELIB=y
+CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_RD_LZ4 is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_BPF_SYSCALL=y
+# CONFIG_SHMEM is not set
+# CONFIG_AIO is not set
+CONFIG_EMBEDDED=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+CONFIG_CC_STACKPROTECTOR_STRONG=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLOCK is not set
+# CONFIG_ARCH_MULTI_V7 is not set
+CONFIG_ARCH_ASPEED=y
+CONFIG_MACH_AST_G4=y
+CONFIG_DEBUG_RODATA=y
+CONFIG_AEABI=y
+CONFIG_UACCESS_WITH_MEMCPY=y
+CONFIG_SECCOMP=y
+# CONFIG_ATAGS is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_KEXEC=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_RUNTIME_UARTS=6
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_FIRMWARE_MEMMAP=y
+CONFIG_FANOTIFY=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_PAGE_POISONING=y
+CONFIG_DEBUG_KMEMLEAK=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_WQ_WATCHDOG=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_SCHED_STACK_END_CHECK=y
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y
+# CONFIG_FTRACE is not set
+CONFIG_MEMTEST=y
+CONFIG_UBSAN=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_UART_8250=y
+CONFIG_DEBUG_UART_PHYS=0x1e784000
+CONFIG_DEBUG_UART_VIRT=0xe8784000
+CONFIG_EARLY_PRINTK=y
+CONFIG_DEBUG_SET_MODULE_RONX=y
+# CONFIG_XZ_DEC_X86 is not set
+# CONFIG_XZ_DEC_POWERPC is not set
+# CONFIG_XZ_DEC_IA64 is not set
+# CONFIG_XZ_DEC_SPARC is not set

2.7.4

Please also add all drivers you need to multi_v5_defconfig. Unfortunately we haven't come up with a good plan for a multi_v6_defconfig that allows us to also have a combined v6+v7 config, so that doesn't exist at this time.

Arnd

Looks good overall. I have a couple of comments, see the replies to the individual patches.

Once the review comments are all addressed, please send a pull request containing all the arch/arm patches to arm at kernel.org and have the drivers (clk, irq, clocksource) merged by the respective subsystem maintainers. The DT bindings normally go together with the drivers, but they can also get merged with the dts files.

For pull requests sent to arm at kernel.org, please split them up into separate pull requests for different topics (dts files, defconfig, arch code, cleanups, ...) so we can merge them into the appropriate branches that we send to Linus during the merge window.

Arnd