sh: Update dma-sh api

PATCH Superseded Nobuhiro Iwamatsu 5 participants 9 messages Mar 10, 2009 – Mar 16, 2009

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Nobuhiro Iwamatsu

author

2009-03-10 02:52 UTC #0 lore raw

PATCH v2 1/1 sh: Update dma-sh api

Add DMA support of new SH CPU and the change of definition. And add Multi IRQ support for SH7763/64/80/85.

Signed-off-by Nobuhiro Iwamatsu <[email protected]>

Signed-off-by Yoshihiro Shimoda <[email protected]>

---
 Makefile                                 |    4 +-
 arch/sh/drivers/dma/Kconfig              |    8 +-
 arch/sh/drivers/dma/dma-sh.c             |  172 ++++++++++++++++++++----------
 arch/sh/drivers/dma/dma-sh.h             |   75 -------------
 arch/sh/include/asm/dma-sh.h             |  117 ++++++++++++++++++++
 arch/sh/include/asm/dma.h                |    8 +-
 arch/sh/include/cpu-sh3/cpu/dma.h        |   17 +--
 arch/sh/include/cpu-sh4/cpu/dma-sh4a.h   |   94 ++++++++++++++++
 arch/sh/include/cpu-sh4/cpu/dma-sh7780.h |   39 -------
 arch/sh/include/cpu-sh4/cpu/dma.h        |   30 +++---
 10 files changed, 354 insertions(+), 210 deletions(-)
 delete mode 100644 arch/sh/drivers/dma/dma-sh.h
 create mode 100644 arch/sh/include/asm/dma-sh.h
 create mode 100644 arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
 delete mode 100644 arch/sh/include/cpu-sh4/cpu/dma-sh7780.h

Makefile +1 -2

index 681c1d2..5f6df0c 100644
@@ -190,8 +190,8 @@ SUBARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ \
 # Default value for CROSS_COMPILE is not to prefix executables
 # Note: Some architectures assign CROSS_COMPILE in their arch/*/Makefile
 export KBUILD_BUILDHOST := $(SUBARCH)
-ARCH		?= $(SUBARCH)
-CROSS_COMPILE	?+ARCH		?= sh
+CROSS_COMPILE	?= sh4-unknown-linux-gnu-
 
 # Architecture as present in compile.h
 UTS_MACHINE 	:= $(ARCH)

arch/sh/drivers/dma/Kconfig +4 -4

index 0193636..57d95fc 100644
@@ -12,10 +12,10 @@ config SH_DMA
 config NR_ONCHIP_DMA_CHANNELS
 	int
 	depends on SH_DMA
-	default "6" if CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721
-	default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R
-	default "12" if CPU_SUBTYPE_SH7780
-	default "4"
+	default "4" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7750S
+	default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R || CPU_SUBTYPE_SH7760
+	default "12" if CPU_SUBTYPE_SH7723 || CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785
+	default "6"
 	help
 	  This allows you to specify the number of channels that the on-chip
 	  DMAC supports. This will be 4 for SH7750/SH7751 and 8 for the

arch/sh/drivers/dma/dma-sh.c +115 ~~-57~~

296 lines not on this page · raw message

arch/sh/drivers/dma/dma-sh.h deleted +0 ~~-75~~

75 lines not on this page · raw message

arch/sh/include/asm/dma-sh.h new file +117 -0

117 lines not on this page · raw message

arch/sh/include/asm/dma.h +2 -6

index beca712..085e05a 100644
@@ -23,12 +23,8 @@
 /* But... */
 /* XXX: This is not applicable to SuperH, just needed for alloc_bootmem */
 #define MAX_DMA_ADDRESS		(PAGE_OFFSET+0x10000000)
-
-#ifdef CONFIG_NR_DMA_CHANNELS
-#  define MAX_DMA_CHANNELS	(CONFIG_NR_DMA_CHANNELS)
-#else
-#  define MAX_DMA_CHANNELS	(CONFIG_NR_ONCHIP_DMA_CHANNELS)
-#endif
+/* MAX DMA Channel */
+#define MAX_DMA_CHANNELS	(CONFIG_NR_ONCHIP_DMA_CHANNELS)
 
 /*
  * Read and write modes can mean drastically different things depending on the

arch/sh/include/cpu-sh3/cpu/dma.h +6 ~~-11~~

index 6813c32..0ea15f3 100644
@@ -1,22 +1,17 @@
 #ifndef __ASM_CPU_SH3_DMA_H
 #define __ASM_CPU_SH3_DMA_H
 
-
 #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7721)
-#define SH_DMAC_BASE	0xa4010020
-#else
-#define SH_DMAC_BASE	0xa4000020
+    defined(CONFIG_CPU_SUBTYPE_SH7721) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7710) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7712)
+#define SH_DMAC_BASE0	0xa4010020
+#else /* SH7705/06/07/09 */
+#define SH_DMAC_BASE0	0xa4000020
 #endif
 
-#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709)
 #define DMTE0_IRQ	48
-#define DMTE1_IRQ	49
-#define DMTE2_IRQ	50
-#define DMTE3_IRQ	51
 #define DMTE4_IRQ	76
-#define DMTE5_IRQ	77
-#endif
 
 /* Definitions for the SuperH DMAC */
 #define TM_BURST	0x00000020

arch/sh/include/cpu-sh4/cpu/dma-sh4a.h new file +94 -0

94 lines not on this page · raw message

arch/sh/include/cpu-sh4/cpu/dma-sh7780.h deleted +0 ~~-39~~

deleted file mode 100644
index 71b426a..0000000
@@ -1,39 +0,0 @@
-#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
-#define __ASM_SH_CPU_SH4_DMA_SH7780_H
-
-#define REQ_HE	0x000000C0
-#define REQ_H	0x00000080
-#define REQ_LE	0x00000040
-#define TM_BURST 0x0000020
-#define TS_8	0x00000000
-#define TS_16	0x00000008
-#define TS_32	0x00000010
-#define TS_16BLK	0x00000018
-#define TS_32BLK	0x00100000
-
-/*
- * The SuperH DMAC supports a number of transmit sizes, we list them here,
- * with their respective values as they appear in the CHCR registers.
- *
- * Defaults to a 64-bit transfer size.
- */
-enum {
-	XMIT_SZ_8BIT,
-	XMIT_SZ_16BIT,
-	XMIT_SZ_32BIT,
-	XMIT_SZ_128BIT,
-	XMIT_SZ_256BIT,
-};
-
-/*
- * The DMA count is defined as the number of bytes to transfer.
- */
-static unsigned int ts_shift[] __maybe_unused = {
-	[XMIT_SZ_8BIT]		= 0,
-	[XMIT_SZ_16BIT]		= 1,
-	[XMIT_SZ_32BIT]		= 2,
-	[XMIT_SZ_128BIT]	= 4,
-	[XMIT_SZ_256BIT]	= 5,
-};
-
-#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */

arch/sh/include/cpu-sh4/cpu/dma.h +14 ~~-16~~

index 235b7cd..bcb3024 100644
@@ -1,31 +1,29 @@
 #ifndef __ASM_CPU_SH4_DMA_H
 #define __ASM_CPU_SH4_DMA_H
 
-#define DMAOR_INIT	( 0x8000 | DMAOR_DME )
-
 /* SH7751/7760/7780 DMA IRQ sources */
-#define DMTE0_IRQ	34
-#define DMTE1_IRQ	35
-#define DMTE2_IRQ	36
-#define DMTE3_IRQ	37
-#define DMTE4_IRQ	44
-#define DMTE5_IRQ	45
-#define DMTE6_IRQ	46
-#define DMTE7_IRQ	47
-#define DMAE_IRQ	38
 
 #ifdef CONFIG_CPU_SH4A
-#define SH_DMAC_BASE	0xfc808020
 
+#define DMAOR_INIT	(DMAOR_DME)
 #define CHCR_TS_MASK	0x18
 #define CHCR_TS_SHIFT	3
 
-#include <cpu/dma-sh7780.h>
-#else
-#define SH_DMAC_BASE	0xffa00000
+#include <cpu/dma-sh4a.h>
+#else /* CONFIG_CPU_SH4A */
+/*
+ * SH7750/SH7751/SH7760
+ */
+#define DMTE0_IRQ	34
+#define DMTE4_IRQ	44
+#define DMTE6_IRQ	46
+#define DMAE0_IRQ	38
 
+#define DMAOR_INIT	(0x8000|DMAOR_DME)
+#define SH_DMAC_BASE0	0xffa00000
+#define SH_DMAC_BASE1	0xffa00070
 /* Definitions for the SuperH DMAC */
-#define TM_BURST	0x0000080
+#define TM_BURST	0x00000080
 #define TS_8		0x00000010
 #define TS_16		0x00000020
 #define TS_32		0x00000030

Signature · 1 line

1.6.1.3

Nobuhiro Iwamatsu

author

2009-03-10 04:48 UTC #1 lore raw

PATCH v2 1/1 sh: Update dma-sh api

Add DMA support of new SH CPU and the change of definition. And add Multi IRQ support for SH7763/64/80/85.

Signed-off-by Nobuhiro Iwamatsu <[email protected]>

Signed-off-by Yoshihiro Shimoda <[email protected]>

---
V2: Remove Makefile

 arch/sh/drivers/dma/Kconfig              |    8 +-
 arch/sh/drivers/dma/dma-sh.c             |  172 ++++++++++++++++++++----------
 arch/sh/drivers/dma/dma-sh.h             |   75 -------------
 arch/sh/include/asm/dma-sh.h             |  117 ++++++++++++++++++++
 arch/sh/include/asm/dma.h                |    8 +-
 arch/sh/include/cpu-sh3/cpu/dma.h        |   17 +--
 arch/sh/include/cpu-sh4/cpu/dma-sh4a.h   |   94 ++++++++++++++++
 arch/sh/include/cpu-sh4/cpu/dma-sh7780.h |   39 -------
 arch/sh/include/cpu-sh4/cpu/dma.h        |   30 +++---
 9 files changed, 352 insertions(+), 208 deletions(-)
 delete mode 100644 arch/sh/drivers/dma/dma-sh.h
 create mode 100644 arch/sh/include/asm/dma-sh.h
 create mode 100644 arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
 delete mode 100644 arch/sh/include/cpu-sh4/cpu/dma-sh7780.h

arch/sh/drivers/dma/Kconfig +4 -4

index 0193636..57d95fc 100644
@@ -12,10 +12,10 @@ config SH_DMA
 config NR_ONCHIP_DMA_CHANNELS
 	int
 	depends on SH_DMA
-	default "6" if CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721
-	default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R
-	default "12" if CPU_SUBTYPE_SH7780
-	default "4"
+	default "4" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7750S
+	default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R || CPU_SUBTYPE_SH7760
+	default "12" if CPU_SUBTYPE_SH7723 || CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785
+	default "6"
 	help
 	  This allows you to specify the number of channels that the on-chip
 	  DMAC supports. This will be 4 for SH7750/SH7751 and 8 for the

arch/sh/drivers/dma/dma-sh.c +115 ~~-57~~

296 lines not on this page · raw message

arch/sh/drivers/dma/dma-sh.h deleted +0 ~~-75~~

75 lines not on this page · raw message

arch/sh/include/asm/dma-sh.h new file +117 -0

117 lines not on this page · raw message

arch/sh/include/asm/dma.h +2 -6

index beca712..085e05a 100644
@@ -23,12 +23,8 @@
 /* But... */
 /* XXX: This is not applicable to SuperH, just needed for alloc_bootmem */
 #define MAX_DMA_ADDRESS		(PAGE_OFFSET+0x10000000)
-
-#ifdef CONFIG_NR_DMA_CHANNELS
-#  define MAX_DMA_CHANNELS	(CONFIG_NR_DMA_CHANNELS)
-#else
-#  define MAX_DMA_CHANNELS	(CONFIG_NR_ONCHIP_DMA_CHANNELS)
-#endif
+/* MAX DMA Channel */
+#define MAX_DMA_CHANNELS	(CONFIG_NR_ONCHIP_DMA_CHANNELS)
 
 /*
  * Read and write modes can mean drastically different things depending on the

arch/sh/include/cpu-sh3/cpu/dma.h +6 ~~-11~~

index 6813c32..0ea15f3 100644
@@ -1,22 +1,17 @@
 #ifndef __ASM_CPU_SH3_DMA_H
 #define __ASM_CPU_SH3_DMA_H
 
-
 #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7721)
-#define SH_DMAC_BASE	0xa4010020
-#else
-#define SH_DMAC_BASE	0xa4000020
+    defined(CONFIG_CPU_SUBTYPE_SH7721) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7710) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7712)
+#define SH_DMAC_BASE0	0xa4010020
+#else /* SH7705/06/07/09 */
+#define SH_DMAC_BASE0	0xa4000020
 #endif
 
-#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709)
 #define DMTE0_IRQ	48
-#define DMTE1_IRQ	49
-#define DMTE2_IRQ	50
-#define DMTE3_IRQ	51
 #define DMTE4_IRQ	76
-#define DMTE5_IRQ	77
-#endif
 
 /* Definitions for the SuperH DMAC */
 #define TM_BURST	0x00000020

arch/sh/include/cpu-sh4/cpu/dma-sh4a.h new file +94 -0

94 lines not on this page · raw message

arch/sh/include/cpu-sh4/cpu/dma-sh7780.h deleted +0 ~~-39~~

deleted file mode 100644
index 71b426a..0000000
@@ -1,39 +0,0 @@
-#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
-#define __ASM_SH_CPU_SH4_DMA_SH7780_H
-
-#define REQ_HE	0x000000C0
-#define REQ_H	0x00000080
-#define REQ_LE	0x00000040
-#define TM_BURST 0x0000020
-#define TS_8	0x00000000
-#define TS_16	0x00000008
-#define TS_32	0x00000010
-#define TS_16BLK	0x00000018
-#define TS_32BLK	0x00100000
-
-/*
- * The SuperH DMAC supports a number of transmit sizes, we list them here,
- * with their respective values as they appear in the CHCR registers.
- *
- * Defaults to a 64-bit transfer size.
- */
-enum {
-	XMIT_SZ_8BIT,
-	XMIT_SZ_16BIT,
-	XMIT_SZ_32BIT,
-	XMIT_SZ_128BIT,
-	XMIT_SZ_256BIT,
-};
-
-/*
- * The DMA count is defined as the number of bytes to transfer.
- */
-static unsigned int ts_shift[] __maybe_unused = {
-	[XMIT_SZ_8BIT]		= 0,
-	[XMIT_SZ_16BIT]		= 1,
-	[XMIT_SZ_32BIT]		= 2,
-	[XMIT_SZ_128BIT]	= 4,
-	[XMIT_SZ_256BIT]	= 5,
-};
-
-#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */

arch/sh/include/cpu-sh4/cpu/dma.h +14 ~~-16~~

index 235b7cd..bcb3024 100644
@@ -1,31 +1,29 @@
 #ifndef __ASM_CPU_SH4_DMA_H
 #define __ASM_CPU_SH4_DMA_H
 
-#define DMAOR_INIT	( 0x8000 | DMAOR_DME )
-
 /* SH7751/7760/7780 DMA IRQ sources */
-#define DMTE0_IRQ	34
-#define DMTE1_IRQ	35
-#define DMTE2_IRQ	36
-#define DMTE3_IRQ	37
-#define DMTE4_IRQ	44
-#define DMTE5_IRQ	45
-#define DMTE6_IRQ	46
-#define DMTE7_IRQ	47
-#define DMAE_IRQ	38
 
 #ifdef CONFIG_CPU_SH4A
-#define SH_DMAC_BASE	0xfc808020
 
+#define DMAOR_INIT	(DMAOR_DME)
 #define CHCR_TS_MASK	0x18
 #define CHCR_TS_SHIFT	3
 
-#include <cpu/dma-sh7780.h>
-#else
-#define SH_DMAC_BASE	0xffa00000
+#include <cpu/dma-sh4a.h>
+#else /* CONFIG_CPU_SH4A */
+/*
+ * SH7750/SH7751/SH7760
+ */
+#define DMTE0_IRQ	34
+#define DMTE4_IRQ	44
+#define DMTE6_IRQ	46
+#define DMAE0_IRQ	38
 
+#define DMAOR_INIT	(0x8000|DMAOR_DME)
+#define SH_DMAC_BASE0	0xffa00000
+#define SH_DMAC_BASE1	0xffa00070
 /* Definitions for the SuperH DMAC */
-#define TM_BURST	0x0000080
+#define TM_BURST	0x00000080
 #define TS_8		0x00000010
 #define TS_16		0x00000020
 #define TS_32		0x00000030

Signature · 1 line

1.6.1.3

Paul Mundt

2009-03-10 06:02 UTC #2 lore raw

In reply to Nobuhiro Iwamatsu

Quoted 7 lines · Nobuhiro Iwamatsu

arch/sh/include/asm/dma.h +0 -0

index beca712..085e05a 100644
@@ -23,12 +23,8 @@
 /* But... */
 /* XXX: This is not applicable to SuperH, just needed for alloc_bootmem */

arch/sh/include/asm/dma.h line 28

Quoted 10 lines

arch/sh/include/asm/dma.h +2 -6

 #define MAX_DMA_ADDRESS		(PAGE_OFFSET+0x10000000)
-
-#ifdef CONFIG_NR_DMA_CHANNELS
-#  define MAX_DMA_CHANNELS	(CONFIG_NR_DMA_CHANNELS)
-#else
-#  define MAX_DMA_CHANNELS	(CONFIG_NR_ONCHIP_DMA_CHANNELS)
-#endif
+/* MAX DMA Channel */
+#define MAX_DMA_CHANNELS	(CONFIG_NR_ONCHIP_DMA_CHANNELS)

This breaks the Dreamcast, which contains multiple DMACs and needs more than the on-chip channels managed by the DMA API. As the Dreamcast is the primary user of this code, please make sure you do not break its use of the API. It would also be good if someone can verify whether the G2 and PVR2 DMA still work after this patch is applied.

On the other hand, I don't know how much we really want to be doing here in the first place. All new development should be happening on the dmaengine API instead, this code is mostly for keeping the existing users limping along, and not much else. Matt Fleming was doing some work there, it would be preferable to see that code updated and merged rather than work spent on the old DMA API.

Nobuhiro Iwamatsu

author

2009-03-10 07:22 UTC #3 lore raw

In reply to Nobuhiro Iwamatsu

Quoted 17 lines · Paul Mundt

Quoted 6 lines · Nobuhiro Iwamatsu

arch/sh/include/asm/dma.h +0 -0

index beca712..085e05a 100644
@@ -23,12 +23,8 @@
 /* But... */

arch/sh/include/asm/dma.h line 27

Quoted 10 lines

arch/sh/include/asm/dma.h +2 -6

 /* XXX: This is not applicable to SuperH, just needed for alloc_bootmem */
 #define MAX_DMA_ADDRESS		(PAGE_OFFSET+0x10000000)
-
-#ifdef CONFIG_NR_DMA_CHANNELS
-#  define MAX_DMA_CHANNELS	(CONFIG_NR_DMA_CHANNELS)
-#else
-#  define MAX_DMA_CHANNELS	(CONFIG_NR_ONCHIP_DMA_CHANNELS)
-#endif
+/* MAX DMA Channel */
+#define MAX_DMA_CHANNELS	(CONFIG_NR_ONCHIP_DMA_CHANNELS)

Thank you for your comments.

Quoted 6 lines

Quoted 1 line
This breaks the Dreamcast, which contains multiple DMACs and needs more than the on-chip channels managed by the DMA API. As the Dreamcast is the primary user of this code, please make sure you do not break its use of the API. It would also be good if someone can verify whether the G2 and PVR2 DMA still work after this patch is applied.

OK. I will fix this point.

Quoted 8 lines

On the other hand, I don't know how much we really want to be doing here in the first place. All new development should be happening on the dmaengine API instead, this code is mostly for keeping the existing users limping along, and not much else. Matt Fleming was doing some work there, it would be preferable to see that code updated and merged rather than work spent on the old DMA API.

I see.
I have already been writing the driver of DMAengine, and I am testing. To make old DMA-API coexist with dma engine in these patches, I wrote.

Best regards,
Nobuhiro

Paul Mundt

2009-03-10 07:23 UTC #4 lore raw

In reply to Nobuhiro Iwamatsu

Quoted 40 lines · Nobuhiro Iwamatsu

Quoted 10 lines · Paul Mundt
Quoted 9 lines · Nobuhiro Iwamatsu
arch/sh/include/asm/dma.h +0 -0
index beca712..085e05a 100644
@@ -23,12 +23,8 @@
 /* But... */
 /* XXX: This is not applicable to SuperH, just needed for alloc_bootmem 
 */
 #define MAX_DMA_ADDRESS		(PAGE_OFFSET+0x10000000)
Quoted 8 lines
arch/sh/include/asm/dma.h line 27
Quoted 8 lines
arch/sh/include/asm/dma.h +2 -6
-
-#ifdef CONFIG_NR_DMA_CHANNELS
-#  define MAX_DMA_CHANNELS	(CONFIG_NR_DMA_CHANNELS)
-#else
-#  define MAX_DMA_CHANNELS	(CONFIG_NR_ONCHIP_DMA_CHANNELS)
-#endif
+/* MAX DMA Channel */
+#define MAX_DMA_CHANNELS	(CONFIG_NR_ONCHIP_DMA_CHANNELS)
Thank you for your comments.
Quoted 6 lines
Quoted 1 line
This breaks the Dreamcast, which contains multiple DMACs and needs more than the on-chip channels managed by the DMA API. As the Dreamcast is the primary user of this code, please make sure you do not break its use of the API. It would also be good if someone can verify whether the G2 and PVR2 DMA still work after this patch is applied.
OK. I will fix this point.
Quoted 8 lines
On the other hand, I don't know how much we really want to be doing here in the first place. All new development should be happening on the dmaengine API instead, this code is mostly for keeping the existing users limping along, and not much else. Matt Fleming was doing some work there, it would be preferable to see that code updated and merged rather than work spent on the old DMA API.

Quoted 4 lines

I see.
I have already been writing the driver of DMAengine, and I am testing. To make old DMA-API coexist with dma engine in these patches, I wrote.

Ah, ok, I wasn't aware that that was what your intention was. In that case, once the Dreamcast fallout is fixed, I'll merge these.

Adrian McMenamin

2009-03-13 12:05 UTC #5 lore raw

In reply to Nobuhiro Iwamatsu

2009/3/10 Paul Mundt <[email protected]>:

Quoted 3 lines · Nobuhiro Iwamatsu

Quoted 2 lines
Quoted 1 line · Paul Mundt
On Tue, Mar 10, 2009 at 01:48:14PM +0900, Nobuhiro Iwamatsu wrote:

...

Quoted 6 lines

Quoted 4 lines
I see.
I have already been writing the driver of DMAengine, and I am testing. To make old DMA-API coexist with dma engine in these patches, I wrote.
Ah, ok, I wasn't aware that that was what your intention was. In that case, once the Dreamcast fallout is fixed, I'll merge these.

Just come across this. I am happy to test any new patch on the Dreamcast once it's done. Just let me know and kick me if I don't respond.

Paul Mundt

2009-03-13 15:09 UTC #6 lore raw

In reply to Nobuhiro Iwamatsu

Quoted 11 lines · Adrian McMenamin

2009/3/10 Paul Mundt <[email protected]>:
Quoted 3 lines · Nobuhiro Iwamatsu
Quoted 2 lines
Quoted 1 line · Paul Mundt
On Tue, Mar 10, 2009 at 01:48:14PM +0900, Nobuhiro Iwamatsu wrote:
...
Quoted 4 lines
Quoted 4 lines
I see.
I have already been writing the driver of DMAengine, and I am testing. To make old DMA-API coexist with dma engine in these patches, I wrote.

Quoted 7 lines

Quoted 2 lines
Ah, ok, I wasn't aware that that was what your intention was. In that case, once the Dreamcast fallout is fixed, I'll merge these.
Just come across this. I am happy to test any new patch on the Dreamcast once it's done. Just let me know and kick me if I don't respond.

The updated version of this is merged now, so please see if there are any regressions in the current git tree.

Adrian McMenamin

2009-03-14 01:12 UTC #7 lore raw

In reply to Nobuhiro Iwamatsu

Quoted 16 lines · Paul Mundt

Quoted 15 lines · Adrian McMenamin
2009/3/10 Paul Mundt <[email protected]>:
Quoted 3 lines · Nobuhiro Iwamatsu
Quoted 2 lines
Quoted 1 line · Paul Mundt
On Tue, Mar 10, 2009 at 01:48:14PM +0900, Nobuhiro Iwamatsu wrote:
...
Quoted 6 lines
Quoted 4 lines
I see.
I have already been writing the driver of DMAengine, and I am testing. To make old DMA-API coexist with dma engine in these patches, I wrote.
Ah, ok, I wasn't aware that that was what your intention was. In that case, once the Dreamcast fallout is fixed, I'll merge these.

Quoted 6 lines

Quoted 3 lines
Just come across this. I am happy to test any new patch on the Dreamcast once it's done. Just let me know and kick me if I don't respond.
The updated version of this is merged now, so please see if there are any regressions in the current git tree.

Doesn't work I'm afraid:

[    0.000000] Linux version 2.6.29-rc7-00215-g600fa57 (adrian@bossclass) (gcc version 4.2.2) #1 PREEMPT Sat Mar 14 00:53:47 GMT 2009
[    0.000000] Boot params:
[    0.000000] ... MOUNT_ROOT_RDONLY - 91f0c75f
[    0.000000] ... RAMDISK_FLAGS     - e1ff3018
[    0.000000] ... ORIG_ROOT_DEV     - 89093610
[    0.000000] ... LOADER_TYPE       - 3612e108
[    0.000000] ... INITRD_START      - 46088904
[    0.000000] ... INITRD_SIZE       - 6002306c
[    0.000000] console [sercon0] enabled
[    0.000000] Booting machvec: Sega Dreamcast
[    0.000000] Node 0: start_pfn = 0xc000, low = 0xd000
[    0.000000] Zone PFN ranges:
[    0.000000]   Normal   0x0000c000 -> 0x0000d000
[    0.000000] Movable zone start PFN for each node
[    0.000000] early_node_map[1] active PFN ranges
[    0.000000]     0: 0x0000c000 -> 0x0000d000
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 4064
[    0.000000] Kernel command line: root=/dev/nfs rw nfsroot2.168.61.50:/home/adrian/debdist ip=dhcp earlyprintk=serial video=pvr2fb:640x480-32@60 console=ttySC1 panic=7
[    0.000000] PID hash table entries: 64 (order: 6, 256 bytes)
[    0.000000] Using tmu for system timer
[    0.004322] Console: colour dummy device 80x25
[    0.009399] Dentry cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.016935] Inode-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.026888] Memory: 12400k/16384k available (2456k kernel code, 623k data, 124k init)
[    0.035501] PVR0205c1 CVR000000 PRR000000
[    0.040841] I-cache : n_ways=1 n_sets%6 way_incr�92
[    0.046567] I-cache : entry_mask=0x00001fe0 alias_mask=0x00001000 n_aliases=2
[    0.054406] D-cache : n_ways=1 n_setsQ2 way_incr384
[    0.060231] D-cache : entry_mask=0x00003fe0 alias_mask=0x00003000 n_aliases=4
[    0.068538] SLUB: Genslabs, HWalign2, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[    0.077089] Calibrating delay loop (skipped)... 199.50 BogoMIPS PRESET (lpj99012)
[    0.086987] Mount-cache hash table entries: 512
[    0.097040] CPU: SH7750
[    0.128986] net_namespace: 296 bytes
[    0.134762] NET: Registered protocol family 16
[    0.266443] bio: create slab <bio-0> at 0
[    0.292390] DMA: Registering DMA API.
[    0.297156] DMAC Address Error0 request_irq fail
[    0.302362] Fault in unaligned fixup: 0000 [#1]
[    0.307267] Modules linked in:
[    0.310696] 
[    0.312257] Pid : 1, Comm:           swapper
[    0.316168] CPU : 0                  Not tainted  (2.6.29-rc7-00215-g600fa57 #1)
[    0.316197] 
[    0.325248] PC is at request_dma+0x2c/0xc0
[    0.329693] PR is at request_dma+0x1e/0xc0
[    0.334162] PC  : 8c1c40cc SP  : 8cc1ff00 SR  : 400001f1 TEA : 0000001a
[    0.341421] R0  : 00000000 R1  : 40000101 R2  : 8c2feb94 R3  : 8c2feb94
[    0.348673] R4  : 00000002 R5  : 8c2bed08 R6  : 8cc47c58 R7  : 00000000
[    0.355926] R8  : ffffffea R9  : 00000000 R10 : 8c2bed08 R11 : 00000000
[    0.363165] R12 : 8c315500 R13 : 8c323064 R14 : 8cc1ff00
[    0.368990] MACH: 00000000 MACL: 00000a80 GBR : 00000000 PR  : 8c1c40be
[    0.376220] 
[    0.376234] Call trace:
[    0.380641] [<8c315516>] pvr2_dma_init+0x16/0x40
[    0.385669] [<8c002060>] do_one_initcall+0x0/0x1a0
[    0.390912] [<8c00208c>] do_one_initcall+0x2c/0x1a0
[    0.396261] [<8c04d1ee>] register_irq_proc+0x6e/0xc0
[    0.401696] [<8c04d27a>] init_irq_proc+0x3a/0x80
[    0.406753] [<8c04d180>] register_irq_proc+0x0/0xc0
[    0.412094] [<8c04a040>] irq_to_desc+0x0/0x40
[    0.416863] [<8c304528>] kernel_init+0x68/0x120
[    0.421908] [<8c002060>] do_one_initcall+0x0/0x1a0
[    0.427122] [<8c003c88>] kernel_thread_helper+0x8/0x20
[    0.432760] [<8c3044c0>] kernel_init+0x0/0x120
[    0.437621] [<8c003c80>] kernel_thread_helper+0x0/0x20
[    0.443317] 
[    0.444873] Code:
[    0.446971]   8c1c40c6:  ldc       r0, sr
[    0.451456]   8c1c40c8:  mov       r1, r0
[    0.455911]   8c1c40ca:  and       #-16, r0
[    0.460557] ->8c1c40cc:  mov.l     @(48,r8), r9
[    0.465623]   8c1c40ce:  mov       #1, r1
[    0.470090]   8c1c40d0:  tst       r0, r0
[    0.474580]   8c1c40d2:  mov.l     r1, @(48,r8)
[    0.479644]   8c1c40d4:  bt        8c1c40e0
[    0.484259]   8c1c40d6:  and       #-16, r0
[    0.488887] 
[    0.490453] Process: swapper (pid: 1, stack limit = 8cc1e001)
[    0.496744] Stack: (0x8cc1ff00 to 0x8cc20000)
[    0.501503] ff00: 8c315516 8cc1ff18 8c321718 8c32148c 8c002060 8c321530 8c00208c 8cc1ff20 
[    0.510632] ff20: 00000001 00000000 8c32ba48 8cc1fef8 8cc47600 8cc46d20 8c04d1ee 8cc1ff48 
[    0.519864] ff40: 8c2ee0a4 8cc1ff4a 3431ff14 00000032 00000000 8c04d27a 8cc1ff6c 8c04d180 
[    0.529019] ff60: 8c04a040 8c304528 8cc1ff84 00000000 00000000 8c321718 8c32148c 8c002060 
[    0.538237] ff80: 8c321530 8c003c88 8cc1ff9c 00000000 00000000 00000000 00000000 00000000 
[    0.547379] ffa0: 00000000 00000000 00000000 00000000 00000000 00000000 8c3044c0 00000000 
[    0.556470] ffc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 
[    0.565759] ffe0: 8cc1ffa4 8c003c80 00000000 40000000 00000000 00000000 00000000 00000000 
[    0.575044] ---[ end trace 4eaa2a86a8e2da22 ]---
[    0.580220] Kernel panic - not syncing: Attempted to kill init!
[    0.586833] Rebooting in 7 seconds..

0x8c1c40cc corresponds to arch/sh/include/asm/cmpxchg-irq.h:9

0x8c1c40be is arch/sh/drivers/dma/dma-api.c:198

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Nobuhiro Iwamatsu

2009-03-16 02:18 UTC #8 lore raw

In reply to Nobuhiro Iwamatsu

Hi, Adrian.

Thank you for your test!.

2009/3/14 Adrian McMenamin <[email protected]>:

Quoted 120 lines · Paul Mundt

Quoted 16 lines · Adrian McMenamin
Quoted 15 lines
2009/3/10 Paul Mundt <[email protected]>:
Quoted 3 lines · Nobuhiro Iwamatsu
Quoted 2 lines
Quoted 1 line · Paul Mundt
On Tue, Mar 10, 2009 at 01:48:14PM +0900, Nobuhiro Iwamatsu wrote:
...
Quoted 6 lines
Quoted 4 lines
I see.
I have already been writing the driver of DMAengine, and I am testing. To make old DMA-API coexist with dma engine in these patches, I wrote.
Ah, ok, I wasn't aware that that was what your intention was. In that case, once the Dreamcast fallout is fixed, I'll merge these.
Quoted 6 lines
Quoted 3 lines
Just come across this. I am happy to test any new patch on the Dreamcast once it's done. Just let me know and kick me if I don't respond.
The updated version of this is merged now, so please see if there are any regressions in the current git tree.
Doesn't work I'm afraid:
[ 0.000000] Linux version 2.6.29-rc7-00215-g600fa57 (adrian@bossclass) (gcc version 4.2.2) #1 PREEMPT Sat Mar 14 00:53:47 GMT 2009
[ 0.000000] Boot params:
[ 0.000000] ... MOUNT_ROOT_RDONLY - 91f0c75f
[ 0.000000] ... RAMDISK_FLAGS - e1ff3018
[ 0.000000] ... ORIG_ROOT_DEV - 89093610
[ 0.000000] ... LOADER_TYPE - 3612e108
[ 0.000000] ... INITRD_START - 46088904
[ 0.000000] ... INITRD_SIZE - 6002306c
[ 0.000000] console [sercon0] enabled
[ 0.000000] Booting machvec: Sega Dreamcast
[ 0.000000] Node 0: start_pfn = 0xc000, low = 0xd000
[ 0.000000] Zone PFN ranges:
[ 0.000000] Normal 0x0000c000 -> 0x0000d000
[ 0.000000] Movable zone start PFN for each node
[ 0.000000] early_node_map[1] active PFN ranges
[ 0.000000] 0: 0x0000c000 -> 0x0000d000
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 4064
[ 0.000000] Kernel command line: root=/dev/nfs rw nfsroot2.168.61.50:/home/adrian/debdist ip=dhcp earlyprintk=serial video=pvr2fb:640x480-32@60 console=ttySC1 panic=7 [ 0.000000] PID hash table entries: 64 (order: 6, 256 bytes)
[ 0.000000] Using tmu for system timer
[ 0.004322] Console: colour dummy device 80x25
[ 0.009399] Dentry cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.016935] Inode-cache hash table entries: 1024 (order: 0, 4096 bytes)
[ 0.026888] Memory: 12400k/16384k available (2456k kernel code, 623k data, 124k init)
[ 0.035501] PVR0205c1 CVR000000 PRR000000
[ 0.040841] I-cache : n_ways=1 n_sets%6 way_incr�92
[ 0.046567] I-cache : entry_mask=0x00001fe0 alias_mask=0x00001000 n_aliases=2
[ 0.054406] D-cache : n_ways=1 n_setsQ2 way_incr384
[ 0.060231] D-cache : entry_mask=0x00003fe0 alias_mask=0x00003000 n_aliases=4
[ 0.068538] SLUB: Genslabs, HWalign2, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[ 0.077089] Calibrating delay loop (skipped)... 199.50 BogoMIPS PRESET (lpj99012)
[ 0.086987] Mount-cache hash table entries: 512
[ 0.097040] CPU: SH7750
[ 0.128986] net_namespace: 296 bytes
[ 0.134762] NET: Registered protocol family 16
[ 0.266443] bio: create slab <bio-0> at 0
[ 0.292390] DMA: Registering DMA API.
[ 0.297156] DMAC Address Error0 request_irq fail
[ 0.302362] Fault in unaligned fixup: 0000 [#1]
[ 0.307267] Modules linked in:
[ 0.310696]
[ 0.312257] Pid : 1, Comm: swapper
[ 0.316168] CPU : 0 Not tainted (2.6.29-rc7-00215-g600fa57 #1)
[ 0.316197]
[ 0.325248] PC is at request_dma+0x2c/0xc0
[ 0.329693] PR is at request_dma+0x1e/0xc0
[ 0.334162] PC : 8c1c40cc SP : 8cc1ff00 SR : 400001f1 TEA : 0000001a
[ 0.341421] R0 : 00000000 R1 : 40000101 R2 : 8c2feb94 R3 : 8c2feb94
[ 0.348673] R4 : 00000002 R5 : 8c2bed08 R6 : 8cc47c58 R7 : 00000000
[ 0.355926] R8 : ffffffea R9 : 00000000 R10 : 8c2bed08 R11 : 00000000
[ 0.363165] R12 : 8c315500 R13 : 8c323064 R14 : 8cc1ff00
[ 0.368990] MACH: 00000000 MACL: 00000a80 GBR : 00000000 PR : 8c1c40be
[ 0.376220]
[ 0.376234] Call trace:
[ 0.380641] [<8c315516>] pvr2_dma_init+0x16/0x40
[ 0.385669] [<8c002060>] do_one_initcall+0x0/0x1a0
[ 0.390912] [<8c00208c>] do_one_initcall+0x2c/0x1a0
[ 0.396261] [<8c04d1ee>] register_irq_proc+0x6e/0xc0
[ 0.401696] [<8c04d27a>] init_irq_proc+0x3a/0x80
[ 0.406753] [<8c04d180>] register_irq_proc+0x0/0xc0
[ 0.412094] [<8c04a040>] irq_to_desc+0x0/0x40
[ 0.416863] [<8c304528>] kernel_init+0x68/0x120
[ 0.421908] [<8c002060>] do_one_initcall+0x0/0x1a0
[ 0.427122] [<8c003c88>] kernel_thread_helper+0x8/0x20
[ 0.432760] [<8c3044c0>] kernel_init+0x0/0x120
[ 0.437621] [<8c003c80>] kernel_thread_helper+0x0/0x20
[ 0.443317]
[ 0.444873] Code:
[ 0.446971] 8c1c40c6: ldc r0, sr
[ 0.451456] 8c1c40c8: mov r1, r0
[ 0.455911] 8c1c40ca: and #-16, r0
[ 0.460557] ->8c1c40cc: mov.l @(48,r8), r9
[ 0.465623] 8c1c40ce: mov #1, r1
[ 0.470090] 8c1c40d0: tst r0, r0
[ 0.474580] 8c1c40d2: mov.l r1, @(48,r8)
[ 0.479644] 8c1c40d4: bt 8c1c40e0
[ 0.484259] 8c1c40d6: and #-16, r0
[ 0.488887]
[ 0.490453] Process: swapper (pid: 1, stack limit = 8cc1e001)
[ 0.496744] Stack: (0x8cc1ff00 to 0x8cc20000)
[ 0.501503] ff00: 8c315516 8cc1ff18 8c321718 8c32148c 8c002060 8c321530 8c00208c 8cc1ff20
[ 0.510632] ff20: 00000001 00000000 8c32ba48 8cc1fef8 8cc47600 8cc46d20 8c04d1ee 8cc1ff48
[ 0.519864] ff40: 8c2ee0a4 8cc1ff4a 3431ff14 00000032 00000000 8c04d27a 8cc1ff6c 8c04d180
[ 0.529019] ff60: 8c04a040 8c304528 8cc1ff84 00000000 00000000 8c321718 8c32148c 8c002060
[ 0.538237] ff80: 8c321530 8c003c88 8cc1ff9c 00000000 00000000 00000000 00000000 00000000
[ 0.547379] ffa0: 00000000 00000000 00000000 00000000 00000000 00000000 8c3044c0 00000000
[ 0.556470] ffc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 0.565759] ffe0: 8cc1ffa4 8c003c80 00000000 40000000 00000000 00000000 00000000 00000000
[ 0.575044] ---[ end trace 4eaa2a86a8e2da22 ]---
[ 0.580220] Kernel panic - not syncing: Attempted to kill init!
[ 0.586833] Rebooting in 7 seconds..

Quoted 3 lines

0x8c1c40cc corresponds to arch/sh/include/asm/cmpxchg-irq.h:9
0x8c1c40be is arch/sh/drivers/dma/dma-api.c:198

This is because DMA-api of sh775x does not support multi-irq. I will send a patch to revise.

Best regards,
Nobuhiro

Signature · 5 lines

Nobuhiro Iwamatsu
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