mpc5200: support for the MAN mpc5200 based board mucmc52

PATCH In review Heiko Schocher 3 participants 21 messages Sep 14, 2009 – Oct 8, 2009

Subsystems (3)

Device tree bindings PowerPC Linux for PowerPC embedded MPC5XXX

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Heiko Schocher

author

2009-09-14 07:50 UTC #0 lore raw

PATCH 1/1 mpc5200: support for the MAN mpc5200 based board mucmc52

- serial Console on PSC1
- 64MB SDRAM
- MTD CFI Flash
- Ethernet FEC
- I2C with PCF8563 and Temp. Sensor ADM9240
- IDE support

Signed-off-by Heiko Schocher <[email protected]>

---
- based on:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git next

- checked with:

$ ./scripts/checkpatch.pl 0001-mpc5200-support-for-the-MAN-mpc5200-based-board-muc.patch
total: 0 errors, 0 warnings, 1714 lines checked

0001-mpc5200-support-for-the-MAN-mpc5200-based-board-muc.patch has no obvious style problems and is ready for submission. $

 arch/powerpc/boot/dts/mucmc52.dts            |  231 ++++
 arch/powerpc/configs/52xx/mucmc52_defconfig  | 1476 ++++++++++++++++++++++++++
 arch/powerpc/platforms/52xx/mpc5200_simple.c |    1 +
 3 files changed, 1708 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/mucmc52.dts
 create mode 100644 arch/powerpc/configs/52xx/mucmc52_defconfig

arch/powerpc/boot/dts/mucmc52.dts new file +231 -0

new file mode 100644
index 0000000..a4a7a20
@@ -0,0 +1,231 @@
+/*
+ * mucmc52 board Device Tree Source
+ *
+ * Copyright (C) 2009 DENX Software Engineering GmbH
+ * Heiko Schocher <[email protected]>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+	model = "man,mucmc52";
+	compatible = "man,mucmc52";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&mpc5200_pic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,5200@0 {
+			device_type = "cpu";
+			reg = <0>;
+			d-cache-line-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x4000>;	// L1, 16K
+			i-cache-size = <0x4000>;	// L1, 16K
+			timebase-frequency = <0>;	// from bootloader
+			bus-frequency = <0>;		// from bootloader
+			clock-frequency = <0>;		// from bootloader
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x04000000>;	// 64MB
+	};
+
+	soc5200@f0000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fsl,mpc5200-immr";
+		ranges = <0 0xf0000000 0x0000c000>;
+		reg = <0xf0000000 0x00000100>;
+		bus-frequency = <0>;		// from bootloader
+		system-frequency = <0>;		// from bootloader
+
+		cdm@200 {
+			compatible = "fsl,mpc5200-cdm";
+			reg = <0x200 0x38>;
+		};
+
+		mpc5200_pic: interrupt-controller@500 {
+			// 5200 interrupts are encoded into two levels;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			compatible = "fsl,mpc5200-pic";
+			reg = <0x500 0x80>;
+		};
+
+		timer@600 {	// General Purpose Timer
+			compatible = "fsl,mpc5200-gpt";
+			reg = <0x600 0x10>;
+			interrupts = <1 9 0>;
+			gpio-controller;
+		};
+
+		gpio_simple: gpio@b00 {
+			compatible = "fsl,mpc5200-gpio";
+			reg = <0xb00 0x40>;
+			interrupts = <1 7 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		dma-controller@1200 {
+			device_type = "dma-controller";
+			compatible = "fsl,mpc5200-bestcomm";
+			reg = <0x1200 0x80>;
+			interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
+			              3 4 0  3 5 0  3 6 0  3 7 0
+			              3 8 0  3 9 0  3 10 0  3 11 0
+			              3 12 0  3 13 0  3 14 0  3 15 0>;
+		};
+
+		xlb@1f00 {
+			compatible = "fsl,mpc5200-xlb";
+			reg = <0x1f00 0x100>;
+		};
+
+		serial@2000 {		// PSC1
+			compatible = "fsl,mpc5200-psc-uart";
+			reg = <0x2000 0x100>;
+			interrupts = <2 1 0>;
+		};
+
+		serial@2200 {		// PSC2
+			compatible = "fsl,mpc5200-psc-uart";
+			reg = <0x2200 0x100>;
+			interrupts = <2 2 0>;
+		};
+
+		serial@2c00 {		// PSC6
+			compatible = "fsl,mpc5200-psc-uart";
+			reg = <0x2c00 0x100>;
+			interrupts = <2 6 0>;
+		};
+
+		ethernet@3000 {
+			compatible = "fsl,mpc5200-fec";
+			reg = <0x3000 0x400>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <2 5 0>;
+			phy-handle = <&phy0>;
+		};
+
+		mdio@3000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,mpc5200-mdio";
+			reg = <0x3000 0x400>;       // fec range, since we need to setup fec interrupts
+			interrupts = <2 5 0>;   // these are for "mii command finished", not link changes & co.
+
+			phy0: ethernet-phy@0 {
+				reg = <0>;
+			};
+		};
+
+		ata@3a00 {
+			compatible = "fsl,mpc5200-ata";
+			reg = <0x3a00 0x100>;
+			interrupts = <2 7 0>;
+		};
+
+		i2c@3d40 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,mpc5200-i2c","fsl-i2c";
+			reg = <0x3d40 0x40>;
+			interrupts = <2 16 0>;
+			fsl5200-clocking;
+
+			hwmon@2c {
+				compatible = "ad,adm9240";
+				reg = <0x2c>;
+			};
+			rtc@51 {
+				compatible = "rtc,pcf8563";
+				reg = <0x51>;
+			};
+		};
+
+		sram@8000 {
+			compatible = "fsl,mpc5200-sram";
+			reg = <0x8000 0x4000>;
+		};
+	};
+
+	localbus {
+		compatible = "fsl,mpc5200-lpb","simple-bus";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges = <0 0 0xff800000 0x00800000>;
+
+		flash@0,0 {
+			compatible = "cfi-flash";
+			reg = <0 0 0x00800000>;
+			bank-width = <4>;
+			device-width = <2>;
+			#size-cells = <1>;
+			#address-cells = <1>;
+			partition@0 {
+				label = "DTS";
+				reg = <0x0 0x00100000>;
+			};
+			partition@100000 {
+				label = "Kernel";
+				reg = <0x100000 0x00200000>;
+			};
+			partition@300000 {
+				label = "RootFS";
+				reg = <0x00300000 0x00200000>;
+			};
+			partition@500000 {
+				label = "user";
+				reg = <0x00500000 0x00200000>;
+			};
+			partition@700000 {
+				label = "U-Boot";
+				reg = <0x00700000 0x00040000>;
+			};
+			partition@740000 {
+				label = "Env";
+				reg = <0x00740000 0x00020000>;
+			};
+			partition@760000 {
+				label = "red. Env";
+				reg = <0x00760000 0x00020000>;
+			};
+			partition@780000 {
+				label = "reserve";
+				reg = <0x00780000 0x00080000>;
+			};
+		};
+	};
+
+	pci@f0000d00 {
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		device_type = "pci";
+		compatible = "fsl,mpc5200-pci";
+		reg = <0xf0000d00 0x100>;
+		interrupt-map-mask = <0xf800 0 0 7>;
+		interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
+				 0xc000 0 0 2 &mpc5200_pic 0 0 3
+				 0xc000 0 0 3 &mpc5200_pic 0 0 3
+				 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
+		clock-frequency = <0>; // From boot loader
+		interrupts = <2 8 0 2 9 0 2 10 0>;
+		bus-range = <0 0>;
+		ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
+			  0x02000000 0 0x90000000 0x90000000 0 0x10000000
+			  0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
+	};
+};

arch/powerpc/configs/52xx/mucmc52_defconfig new file +1476 -0

1,476 lines not on this page · raw message

arch/powerpc/platforms/52xx/mpc5200_simple.c +1 -0

index c31e5b5..7794bd8 100644
@@ -51,6 +51,7 @@ static void __init mpc5200_simple_setup_arch(void)
 /* list of the supported boards */
 static char *board[] __initdata = {
 	"intercontrol,digsy-mtc",
+	"man,mucmc52",
 	"phytec,pcm030",
 	"phytec,pcm032",
 	"promess,motionpro",

Signature · 5 lines

1.6.0.6

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Wolfram Sang

2009-09-14 08:03 UTC #1 lore raw

Hi,

arch/powerpc/boot/dts/mucmc52.dts line 59

Quoted 2 lines

arch/powerpc/boot/dts/mucmc52.dts new file +2 -0
+		mpc5200_pic: interrupt-controller@500 {
+			// 5200 interrupts are encoded into two levels;

Grant, maybe this comment could be dropped also for the in-kernel dts-files? I think it is sufficently described in mpc5200.txt. I could prepare a patch if you agree.

arch/powerpc/boot/dts/mucmc52.dts line 146

Quoted 7 lines

arch/powerpc/boot/dts/mucmc52.dts new file +7 -0

+		i2c@3d40 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,mpc5200-i2c","fsl-i2c";
+			reg = <0x3d40 0x40>;
+			interrupts = <2 16 0>;
+			fsl5200-clocking;

Please drop the clocking-line. It became obsolete.

Regards,

Wolfram

Signature · 2 lines

Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

Heiko Schocher

author

2009-09-14 13:55 UTC #2 lore raw

Hello Wolfram,

Quoted 9 lines · Wolfram Sang

Hi,
arch/powerpc/boot/dts/mucmc52.dts line 59
Quoted 2 lines
arch/powerpc/boot/dts/mucmc52.dts new file +2 -0
+		mpc5200_pic: interrupt-controller@500 {
+			// 5200 interrupts are encoded into two levels;
Grant, maybe this comment could be dropped also for the in-kernel dts-files? I think it is sufficently described in mpc5200.txt. I could prepare a patch if you agree.

Quoted 9 lines

arch/powerpc/boot/dts/mucmc52.dts line 146
Quoted 7 lines
arch/powerpc/boot/dts/mucmc52.dts new file +7 -0
+		i2c@3d40 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,mpc5200-i2c","fsl-i2c";
+			reg = <0x3d40 0x40>;
+			interrupts = <2 16 0>;
+			fsl5200-clocking;
Please drop the clocking-line. It became obsolete.

OK, I fix this.

Thanks for reviewing

bye
Heiko

Signature · 2 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Grant Likely

2009-09-14 14:46 UTC #3 lore raw

In reply to Wolfram Sang

On Mon, Sep 14, 2009 at 2:03 AM, Wolfram Sang <[email protected]> wrote= :

Quoted 4 lines

Hi,
Quoted 2 lines
+ =A0 =A0 =A0 =A0 =A0 =A0 mpc5200_pic: interrupt-controller@500 {
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 // 5200 interrupts are encoded=

into two levels;

Quoted 2 lines

Grant, maybe this comment could be dropped also for the in-kernel dts-fil=

es? I

Quoted 1 line

think it is sufficently described in mpc5200.txt. I could prepare a patch=

Quoted 1 line

you agree.

Meh. I don't mind it being there. Interrupt encoding is confusing enough as is for people unfamiliar with the device tree, that any additional hints are a plus. In fact, if you want to prepare a patch, instead of removing this comment, replace it with one that tells readers where to look for the encoding documentation.

Cheers,
g.

--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Heiko Schocher

author

2009-10-05 07:05 UTC #4 lore raw

PATCH v2 1/1 mpc5200: support for the MAN mpc5200 based board uc101

- serial Console on PSC1
- 64MB SDRAM
- MTD CFI Flash
- Ethernet FEC
- IDE support

Signed-off-by Heiko Schocher <[email protected]>

---
- based on:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git next

- checked with:

$ ./scripts/checkpatch.pl 0001-mpc5200-support-for-the-MAN-mpc5200-based-board-uc1.patch
total: 0 errors, 0 warnings, 324 lines checked

0001-mpc5200-support-for-the-MAN-mpc5200-based-board-uc1.patch has no obvious style problems and is ready for submission. $

changes since v1:

- add comments from Grant Likely <[email protected]> use mpc5200_defconfig as default configuration
- add comments from Wolfram Sang <[email protected]>
- rebase against current next

 arch/powerpc/boot/dts/uc101.dts              |  317 ++++++++++++++++++++++++++
 arch/powerpc/platforms/52xx/mpc5200_simple.c |    1 +
 2 files changed, 318 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/uc101.dts

arch/powerpc/boot/dts/uc101.dts new file +317 -0

new file mode 100644
index 0000000..9d79e48
@@ -0,0 +1,317 @@
+/*
+ * uc101 board Device Tree Source
+ *
+ * Copyright (C) 2009 DENX Software Engineering GmbH
+ * Heiko Schocher <[email protected]>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+	model = "manroland,uc101";
+	compatible = "manroland,uc101";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&mpc5200_pic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,5200@0 {
+			device_type = "cpu";
+			reg = <0>;
+			d-cache-line-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x4000>;	// L1, 16K
+			i-cache-size = <0x4000>;	// L1, 16K
+			timebase-frequency = <0>;	// from bootloader
+			bus-frequency = <0>;		// from bootloader
+			clock-frequency = <0>;		// from bootloader
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x04000000>;	// 64MB
+	};
+
+	soc5200@f0000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fsl,mpc5200-immr",
+				"fsl,mpc5200b-immr";
+		ranges = <0 0xf0000000 0x0000c000>;
+		reg = <0xf0000000 0x00000100>;
+		bus-frequency = <0>;		// from bootloader
+		system-frequency = <0>;		// from bootloader
+
+		cdm@200 {
+			compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
+			reg = <0x200 0x38>;
+		};
+
+		mpc5200_pic: interrupt-controller@500 {
+			// 5200 interrupts are encoded into two levels;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
+			reg = <0x500 0x80>;
+			interrupts = <0 0 3>;
+		};
+
+		gpt0: timer@600 {	// GPT 0 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x600 0x10>;
+			interrupts = <1 9 0>;
+			gpio-controller;
+		};
+
+		gpt1: timer@610 {	// GPT 1 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x610 0x10>;
+			interrupts = <1 10 0>;
+			gpio-controller;
+		};
+
+		gpt2: timer@620 {	// GPT 2 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x620 0x10>;
+			interrupts = <1 11 0>;
+			gpio-controller;
+		};
+
+		gpt3: timer@630 {	// GPT 3 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x630 0x10>;
+			interrupts = <1 12 0>;
+			gpio-controller;
+		};
+
+		gpt4: timer@640 {	// GPT 4 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x640 0x10>;
+			interrupts = <1 13 0>;
+			gpio-controller;
+		};
+
+		gpt5: timer@650 {	// GPT 5 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x650 0x10>;
+			interrupts = <1 14 0>;
+			gpio-controller;
+		};
+
+		gpt6: timer@660 {	// GPT 6 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x660 0x10>;
+			interrupts = <1 15 0>;
+			gpio-controller;
+		};
+
+		gpt7: timer@670 {	// GPT 7 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x670 0x10>;
+			interrupts = <1 16 0>;
+			gpio-controller;
+		};
+
+		gpio_simple: gpio@b00 {
+			compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
+			reg = <0xb00 0x40>;
+			interrupts = <1 7 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpio_wkup: gpio@c00 {
+			compatible = "fsl,mpc5200b-gpio-wkup",
+					"fsl,mpc5200-gpio-wkup";
+			reg = <0xc00 0x40>;
+			interrupts = <1 8 0 0 3 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpio_sint: gpio_sint@b00 {
+			compatible = "fsl,mpc5200b-gpio-sint",
+					"fsl,mpc5200-gpio-sint";
+			reg = <0xb00 0x40>;
+			interrupts = <1 8 0 0 3 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		dma-controller@1200 {
+			device_type = "dma-controller";
+			compatible = "fsl,mpc5200b-bestcomm",
+					"fsl,mpc5200-bestcomm";
+			reg = <0x1200 0x80>;
+			interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
+			              3 4 0  3 5 0  3 6 0  3 7 0
+			              3 8 0  3 9 0  3 10 0  3 11 0
+			              3 12 0  3 13 0  3 14 0  3 15 0>;
+		};
+
+		xlb@1f00 {
+			compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
+			reg = <0x1f00 0x100>;
+		};
+
+		serial@2000 {		// PSC1
+			compatible = "fsl,mpc5200b-psc-uart",
+					"fsl,mpc5200-psc-uart";
+			reg = <0x2000 0x100>;
+			interrupts = <2 1 0>;
+		};
+
+		serial@2200 {		// PSC2
+			compatible = "fsl,mpc5200b-psc-uart",
+					"fsl,mpc5200-psc-uart";
+			reg = <0x2200 0x100>;
+			interrupts = <2 2 0>;
+		};
+
+		serial@2c00 {		// PSC6
+			compatible = "fsl,mpc5200b-psc-uart",
+					"fsl,mpc5200-psc-uart";
+			reg = <0x2c00 0x100>;
+			interrupts = <2 6 0>;
+		};
+
+		ethernet@3000 {
+			compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
+			reg = <0x3000 0x400>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <2 5 0>;
+			phy-handle = <&phy0>;
+		};
+
+		mdio@3000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
+			reg = <0x3000 0x400>;	// fec range, since we need to
+						// setup fec interrupts
+			interrupts = <2 5 0>;	// these are for "mii command
+						// finished", not link
+						// changes & co.
+
+			phy0: ethernet-phy@0 {
+				compatible = "intel,lxt971";
+				reg = <0>;
+			};
+		};
+
+		ata@3a00 {
+			compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
+			reg = <0x3a00 0x100>;
+			interrupts = <2 7 0>;
+		};
+
+		i2c@3d40 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c",
+					"fsl-i2c";
+			reg = <0x3d40 0x40>;
+			interrupts = <2 16 0>;
+			fsl,preserve-clocking;
+			clock-frequency = <400000>;
+
+			hwmon@2c {
+				compatible = "ad,adm9240";
+				reg = <0x2c>;
+			};
+			rtc@51 {
+				compatible = "nxp,pcf8563";
+				reg = <0x51>;
+			};
+		};
+
+		sram@8000 {
+			compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
+			reg = <0x8000 0x4000>;
+		};
+
+		wdt {
+			compatible = "generic,gpio-wdt";
+			reg = <0x600 0x10>;
+			gpios = <&gpt0 0 0>;
+			period = <500>;	// WDT trigger period in msec
+		};
+	};
+
+	localbus {
+		compatible = "fsl,mpc5200b-lpb","simple-bus";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges = <0 0 0xff800000 0x00800000
+			  1 0 0x80000000 0x00800000
+			  3 0 0x80000000 0x00800000>;
+
+		flash@0,0 {
+			compatible = "cfi-flash";
+			reg = <0 0 0x00800000>;
+			bank-width = <2>;
+			device-width = <2>;
+			#size-cells = <1>;
+			#address-cells = <1>;
+			partition@0 {
+				label = "DTS";
+				reg = <0x0 0x00100000>;
+			};
+			partition@100000 {
+				label = "Kernel";
+				reg = <0x100000 0x00200000>;
+			};
+			partition@300000 {
+				label = "RootFS";
+				reg = <0x00300000 0x00200000>;
+			};
+
+			partition@500000 {
+				label = "user";
+				reg = <0x00500000 0x00200000>;
+			};
+			partition@700000 {
+				label = "U-Boot";
+				reg = <0x00700000 0x00040000>;
+			};
+			partition@740000 {
+				label = "Env";
+				reg = <0x00740000 0x00010000>;
+			};
+			partition@750000 {
+				label = "red. Env";
+				reg = <0x00750000 0x00010000>;
+			};
+			partition@760000 {
+				label = "reserve";
+				reg = <0x00760000 0x000a0000>;
+			};
+		};
+
+	};
+};

arch/powerpc/platforms/52xx/mpc5200_simple.c +1 -0

index c31e5b5..caf6d92 100644
@@ -51,6 +51,7 @@ static void __init mpc5200_simple_setup_arch(void)
 /* list of the supported boards */
 static char *board[] __initdata = {
 	"intercontrol,digsy-mtc",
+	"manroland,uc101",
 	"phytec,pcm030",
 	"phytec,pcm032",
 	"promess,motionpro",

Signature · 5 lines

1.6.0.6

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Wolfram Sang

2009-10-05 09:53 UTC #5 lore raw

Re: [PATCH v2] mpc5200: support for the MAN mpc5200 based board uc101

Quoted 30 lines · Heiko Schocher

- serial Console on PSC1
- 64MB SDRAM
- MTD CFI Flash
- Ethernet FEC
- IDE support
Signed-off-by Heiko Schocher <[email protected]>
---
- based on:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git next
- checked with:
$ ./scripts/checkpatch.pl 0001-mpc5200-support-for-the-MAN-mpc5200-based-board-uc1.patch
total: 0 errors, 0 warnings, 324 lines checked
0001-mpc5200-support-for-the-MAN-mpc5200-based-board-uc1.patch has no obvious style problems and is ready for submission. $
changes since v1:
- add comments from Grant Likely <[email protected]> use mpc5200_defconfig as default configuration
- add comments from Wolfram Sang <[email protected]>
- rebase against current next
 arch/powerpc/boot/dts/uc101.dts              |  317 ++++++++++++++++++++++++++
 arch/powerpc/platforms/52xx/mpc5200_simple.c |    1 +
 2 files changed, 318 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/uc101.dts

[...]

arch/powerpc/boot/dts/uc101.dts line 263

Quoted 6 lines

arch/powerpc/boot/dts/uc101.dts new file +6 -0

+		wdt {
+			compatible = "generic,gpio-wdt";
+			reg = <0x600 0x10>;
+			gpios = <&gpt0 0 0>;
+			period = <500>;	// WDT trigger period in msec
+		};

Is this an official binding? I also did an gpio-watchdog a while ago and there were some issues with the binding, IIRC. Would be nice if this has been solved meanwhile.

Other than that, it looks okay to me.

Regards,

Wolfram

Signature · 2 lines

Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

Heiko Schocher

author

2009-10-05 10:13 UTC #6 lore raw

Re: [PATCH v2] mpc5200: support for the MAN mpc5200 based board uc101

Hello Wolfram,

Quoted 9 lines · Wolfram Sang

Quoted 7 lines · Heiko Schocher
- serial Console on PSC1
- 64MB SDRAM
- MTD CFI Flash
- Ethernet FEC
- IDE support
Signed-off-by Heiko Schocher <[email protected]>

[...]

Quoted 11 lines

[...]
arch/powerpc/boot/dts/uc101.dts line 263
Quoted 6 lines
arch/powerpc/boot/dts/uc101.dts new file +6 -0
+		wdt {
+			compatible = "generic,gpio-wdt";
+			reg = <0x600 0x10>;
+			gpios = <&gpt0 0 0>;
+			period = <500>;	// WDT trigger period in msec
+		};
Is this an official binding? I also did an gpio-watchdog a while ago and there were some issues with the binding, IIRC. Would be nice if this has been solved meanwhile.

Oh, sorry, no. I remove it.

Quoted 1 line

Other than that, it looks okay to me.

Ok, thanks for reviewing, I resent soon an update

bye
Heiko

Signature · 2 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Grant Likely

2009-10-05 13:47 UTC #7 lore raw

Re: [PATCH v2] mpc5200: support for the MAN mpc5200 based board uc101

Quoted 6 lines · Heiko Schocher

Quoted 3 lines · Wolfram Sang
Is this an official binding? I also did an gpio-watchdog a while ago and there were some issues with the binding, IIRC. Would be nice if this has been solved meanwhile.
Oh, sorry, no. I remove it.

You don't need to remove it, but choose a compatible value within the board/manufacturer namespace. ie. 'manroland,uc101-watchdog'. You also need to document what it means in Documentation/powerpc/dts-bindings/. If you do want to do some kind of generic gpio watchdog binding, then write a documentation patch for it and post it to devicetree-discuss for review. Make sure you cc:
both me and Wolfram when you post it.

Cheers,
g.

Signature · 2 lines

Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Heiko Schocher

author

2009-10-06 05:29 UTC #8 lore raw

Re: [PATCH v2] mpc5200: support for the MAN mpc5200 based board uc101

Hello Grant,

Quoted 9 lines · Grant Likely

Quoted 5 lines · Heiko Schocher
Quoted 3 lines · Wolfram Sang
Is this an official binding? I also did an gpio-watchdog a while ago and there were some issues with the binding, IIRC. Would be nice if this has been solved meanwhile.
Oh, sorry, no. I remove it.
You don't need to remove it, but choose a compatible value within the board/manufacturer namespace. ie. 'manroland,uc101-watchdog'. You

Hmm.. currently I prefer to remove it, because it is not a uc101 special wdt driver. When this wdt driver go in mainline, it is easy to readd it to this board support.

bye,
Heiko

Signature · 2 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Wolfram Sang

2009-10-06 08:06 UTC #9 lore raw

Re: [PATCH v2] mpc5200: support for the MAN mpc5200 based board uc101

Quoted 4 lines

Hmm.. currently I prefer to remove it, because it is not a uc101 special wdt driver. When this wdt driver go in mainline, it is easy to readd it to this board support.

Great, another one interested in a mainline GPIO-WDT-driver :) I'll check again what happened last time and summarize it later this day. The we can hopefully work out something.

Signature · 2 lines

Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

Heiko Schocher

author

2009-10-07 06:57 UTC #10 lore raw

PATCH v3 1/1 mpc5200: support for the MAN mpc5200 based board uc101

In reply to Grant Likely

- serial Console on PSC1
- 64MB SDRAM
- MTD CFI Flash
- Ethernet FEC
- I2C with PCF8563 and Temp. Sensor ADM9240
- IDE support

Signed-off-by Heiko Schocher <[email protected]>

---

- based on:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git next

- checked with:

$ ./scripts/checkpatch.pl 0001-mpc5200-support-for-the-MAN-mpc5200-based-board-uc1.patch
total: 0 errors, 0 warnings, 317 lines checked

0001-mpc5200-support-for-the-MAN-mpc5200-based-board-uc1.patch has no obvious style problems and is ready for submission. $

changes since v1:

- add comments from Grant Likely <[email protected]> use mpc5200_defconfig as default configuration
- add comments from Wolfram Sang <[email protected]>
- rebase against current next

changes since v2:
- add comment from Wolfram Sang
remove unofficial binding

 arch/powerpc/boot/dts/uc101.dts              |  310 ++++++++++++++++++++++++++
 arch/powerpc/platforms/52xx/mpc5200_simple.c |    1 +
 2 files changed, 311 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/uc101.dts

arch/powerpc/boot/dts/uc101.dts new file +310 -0

new file mode 100644
index 0000000..bfb8dd9
@@ -0,0 +1,310 @@
+/*
+ * uc101 board Device Tree Source
+ *
+ * Copyright (C) 2009 DENX Software Engineering GmbH
+ * Heiko Schocher <[email protected]>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+	model = "manroland,uc101";
+	compatible = "manroland,uc101";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&mpc5200_pic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,5200@0 {
+			device_type = "cpu";
+			reg = <0>;
+			d-cache-line-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x4000>;	// L1, 16K
+			i-cache-size = <0x4000>;	// L1, 16K
+			timebase-frequency = <0>;	// from bootloader
+			bus-frequency = <0>;		// from bootloader
+			clock-frequency = <0>;		// from bootloader
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x04000000>;	// 64MB
+	};
+
+	soc5200@f0000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fsl,mpc5200-immr",
+				"fsl,mpc5200b-immr";
+		ranges = <0 0xf0000000 0x0000c000>;
+		reg = <0xf0000000 0x00000100>;
+		bus-frequency = <0>;		// from bootloader
+		system-frequency = <0>;		// from bootloader
+
+		cdm@200 {
+			compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
+			reg = <0x200 0x38>;
+		};
+
+		mpc5200_pic: interrupt-controller@500 {
+			// 5200 interrupts are encoded into two levels;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
+			reg = <0x500 0x80>;
+			interrupts = <0 0 3>;
+		};
+
+		gpt0: timer@600 {	// GPT 0 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x600 0x10>;
+			interrupts = <1 9 0>;
+			gpio-controller;
+		};
+
+		gpt1: timer@610 {	// GPT 1 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x610 0x10>;
+			interrupts = <1 10 0>;
+			gpio-controller;
+		};
+
+		gpt2: timer@620 {	// GPT 2 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x620 0x10>;
+			interrupts = <1 11 0>;
+			gpio-controller;
+		};
+
+		gpt3: timer@630 {	// GPT 3 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x630 0x10>;
+			interrupts = <1 12 0>;
+			gpio-controller;
+		};
+
+		gpt4: timer@640 {	// GPT 4 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x640 0x10>;
+			interrupts = <1 13 0>;
+			gpio-controller;
+		};
+
+		gpt5: timer@650 {	// GPT 5 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x650 0x10>;
+			interrupts = <1 14 0>;
+			gpio-controller;
+		};
+
+		gpt6: timer@660 {	// GPT 6 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x660 0x10>;
+			interrupts = <1 15 0>;
+			gpio-controller;
+		};
+
+		gpt7: timer@670 {	// GPT 7 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x670 0x10>;
+			interrupts = <1 16 0>;
+			gpio-controller;
+		};
+
+		gpio_simple: gpio@b00 {
+			compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
+			reg = <0xb00 0x40>;
+			interrupts = <1 7 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpio_wkup: gpio@c00 {
+			compatible = "fsl,mpc5200b-gpio-wkup",
+					"fsl,mpc5200-gpio-wkup";
+			reg = <0xc00 0x40>;
+			interrupts = <1 8 0 0 3 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpio_sint: gpio_sint@b00 {
+			compatible = "fsl,mpc5200b-gpio-sint",
+					"fsl,mpc5200-gpio-sint";
+			reg = <0xb00 0x40>;
+			interrupts = <1 8 0 0 3 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		dma-controller@1200 {
+			device_type = "dma-controller";
+			compatible = "fsl,mpc5200b-bestcomm",
+					"fsl,mpc5200-bestcomm";
+			reg = <0x1200 0x80>;
+			interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
+			              3 4 0  3 5 0  3 6 0  3 7 0
+			              3 8 0  3 9 0  3 10 0  3 11 0
+			              3 12 0  3 13 0  3 14 0  3 15 0>;
+		};
+
+		xlb@1f00 {
+			compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
+			reg = <0x1f00 0x100>;
+		};
+
+		serial@2000 {		// PSC1
+			compatible = "fsl,mpc5200b-psc-uart",
+					"fsl,mpc5200-psc-uart";
+			reg = <0x2000 0x100>;
+			interrupts = <2 1 0>;
+		};
+
+		serial@2200 {		// PSC2
+			compatible = "fsl,mpc5200b-psc-uart",
+					"fsl,mpc5200-psc-uart";
+			reg = <0x2200 0x100>;
+			interrupts = <2 2 0>;
+		};
+
+		serial@2c00 {		// PSC6
+			compatible = "fsl,mpc5200b-psc-uart",
+					"fsl,mpc5200-psc-uart";
+			reg = <0x2c00 0x100>;
+			interrupts = <2 6 0>;
+		};
+
+		ethernet@3000 {
+			compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
+			reg = <0x3000 0x400>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <2 5 0>;
+			phy-handle = <&phy0>;
+		};
+
+		mdio@3000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
+			reg = <0x3000 0x400>;	// fec range, since we need to
+						// setup fec interrupts
+			interrupts = <2 5 0>;	// these are for "mii command
+						// finished", not link
+						// changes & co.
+
+			phy0: ethernet-phy@0 {
+				compatible = "intel,lxt971";
+				reg = <0>;
+			};
+		};
+
+		ata@3a00 {
+			compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
+			reg = <0x3a00 0x100>;
+			interrupts = <2 7 0>;
+		};
+
+		i2c@3d40 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c",
+					"fsl-i2c";
+			reg = <0x3d40 0x40>;
+			interrupts = <2 16 0>;
+			fsl,preserve-clocking;
+			clock-frequency = <400000>;
+
+			hwmon@2c {
+				compatible = "ad,adm9240";
+				reg = <0x2c>;
+			};
+			rtc@51 {
+				compatible = "nxp,pcf8563";
+				reg = <0x51>;
+			};
+		};
+
+		sram@8000 {
+			compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
+			reg = <0x8000 0x4000>;
+		};
+	};
+
+	localbus {
+		compatible = "fsl,mpc5200b-lpb","simple-bus";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges = <0 0 0xff800000 0x00800000
+			  1 0 0x80000000 0x00800000
+			  3 0 0x80000000 0x00800000>;
+
+		flash@0,0 {
+			compatible = "cfi-flash";
+			reg = <0 0 0x00800000>;
+			bank-width = <2>;
+			device-width = <2>;
+			#size-cells = <1>;
+			#address-cells = <1>;
+			partition@0 {
+				label = "DTS";
+				reg = <0x0 0x00100000>;
+			};
+			partition@100000 {
+				label = "Kernel";
+				reg = <0x100000 0x00200000>;
+			};
+			partition@300000 {
+				label = "RootFS";
+				reg = <0x00300000 0x00200000>;
+			};
+
+			partition@500000 {
+				label = "user";
+				reg = <0x00500000 0x00200000>;
+			};
+			partition@700000 {
+				label = "U-Boot";
+				reg = <0x00700000 0x00040000>;
+			};
+			partition@740000 {
+				label = "Env";
+				reg = <0x00740000 0x00010000>;
+			};
+			partition@750000 {
+				label = "red. Env";
+				reg = <0x00750000 0x00010000>;
+			};
+			partition@760000 {
+				label = "reserve";
+				reg = <0x00760000 0x000a0000>;
+			};
+		};
+
+	};
+};

arch/powerpc/platforms/52xx/mpc5200_simple.c +1 -0

index c31e5b5..caf6d92 100644
@@ -51,6 +51,7 @@ static void __init mpc5200_simple_setup_arch(void)
 /* list of the supported boards */
 static char *board[] __initdata = {
 	"intercontrol,digsy-mtc",
+	"manroland,uc101",
 	"phytec,pcm030",
 	"phytec,pcm032",
 	"promess,motionpro",

Signature · 6 lines

1.6.0.6


-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Heiko Schocher

author

2009-10-07 06:57 UTC #11 lore raw

PATCH v3 1/1 mpc5200: support for the MAN mpc5200 based board mucmc52

In reply to Grant Likely

- serial Console on PSC1
- 64MB SDRAM
- MTD CFI Flash
- Ethernet FEC
- IDE support

Signed-off-by Heiko Schocher <[email protected]>

---

- based on:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git next

- checked with:

$ ./scripts/checkpatch.pl 0002-mpc5200-support-for-the-MAN-mpc5200-based-board-muc.patch
total: 0 errors, 0 warnings, 361 lines checked

0002-mpc5200-support-for-the-MAN-mpc5200-based-board-muc.patch has no obvious style problems and is ready for submission. $

changes since v1:

- add comments from Grant Likely <[email protected]> use mpc5200_defconfig as default configuration, therefore added SIMPLE_GPIO support in it, because this is not selectable as a module.
- add comments from Wolfram Sang <[email protected]>
- rebase against current next

changes since v2:
- add comment from Wolfram Sang
remove unofficial binding

 arch/powerpc/boot/dts/mucmc52.dts            |  346 ++++++++++++++++++++++++++
 arch/powerpc/configs/mpc5200_defconfig       |    2 +-
 arch/powerpc/platforms/52xx/mpc5200_simple.c |    1 +
 3 files changed, 348 insertions(+), 1 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/mucmc52.dts

arch/powerpc/boot/dts/mucmc52.dts new file +346 -0

new file mode 100644
index 0000000..3924811
@@ -0,0 +1,346 @@
+/*
+ * mucmc52 board Device Tree Source
+ *
+ * Copyright (C) 2009 DENX Software Engineering GmbH
+ * Heiko Schocher <[email protected]>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+	model = "manroland,mucmc52";
+	compatible = "manroland,mucmc52";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&mpc5200_pic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,5200@0 {
+			device_type = "cpu";
+			reg = <0>;
+			d-cache-line-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x4000>;	// L1, 16K
+			i-cache-size = <0x4000>;	// L1, 16K
+			timebase-frequency = <0>;	// from bootloader
+			bus-frequency = <0>;		// from bootloader
+			clock-frequency = <0>;		// from bootloader
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x04000000>;	// 64MB
+	};
+
+	soc5200@f0000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fsl,mpc5200-immr",
+				"fsl,mpc5200b-immr";
+		ranges = <0 0xf0000000 0x0000c000>;
+		reg = <0xf0000000 0x00000100>;
+		bus-frequency = <0>;		// from bootloader
+		system-frequency = <0>;		// from bootloader
+
+		cdm@200 {
+			compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
+			reg = <0x200 0x38>;
+		};
+
+		mpc5200_pic: interrupt-controller@500 {
+			// 5200 interrupts are encoded into two levels;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
+			reg = <0x500 0x80>;
+			interrupts = <0 0 3>;
+		};
+
+		gpt0: timer@600 {	// GPT 0 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x600 0x10>;
+			interrupts = <1 9 0>;
+			gpio-controller;
+		};
+
+		gpt1: timer@610 {	// GPT 1 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x610 0x10>;
+			interrupts = <1 10 0>;
+			gpio-controller;
+		};
+
+		gpt2: timer@620 {	// GPT 2 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x620 0x10>;
+			interrupts = <1 11 0>;
+			gpio-controller;
+		};
+
+		gpt3: timer@630 {	// GPT 3 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x630 0x10>;
+			interrupts = <1 12 0>;
+			gpio-controller;
+		};
+
+		gpio_simple: gpio@b00 {
+			compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
+			#gpio-cells = <2>;
+			reg = <0xb00 0x40>;
+			interrupts = <1 7 0>;
+			gpio-controller;
+		};
+
+		gpio_wkup: gpio@c00 {
+			compatible = "fsl,mpc5200b-gpio-wkup",
+					"fsl,mpc5200-gpio-wkup";
+			#gpio-cells = <2>;
+			reg = <0xc00 0x40>;
+			interrupts = <1 8 0 0 3 0>;
+			gpio-controller;
+		};
+
+		dma-controller@1200 {
+			device_type = "dma-controller";
+			compatible = "fsl,mpc5200b-bestcomm",
+					"fsl,mpc5200-bestcomm";
+			reg = <0x1200 0x80>;
+			interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
+			              3 4 0  3 5 0  3 6 0  3 7 0
+			              3 8 0  3 9 0  3 10 0  3 11 0
+			              3 12 0  3 13 0  3 14 0  3 15 0>;
+		};
+
+		xlb@1f00 {
+			compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
+			reg = <0x1f00 0x100>;
+		};
+
+		serial@2000 {		// PSC1
+			compatible = "fsl,mpc5200b-psc-uart",
+					"fsl,mpc5200-psc-uart";
+			reg = <0x2000 0x100>;
+			interrupts = <2 1 0>;
+		};
+
+		serial@2200 {		// PSC2
+			compatible = "fsl,mpc5200b-psc-uart",
+					"fsl,mpc5200-psc-uart";
+			reg = <0x2200 0x100>;
+			interrupts = <2 2 0>;
+		};
+
+		serial@2c00 {		// PSC6
+			compatible = "fsl,mpc5200b-psc-uart",
+					"fsl,mpc5200-psc-uart";
+			reg = <0x2c00 0x100>;
+			interrupts = <2 6 0>;
+		};
+
+		ethernet@3000 {
+			compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
+			reg = <0x3000 0x400>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <2 5 0>;
+			phy-handle = <&phy0>;
+		};
+
+		mdio@3000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
+			reg = <0x3000 0x400>; 	// fec range, since we need to
+						// setup fec interrupts
+			interrupts = <2 5 0>; 	// these are for "mii command
+						// finished", not link changes
+						//  & co.
+
+			phy0: ethernet-phy@0 {
+				compatible = "intel,lxt971";
+				reg = <0>;
+			};
+		};
+
+		ata@3a00 {
+			compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
+			reg = <0x3a00 0x100>;
+			interrupts = <2 7 0>;
+		};
+
+		i2c@3d40 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c",
+					"fsl-i2c";
+			reg = <0x3d40 0x40>;
+			interrupts = <2 16 0>;
+
+			hwmon@2c {
+				compatible = "ad,adm9240";
+				reg = <0x2c>;
+			};
+			rtc@51 {
+				compatible = "nxp,pcf8563";
+				reg = <0x51>;
+			};
+		};
+
+		sram@8000 {
+			compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
+			reg = <0x8000 0x4000>;
+		};
+	};
+
+	localbus {
+		compatible = "fsl,mpc5200b-lpb","simple-bus";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges = <0 0 0xff800000 0x00800000
+			  1 0 0x80000000 0x00800000
+			  3 0 0x80000000 0x00800000>;
+
+		flash@0,0 {
+			compatible = "cfi-flash";
+			reg = <0 0 0x00800000>;
+			bank-width = <4>;
+			device-width = <2>;
+			#size-cells = <1>;
+			#address-cells = <1>;
+			partition@0 {
+				label = "DTS";
+				reg = <0x0 0x00100000>;
+			};
+			partition@100000 {
+				label = "Kernel";
+				reg = <0x100000 0x00200000>;
+			};
+			partition@300000 {
+				label = "RootFS";
+				reg = <0x00300000 0x00200000>;
+			};
+			partition@500000 {
+				label = "user";
+				reg = <0x00500000 0x00200000>;
+			};
+			partition@700000 {
+				label = "U-Boot";
+				reg = <0x00700000 0x00040000>;
+			};
+			partition@740000 {
+				label = "Env";
+				reg = <0x00740000 0x00020000>;
+			};
+			partition@760000 {
+				label = "red. Env";
+				reg = <0x00760000 0x00020000>;
+			};
+			partition@780000 {
+				label = "reserve";
+				reg = <0x00780000 0x00080000>;
+			};
+		};
+
+		simple100: gpio-controller-100@3,600100 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600100 0x1>;
+				gpio-controller;
+		};
+		simple104: gpio-controller-104@3,600104 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600104 0x1>;
+				gpio-controller;
+		};
+		simple200: gpio-controller-200@3,600200 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600200 0x1>;
+				gpio-controller;
+		};
+		simple201: gpio-controller-201@3,600201 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600201 0x1>;
+				gpio-controller;
+		};
+		simple202: gpio-controller-202@3,600202 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600202 0x1>;
+				gpio-controller;
+		};
+		simple203: gpio-controller-203@3,600203 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600203 0x1>;
+				gpio-controller;
+		};
+		simple204: gpio-controller-204@3,600204 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600204 0x1>;
+				gpio-controller;
+		};
+		simple206: gpio-controller-206@3,600206 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600206 0x1>;
+				gpio-controller;
+		};
+		simple207: gpio-controller-207@3,600207 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600207 0x1>;
+				gpio-controller;
+		};
+		simple20f: gpio-controller-20f@3,60020f {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x0060020f 0x1>;
+				gpio-controller;
+		};
+
+	};
+
+	pci@f0000d00 {
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		device_type = "pci";
+		compatible = "fsl,mpc5200-pci";
+		reg = <0xf0000d00 0x100>;
+		interrupt-map-mask = <0xf800 0 0 7>;
+		interrupt-map = <
+				/* IDSEL 0x10 */
+				0x8000 0 0 1 &mpc5200_pic 0 3 3
+				0x8000 0 0 2 &mpc5200_pic 0 3 3
+				0x8000 0 0 3 &mpc5200_pic 0 2 3
+				0x8000 0 0 4 &mpc5200_pic 0 1 3
+				>;
+		clock-frequency = <0>; // From boot loader
+		interrupts = <2 8 0 2 9 0 2 10 0>;
+		bus-range = <0 0>;
+		ranges = <0x42000000 0 0x60000000 0x60000000 0 0x10000000
+			  0x02000000 0 0x90000000 0x90000000 0 0x10000000
+			  0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
+	};
+};

arch/powerpc/configs/mpc5200_defconfig +1 -1

index aaa4416..d035421 100644
@@ -205,7 +205,7 @@ CONFIG_RTAS_PROC=y
 CONFIG_PPC_BESTCOMM=y
 CONFIG_PPC_BESTCOMM_ATA=y
 CONFIG_PPC_BESTCOMM_FEC=y
-# CONFIG_SIMPLE_GPIO is not set
+CONFIG_SIMPLE_GPIO=y
 
 #
 # Kernel options

arch/powerpc/platforms/52xx/mpc5200_simple.c +1 -0

index caf6d92..d45be5b 100644
@@ -51,6 +51,7 @@ static void __init mpc5200_simple_setup_arch(void)
 /* list of the supported boards */
 static char *board[] __initdata = {
 	"intercontrol,digsy-mtc",
+	"manroland,mucmc52",
 	"manroland,uc101",
 	"phytec,pcm030",
 	"phytec,pcm032",

Signature · 5 lines

1.6.0.6

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Wolfram Sang

Reviewed-by on v3 1/1

2009-10-07 09:49 UTC #12 lore raw

Quoted 7 lines · Heiko Schocher

- serial Console on PSC1
- 64MB SDRAM
- MTD CFI Flash
- Ethernet FEC
- IDE support
Signed-off-by Heiko Schocher <[email protected]>

Sorry for finding things incrementally, but I think there is still one issue left. Once this is sorted out, you could add my:

Reviewed-by Wolfram Sang <[email protected]>

Quoted 75 lines

---

- based on:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git next

- checked with:

$ ./scripts/checkpatch.pl 0002-mpc5200-support-for-the-MAN-mpc5200-based-board-muc.patch
total: 0 errors, 0 warnings, 361 lines checked

0002-mpc5200-support-for-the-MAN-mpc5200-based-board-muc.patch has no obvious style problems and is ready for submission. $

changes since v1:

changes since v2:
- add comment from Wolfram Sang
remove unofficial binding

 arch/powerpc/boot/dts/mucmc52.dts            |  346 ++++++++++++++++++++++++++
 arch/powerpc/configs/mpc5200_defconfig       |    2 +-
 arch/powerpc/platforms/52xx/mpc5200_simple.c |    1 +
 3 files changed, 348 insertions(+), 1 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/mucmc52.dts

arch/powerpc/boot/dts/mucmc52.dts new file +38 -0

new file mode 100644
index 0000000..3924811
@@ -0,0 +1,346 @@
+/*
+ * mucmc52 board Device Tree Source
+ *
+ * Copyright (C) 2009 DENX Software Engineering GmbH
+ * Heiko Schocher <[email protected]>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+	model = "manroland,mucmc52";
+	compatible = "manroland,mucmc52";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&mpc5200_pic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,5200@0 {
+			device_type = "cpu";
+			reg = <0>;
+			d-cache-line-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x4000>;	// L1, 16K
+			i-cache-size = <0x4000>;	// L1, 16K
+			timebase-frequency = <0>;	// from bootloader
+			bus-frequency = <0>;		// from bootloader
+			clock-frequency = <0>;		// from bootloader
+		};
+	};
+

arch/powerpc/boot/dts/mucmc52.dts line 48

Quoted 10 lines

arch/powerpc/boot/dts/mucmc52.dts new file +10 -0

+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x04000000>;	// 64MB
+	};
+
+	soc5200@f0000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fsl,mpc5200-immr",
+				"fsl,mpc5200b-immr";

You should decide on the latter one only here.

Quoted 329 lines

arch/powerpc/boot/dts/mucmc52.dts new file +298 -0

+		ranges = <0 0xf0000000 0x0000c000>;
+		reg = <0xf0000000 0x00000100>;
+		bus-frequency = <0>;		// from bootloader
+		system-frequency = <0>;		// from bootloader
+
+		cdm@200 {
+			compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
+			reg = <0x200 0x38>;
+		};
+
+		mpc5200_pic: interrupt-controller@500 {
+			// 5200 interrupts are encoded into two levels;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
+			reg = <0x500 0x80>;
+			interrupts = <0 0 3>;
+		};
+
+		gpt0: timer@600 {	// GPT 0 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x600 0x10>;
+			interrupts = <1 9 0>;
+			gpio-controller;
+		};
+
+		gpt1: timer@610 {	// GPT 1 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x610 0x10>;
+			interrupts = <1 10 0>;
+			gpio-controller;
+		};
+
+		gpt2: timer@620 {	// GPT 2 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x620 0x10>;
+			interrupts = <1 11 0>;
+			gpio-controller;
+		};
+
+		gpt3: timer@630 {	// GPT 3 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x630 0x10>;
+			interrupts = <1 12 0>;
+			gpio-controller;
+		};
+
+		gpio_simple: gpio@b00 {
+			compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
+			#gpio-cells = <2>;
+			reg = <0xb00 0x40>;
+			interrupts = <1 7 0>;
+			gpio-controller;
+		};
+
+		gpio_wkup: gpio@c00 {
+			compatible = "fsl,mpc5200b-gpio-wkup",
+					"fsl,mpc5200-gpio-wkup";
+			#gpio-cells = <2>;
+			reg = <0xc00 0x40>;
+			interrupts = <1 8 0 0 3 0>;
+			gpio-controller;
+		};
+
+		dma-controller@1200 {
+			device_type = "dma-controller";
+			compatible = "fsl,mpc5200b-bestcomm",
+					"fsl,mpc5200-bestcomm";
+			reg = <0x1200 0x80>;
+			interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
+			              3 4 0  3 5 0  3 6 0  3 7 0
+			              3 8 0  3 9 0  3 10 0  3 11 0
+			              3 12 0  3 13 0  3 14 0  3 15 0>;
+		};
+
+		xlb@1f00 {
+			compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
+			reg = <0x1f00 0x100>;
+		};
+
+		serial@2000 {		// PSC1
+			compatible = "fsl,mpc5200b-psc-uart",
+					"fsl,mpc5200-psc-uart";
+			reg = <0x2000 0x100>;
+			interrupts = <2 1 0>;
+		};
+
+		serial@2200 {		// PSC2
+			compatible = "fsl,mpc5200b-psc-uart",
+					"fsl,mpc5200-psc-uart";
+			reg = <0x2200 0x100>;
+			interrupts = <2 2 0>;
+		};
+
+		serial@2c00 {		// PSC6
+			compatible = "fsl,mpc5200b-psc-uart",
+					"fsl,mpc5200-psc-uart";
+			reg = <0x2c00 0x100>;
+			interrupts = <2 6 0>;
+		};
+
+		ethernet@3000 {
+			compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
+			reg = <0x3000 0x400>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <2 5 0>;
+			phy-handle = <&phy0>;
+		};
+
+		mdio@3000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
+			reg = <0x3000 0x400>; 	// fec range, since we need to
+						// setup fec interrupts
+			interrupts = <2 5 0>; 	// these are for "mii command
+						// finished", not link changes
+						//  & co.
+
+			phy0: ethernet-phy@0 {
+				compatible = "intel,lxt971";
+				reg = <0>;
+			};
+		};
+
+		ata@3a00 {
+			compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
+			reg = <0x3a00 0x100>;
+			interrupts = <2 7 0>;
+		};
+
+		i2c@3d40 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c",
+					"fsl-i2c";
+			reg = <0x3d40 0x40>;
+			interrupts = <2 16 0>;
+
+			hwmon@2c {
+				compatible = "ad,adm9240";
+				reg = <0x2c>;
+			};
+			rtc@51 {
+				compatible = "nxp,pcf8563";
+				reg = <0x51>;
+			};
+		};
+
+		sram@8000 {
+			compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
+			reg = <0x8000 0x4000>;
+		};
+	};
+
+	localbus {
+		compatible = "fsl,mpc5200b-lpb","simple-bus";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges = <0 0 0xff800000 0x00800000
+			  1 0 0x80000000 0x00800000
+			  3 0 0x80000000 0x00800000>;
+
+		flash@0,0 {
+			compatible = "cfi-flash";
+			reg = <0 0 0x00800000>;
+			bank-width = <4>;
+			device-width = <2>;
+			#size-cells = <1>;
+			#address-cells = <1>;
+			partition@0 {
+				label = "DTS";
+				reg = <0x0 0x00100000>;
+			};
+			partition@100000 {
+				label = "Kernel";
+				reg = <0x100000 0x00200000>;
+			};
+			partition@300000 {
+				label = "RootFS";
+				reg = <0x00300000 0x00200000>;
+			};
+			partition@500000 {
+				label = "user";
+				reg = <0x00500000 0x00200000>;
+			};
+			partition@700000 {
+				label = "U-Boot";
+				reg = <0x00700000 0x00040000>;
+			};
+			partition@740000 {
+				label = "Env";
+				reg = <0x00740000 0x00020000>;
+			};
+			partition@760000 {
+				label = "red. Env";
+				reg = <0x00760000 0x00020000>;
+			};
+			partition@780000 {
+				label = "reserve";
+				reg = <0x00780000 0x00080000>;
+			};
+		};
+
+		simple100: gpio-controller-100@3,600100 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600100 0x1>;
+				gpio-controller;
+		};
+		simple104: gpio-controller-104@3,600104 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600104 0x1>;
+				gpio-controller;
+		};
+		simple200: gpio-controller-200@3,600200 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600200 0x1>;
+				gpio-controller;
+		};
+		simple201: gpio-controller-201@3,600201 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600201 0x1>;
+				gpio-controller;
+		};
+		simple202: gpio-controller-202@3,600202 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600202 0x1>;
+				gpio-controller;
+		};
+		simple203: gpio-controller-203@3,600203 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600203 0x1>;
+				gpio-controller;
+		};
+		simple204: gpio-controller-204@3,600204 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600204 0x1>;
+				gpio-controller;
+		};
+		simple206: gpio-controller-206@3,600206 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600206 0x1>;
+				gpio-controller;
+		};
+		simple207: gpio-controller-207@3,600207 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600207 0x1>;
+				gpio-controller;
+		};
+		simple20f: gpio-controller-20f@3,60020f {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x0060020f 0x1>;
+				gpio-controller;
+		};
+
+	};
+
+	pci@f0000d00 {
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		device_type = "pci";
+		compatible = "fsl,mpc5200-pci";
+		reg = <0xf0000d00 0x100>;
+		interrupt-map-mask = <0xf800 0 0 7>;
+		interrupt-map = <
+				/* IDSEL 0x10 */
+				0x8000 0 0 1 &mpc5200_pic 0 3 3
+				0x8000 0 0 2 &mpc5200_pic 0 3 3
+				0x8000 0 0 3 &mpc5200_pic 0 2 3
+				0x8000 0 0 4 &mpc5200_pic 0 1 3
+				>;
+		clock-frequency = <0>; // From boot loader
+		interrupts = <2 8 0 2 9 0 2 10 0>;
+		bus-range = <0 0>;
+		ranges = <0x42000000 0 0x60000000 0x60000000 0 0x10000000
+			  0x02000000 0 0x90000000 0x90000000 0 0x10000000
+			  0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
+	};
+};

arch/powerpc/configs/mpc5200_defconfig +1 -1

index aaa4416..d035421 100644
@@ -205,7 +205,7 @@ CONFIG_RTAS_PROC=y
 CONFIG_PPC_BESTCOMM=y
 CONFIG_PPC_BESTCOMM_ATA=y
 CONFIG_PPC_BESTCOMM_FEC=y
-# CONFIG_SIMPLE_GPIO is not set
+CONFIG_SIMPLE_GPIO=y
 
 #
 # Kernel options

arch/powerpc/platforms/52xx/mpc5200_simple.c +1 -0

index caf6d92..d45be5b 100644
@@ -51,6 +51,7 @@ static void __init mpc5200_simple_setup_arch(void)
 /* list of the supported boards */
 static char *board[] __initdata = {
 	"intercontrol,digsy-mtc",
+	"manroland,mucmc52",
 	"manroland,uc101",
 	"phytec,pcm030",
 	"phytec,pcm032",

Signature · 5 lines

1.6.0.6

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Signature · 2 lines

Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

Grant Likely

2009-10-07 13:57 UTC #13 lore raw

Quoted 10 lines · Wolfram Sang

Quoted 7 lines · Heiko Schocher
- serial Console on PSC1
- 64MB SDRAM
- MTD CFI Flash
- Ethernet FEC
- IDE support
Signed-off-by Heiko Schocher <[email protected]>
Sorry for finding things incrementally, but I think there is still one is=

sue

Quoted 4 lines

left. Once this is sorted out, you could add my:
Reviewed-by Wolfram Sang <[email protected]>

[...]

Quoted 5 lines

Quoted 5 lines
+ =A0 =A0 soc5200@f0000000 {
+ =A0 =A0 =A0 =A0 =A0 =A0 #address-cells =3D <1>;
+ =A0 =A0 =A0 =A0 =A0 =A0 #size-cells =3D <1>;
+ =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5200-immr",
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 "fsl,mpc5200b-=

immr";

Quoted 2 lines

You should decide on the latter one only here.

Besides, the order is wrong. The exact version (mpc5200b) always appears before the list of backward compatible values (the non-'b' version). But Wolfram is right. The IMMR node of the mpc5200b is *not* wholly backwards compatible with fsl,mpc5200-immr, so 'fsl,mpc5200-immr' should not be in the list. fsl,mpc5200-<blah> only appears in the child nodes when the specific device truly is backwards compatible. Compare your .dts file line-for-line with one of the in-tree mpc5200b .dts files.

--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Heiko Schocher

author

2009-10-08 06:20 UTC #14 lore raw

PATCH v4 1/1 mpc5200: support for the MAN mpc5200 based board uc101

- serial Console on PSC1
- 64MB SDRAM
- MTD CFI Flash
- Ethernet FEC
- I2C with PCF8563 and Temp. Sensor ADM9240
- IDE support

Signed-off-by Heiko Schocher <[email protected]>

Reviewed-by Wolfram Sang <[email protected]>

---

- based on:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git next

- checked with:

$ ./scripts/checkpatch.pl 0001-mpc5200-support-for-the-MAN-mpc5200-based-board-uc1.patch
total: 0 errors, 0 warnings, 316 lines checked

0001-mpc5200-support-for-the-MAN-mpc5200-based-board-uc1.patch has no obvious style problems and is ready for submission. $

changes since v1:

- add comments from Grant Likely <[email protected]> use mpc5200_defconfig as default configuration
- add comments from Wolfram Sang <[email protected]>
- rebase against current next

changes since v2:
- add comment from Wolfram Sang
remove unofficial binding

changes since v3:
- add comment from Wolfram Sang
use "fsl,mpc5200b-immr" only
added Reviewed-by: Wolfram Sang <[email protected]>

 arch/powerpc/boot/dts/uc101.dts              |  309 ++++++++++++++++++++++++++
 arch/powerpc/platforms/52xx/mpc5200_simple.c |    1 +
 2 files changed, 310 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/uc101.dts

arch/powerpc/boot/dts/uc101.dts new file +309 -0

new file mode 100644
index 0000000..e928d22
@@ -0,0 +1,309 @@
+/*
+ * uc101 board Device Tree Source
+ *
+ * Copyright (C) 2009 DENX Software Engineering GmbH
+ * Heiko Schocher <[email protected]>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+	model = "manroland,uc101";
+	compatible = "manroland,uc101";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&mpc5200_pic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,5200@0 {
+			device_type = "cpu";
+			reg = <0>;
+			d-cache-line-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x4000>;	// L1, 16K
+			i-cache-size = <0x4000>;	// L1, 16K
+			timebase-frequency = <0>;	// from bootloader
+			bus-frequency = <0>;		// from bootloader
+			clock-frequency = <0>;		// from bootloader
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x04000000>;	// 64MB
+	};
+
+	soc5200@f0000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fsl,mpc5200b-immr";
+		ranges = <0 0xf0000000 0x0000c000>;
+		reg = <0xf0000000 0x00000100>;
+		bus-frequency = <0>;		// from bootloader
+		system-frequency = <0>;		// from bootloader
+
+		cdm@200 {
+			compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
+			reg = <0x200 0x38>;
+		};
+
+		mpc5200_pic: interrupt-controller@500 {
+			// 5200 interrupts are encoded into two levels;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
+			reg = <0x500 0x80>;
+			interrupts = <0 0 3>;
+		};
+
+		gpt0: timer@600 {	// GPT 0 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x600 0x10>;
+			interrupts = <1 9 0>;
+			gpio-controller;
+		};
+
+		gpt1: timer@610 {	// GPT 1 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x610 0x10>;
+			interrupts = <1 10 0>;
+			gpio-controller;
+		};
+
+		gpt2: timer@620 {	// GPT 2 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x620 0x10>;
+			interrupts = <1 11 0>;
+			gpio-controller;
+		};
+
+		gpt3: timer@630 {	// GPT 3 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x630 0x10>;
+			interrupts = <1 12 0>;
+			gpio-controller;
+		};
+
+		gpt4: timer@640 {	// GPT 4 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x640 0x10>;
+			interrupts = <1 13 0>;
+			gpio-controller;
+		};
+
+		gpt5: timer@650 {	// GPT 5 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x650 0x10>;
+			interrupts = <1 14 0>;
+			gpio-controller;
+		};
+
+		gpt6: timer@660 {	// GPT 6 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x660 0x10>;
+			interrupts = <1 15 0>;
+			gpio-controller;
+		};
+
+		gpt7: timer@670 {	// GPT 7 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x670 0x10>;
+			interrupts = <1 16 0>;
+			gpio-controller;
+		};
+
+		gpio_simple: gpio@b00 {
+			compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
+			reg = <0xb00 0x40>;
+			interrupts = <1 7 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpio_wkup: gpio@c00 {
+			compatible = "fsl,mpc5200b-gpio-wkup",
+					"fsl,mpc5200-gpio-wkup";
+			reg = <0xc00 0x40>;
+			interrupts = <1 8 0 0 3 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpio_sint: gpio_sint@b00 {
+			compatible = "fsl,mpc5200b-gpio-sint",
+					"fsl,mpc5200-gpio-sint";
+			reg = <0xb00 0x40>;
+			interrupts = <1 8 0 0 3 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		dma-controller@1200 {
+			device_type = "dma-controller";
+			compatible = "fsl,mpc5200b-bestcomm",
+					"fsl,mpc5200-bestcomm";
+			reg = <0x1200 0x80>;
+			interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
+			              3 4 0  3 5 0  3 6 0  3 7 0
+			              3 8 0  3 9 0  3 10 0  3 11 0
+			              3 12 0  3 13 0  3 14 0  3 15 0>;
+		};
+
+		xlb@1f00 {
+			compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
+			reg = <0x1f00 0x100>;
+		};
+
+		serial@2000 {		// PSC1
+			compatible = "fsl,mpc5200b-psc-uart",
+					"fsl,mpc5200-psc-uart";
+			reg = <0x2000 0x100>;
+			interrupts = <2 1 0>;
+		};
+
+		serial@2200 {		// PSC2
+			compatible = "fsl,mpc5200b-psc-uart",
+					"fsl,mpc5200-psc-uart";
+			reg = <0x2200 0x100>;
+			interrupts = <2 2 0>;
+		};
+
+		serial@2c00 {		// PSC6
+			compatible = "fsl,mpc5200b-psc-uart",
+					"fsl,mpc5200-psc-uart";
+			reg = <0x2c00 0x100>;
+			interrupts = <2 6 0>;
+		};
+
+		ethernet@3000 {
+			compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
+			reg = <0x3000 0x400>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <2 5 0>;
+			phy-handle = <&phy0>;
+		};
+
+		mdio@3000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
+			reg = <0x3000 0x400>;	// fec range, since we need to
+						// setup fec interrupts
+			interrupts = <2 5 0>;	// these are for "mii command
+						// finished", not link
+						// changes & co.
+
+			phy0: ethernet-phy@0 {
+				compatible = "intel,lxt971";
+				reg = <0>;
+			};
+		};
+
+		ata@3a00 {
+			compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
+			reg = <0x3a00 0x100>;
+			interrupts = <2 7 0>;
+		};
+
+		i2c@3d40 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c",
+					"fsl-i2c";
+			reg = <0x3d40 0x40>;
+			interrupts = <2 16 0>;
+			fsl,preserve-clocking;
+			clock-frequency = <400000>;
+
+			hwmon@2c {
+				compatible = "ad,adm9240";
+				reg = <0x2c>;
+			};
+			rtc@51 {
+				compatible = "nxp,pcf8563";
+				reg = <0x51>;
+			};
+		};
+
+		sram@8000 {
+			compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
+			reg = <0x8000 0x4000>;
+		};
+	};
+
+	localbus {
+		compatible = "fsl,mpc5200b-lpb","simple-bus";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges = <0 0 0xff800000 0x00800000
+			  1 0 0x80000000 0x00800000
+			  3 0 0x80000000 0x00800000>;
+
+		flash@0,0 {
+			compatible = "cfi-flash";
+			reg = <0 0 0x00800000>;
+			bank-width = <2>;
+			device-width = <2>;
+			#size-cells = <1>;
+			#address-cells = <1>;
+			partition@0 {
+				label = "DTS";
+				reg = <0x0 0x00100000>;
+			};
+			partition@100000 {
+				label = "Kernel";
+				reg = <0x100000 0x00200000>;
+			};
+			partition@300000 {
+				label = "RootFS";
+				reg = <0x00300000 0x00200000>;
+			};
+
+			partition@500000 {
+				label = "user";
+				reg = <0x00500000 0x00200000>;
+			};
+			partition@700000 {
+				label = "U-Boot";
+				reg = <0x00700000 0x00040000>;
+			};
+			partition@740000 {
+				label = "Env";
+				reg = <0x00740000 0x00010000>;
+			};
+			partition@750000 {
+				label = "red. Env";
+				reg = <0x00750000 0x00010000>;
+			};
+			partition@760000 {
+				label = "reserve";
+				reg = <0x00760000 0x000a0000>;
+			};
+		};
+
+	};
+};

arch/powerpc/platforms/52xx/mpc5200_simple.c +1 -0

index c31e5b5..caf6d92 100644
@@ -51,6 +51,7 @@ static void __init mpc5200_simple_setup_arch(void)
 /* list of the supported boards */
 static char *board[] __initdata = {
 	"intercontrol,digsy-mtc",
+	"manroland,uc101",
 	"phytec,pcm030",
 	"phytec,pcm032",
 	"promess,motionpro",

Signature · 5 lines

1.6.0.6

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Heiko Schocher

author

2009-10-08 06:21 UTC #15 lore raw

PATCH v4 1/1 mpc5200: support for the MAN mpc5200 based board mucmc52

In reply to Grant Likely

- serial Console on PSC1
- 64MB SDRAM
- MTD CFI Flash
- Ethernet FEC
- IDE support

Signed-off-by Heiko Schocher <[email protected]>

Reviewed-by Wolfram Sang <[email protected]>

---

- based on:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git next

- checked with:

$ ./scripts/checkpatch.pl 0002-mpc5200-support-for-the-MAN-mpc5200-based-board-muc.patch
total: 0 errors, 0 warnings, 360 lines checked

0002-mpc5200-support-for-the-MAN-mpc5200-based-board-muc.patch has no obvious style problems and is ready for submission. $

changes since v1:

changes since v2:
- add comment from Wolfram Sang
remove unofficial binding

changes since v3:
- add comment from Wolfram Sang
use "fsl,mpc5200b-immr" only
added Reviewed-by: Wolfram Sang <[email protected]>

 arch/powerpc/boot/dts/mucmc52.dts            |  345 ++++++++++++++++++++++++++
 arch/powerpc/configs/mpc5200_defconfig       |    2 +-
 arch/powerpc/platforms/52xx/mpc5200_simple.c |    1 +
 3 files changed, 347 insertions(+), 1 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/mucmc52.dts

arch/powerpc/boot/dts/mucmc52.dts new file +345 -0

new file mode 100644
index 0000000..7b29d76
@@ -0,0 +1,345 @@
+/*
+ * mucmc52 board Device Tree Source
+ *
+ * Copyright (C) 2009 DENX Software Engineering GmbH
+ * Heiko Schocher <[email protected]>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+	model = "manroland,mucmc52";
+	compatible = "manroland,mucmc52";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&mpc5200_pic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,5200@0 {
+			device_type = "cpu";
+			reg = <0>;
+			d-cache-line-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x4000>;	// L1, 16K
+			i-cache-size = <0x4000>;	// L1, 16K
+			timebase-frequency = <0>;	// from bootloader
+			bus-frequency = <0>;		// from bootloader
+			clock-frequency = <0>;		// from bootloader
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x04000000>;	// 64MB
+	};
+
+	soc5200@f0000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fsl,mpc5200b-immr";
+		ranges = <0 0xf0000000 0x0000c000>;
+		reg = <0xf0000000 0x00000100>;
+		bus-frequency = <0>;		// from bootloader
+		system-frequency = <0>;		// from bootloader
+
+		cdm@200 {
+			compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
+			reg = <0x200 0x38>;
+		};
+
+		mpc5200_pic: interrupt-controller@500 {
+			// 5200 interrupts are encoded into two levels;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
+			reg = <0x500 0x80>;
+			interrupts = <0 0 3>;
+		};
+
+		gpt0: timer@600 {	// GPT 0 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x600 0x10>;
+			interrupts = <1 9 0>;
+			gpio-controller;
+		};
+
+		gpt1: timer@610 {	// GPT 1 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x610 0x10>;
+			interrupts = <1 10 0>;
+			gpio-controller;
+		};
+
+		gpt2: timer@620 {	// GPT 2 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x620 0x10>;
+			interrupts = <1 11 0>;
+			gpio-controller;
+		};
+
+		gpt3: timer@630 {	// GPT 3 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x630 0x10>;
+			interrupts = <1 12 0>;
+			gpio-controller;
+		};
+
+		gpio_simple: gpio@b00 {
+			compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
+			#gpio-cells = <2>;
+			reg = <0xb00 0x40>;
+			interrupts = <1 7 0>;
+			gpio-controller;
+		};
+
+		gpio_wkup: gpio@c00 {
+			compatible = "fsl,mpc5200b-gpio-wkup",
+					"fsl,mpc5200-gpio-wkup";
+			#gpio-cells = <2>;
+			reg = <0xc00 0x40>;
+			interrupts = <1 8 0 0 3 0>;
+			gpio-controller;
+		};
+
+		dma-controller@1200 {
+			device_type = "dma-controller";
+			compatible = "fsl,mpc5200b-bestcomm",
+					"fsl,mpc5200-bestcomm";
+			reg = <0x1200 0x80>;
+			interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
+			              3 4 0  3 5 0  3 6 0  3 7 0
+			              3 8 0  3 9 0  3 10 0  3 11 0
+			              3 12 0  3 13 0  3 14 0  3 15 0>;
+		};
+
+		xlb@1f00 {
+			compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
+			reg = <0x1f00 0x100>;
+		};
+
+		serial@2000 {		// PSC1
+			compatible = "fsl,mpc5200b-psc-uart",
+					"fsl,mpc5200-psc-uart";
+			reg = <0x2000 0x100>;
+			interrupts = <2 1 0>;
+		};
+
+		serial@2200 {		// PSC2
+			compatible = "fsl,mpc5200b-psc-uart",
+					"fsl,mpc5200-psc-uart";
+			reg = <0x2200 0x100>;
+			interrupts = <2 2 0>;
+		};
+
+		serial@2c00 {		// PSC6
+			compatible = "fsl,mpc5200b-psc-uart",
+					"fsl,mpc5200-psc-uart";
+			reg = <0x2c00 0x100>;
+			interrupts = <2 6 0>;
+		};
+
+		ethernet@3000 {
+			compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
+			reg = <0x3000 0x400>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <2 5 0>;
+			phy-handle = <&phy0>;
+		};
+
+		mdio@3000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
+			reg = <0x3000 0x400>; 	// fec range, since we need to
+						// setup fec interrupts
+			interrupts = <2 5 0>; 	// these are for "mii command
+						// finished", not link changes
+						//  & co.
+
+			phy0: ethernet-phy@0 {
+				compatible = "intel,lxt971";
+				reg = <0>;
+			};
+		};
+
+		ata@3a00 {
+			compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
+			reg = <0x3a00 0x100>;
+			interrupts = <2 7 0>;
+		};
+
+		i2c@3d40 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c",
+					"fsl-i2c";
+			reg = <0x3d40 0x40>;
+			interrupts = <2 16 0>;
+
+			hwmon@2c {
+				compatible = "ad,adm9240";
+				reg = <0x2c>;
+			};
+			rtc@51 {
+				compatible = "nxp,pcf8563";
+				reg = <0x51>;
+			};
+		};
+
+		sram@8000 {
+			compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
+			reg = <0x8000 0x4000>;
+		};
+	};
+
+	localbus {
+		compatible = "fsl,mpc5200b-lpb","simple-bus";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges = <0 0 0xff800000 0x00800000
+			  1 0 0x80000000 0x00800000
+			  3 0 0x80000000 0x00800000>;
+
+		flash@0,0 {
+			compatible = "cfi-flash";
+			reg = <0 0 0x00800000>;
+			bank-width = <4>;
+			device-width = <2>;
+			#size-cells = <1>;
+			#address-cells = <1>;
+			partition@0 {
+				label = "DTS";
+				reg = <0x0 0x00100000>;
+			};
+			partition@100000 {
+				label = "Kernel";
+				reg = <0x100000 0x00200000>;
+			};
+			partition@300000 {
+				label = "RootFS";
+				reg = <0x00300000 0x00200000>;
+			};
+			partition@500000 {
+				label = "user";
+				reg = <0x00500000 0x00200000>;
+			};
+			partition@700000 {
+				label = "U-Boot";
+				reg = <0x00700000 0x00040000>;
+			};
+			partition@740000 {
+				label = "Env";
+				reg = <0x00740000 0x00020000>;
+			};
+			partition@760000 {
+				label = "red. Env";
+				reg = <0x00760000 0x00020000>;
+			};
+			partition@780000 {
+				label = "reserve";
+				reg = <0x00780000 0x00080000>;
+			};
+		};
+
+		simple100: gpio-controller-100@3,600100 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600100 0x1>;
+				gpio-controller;
+		};
+		simple104: gpio-controller-104@3,600104 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600104 0x1>;
+				gpio-controller;
+		};
+		simple200: gpio-controller-200@3,600200 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600200 0x1>;
+				gpio-controller;
+		};
+		simple201: gpio-controller-201@3,600201 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600201 0x1>;
+				gpio-controller;
+		};
+		simple202: gpio-controller-202@3,600202 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600202 0x1>;
+				gpio-controller;
+		};
+		simple203: gpio-controller-203@3,600203 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600203 0x1>;
+				gpio-controller;
+		};
+		simple204: gpio-controller-204@3,600204 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600204 0x1>;
+				gpio-controller;
+		};
+		simple206: gpio-controller-206@3,600206 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600206 0x1>;
+				gpio-controller;
+		};
+		simple207: gpio-controller-207@3,600207 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600207 0x1>;
+				gpio-controller;
+		};
+		simple20f: gpio-controller-20f@3,60020f {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x0060020f 0x1>;
+				gpio-controller;
+		};
+
+	};
+
+	pci@f0000d00 {
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		device_type = "pci";
+		compatible = "fsl,mpc5200-pci";
+		reg = <0xf0000d00 0x100>;
+		interrupt-map-mask = <0xf800 0 0 7>;
+		interrupt-map = <
+				/* IDSEL 0x10 */
+				0x8000 0 0 1 &mpc5200_pic 0 3 3
+				0x8000 0 0 2 &mpc5200_pic 0 3 3
+				0x8000 0 0 3 &mpc5200_pic 0 2 3
+				0x8000 0 0 4 &mpc5200_pic 0 1 3
+				>;
+		clock-frequency = <0>; // From boot loader
+		interrupts = <2 8 0 2 9 0 2 10 0>;
+		bus-range = <0 0>;
+		ranges = <0x42000000 0 0x60000000 0x60000000 0 0x10000000
+			  0x02000000 0 0x90000000 0x90000000 0 0x10000000
+			  0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
+	};
+};

arch/powerpc/configs/mpc5200_defconfig +1 -1

index aaa4416..d035421 100644
@@ -205,7 +205,7 @@ CONFIG_RTAS_PROC=y
 CONFIG_PPC_BESTCOMM=y
 CONFIG_PPC_BESTCOMM_ATA=y
 CONFIG_PPC_BESTCOMM_FEC=y
-# CONFIG_SIMPLE_GPIO is not set
+CONFIG_SIMPLE_GPIO=y
 
 #
 # Kernel options

arch/powerpc/platforms/52xx/mpc5200_simple.c +1 -0

index caf6d92..d45be5b 100644
@@ -51,6 +51,7 @@ static void __init mpc5200_simple_setup_arch(void)
 /* list of the supported boards */
 static char *board[] __initdata = {
 	"intercontrol,digsy-mtc",
+	"manroland,mucmc52",
 	"manroland,uc101",
 	"phytec,pcm030",
 	"phytec,pcm032",

Signature · 6 lines

1.6.0.6


-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Heiko Schocher

author

2009-10-08 06:16 UTC #16 lore raw

In reply to Wolfram Sang

Hello Wolfram,

Quoted 11 lines · Wolfram Sang

Quoted 7 lines · Heiko Schocher
- serial Console on PSC1
- 64MB SDRAM
- MTD CFI Flash
- Ethernet FEC
- IDE support
Signed-off-by Heiko Schocher <[email protected]>
Sorry for finding things incrementally, but I think there is still one issue left. Once this is sorted out, you could add my:

No problem, thanks for finding it!

Quoted 1 line

Reviewed-by Wolfram Sang <[email protected]>

OK, added, send patches soon.

thanks
bye
Heiko

Signature · 2 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Heiko Schocher

author

2009-10-05 07:05 UTC #17 lore raw

PATCH v2 1/1 mpc5200: support for the MAN mpc5200 based board mucmc52

In reply to Grant Likely

- serial Console on PSC1
- 64MB SDRAM
- MTD CFI Flash
- Ethernet FEC
- IDE support

Signed-off-by Heiko Schocher <[email protected]>

---
- based on:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git next

- checked with:

$ ./scripts/checkpatch.pl 0002-mpc5200-support-for-the-MAN-mpc5200-based-board-muc.patch
total: 0 errors, 0 warnings, 368 lines checked

0002-mpc5200-support-for-the-MAN-mpc5200-based-board-muc.patch has no obvious style problems and is ready for submission. $

changes since v1:

 arch/powerpc/boot/dts/mucmc52.dts            |  353 ++++++++++++++++++++++++++
 arch/powerpc/configs/mpc5200_defconfig       |    2 +-
 arch/powerpc/platforms/52xx/mpc5200_simple.c |    1 +
 3 files changed, 355 insertions(+), 1 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/mucmc52.dts

arch/powerpc/boot/dts/mucmc52.dts new file +353 -0

new file mode 100644
index 0000000..88ad3e7
@@ -0,0 +1,353 @@
+/*
+ * mucmc52 board Device Tree Source
+ *
+ * Copyright (C) 2009 DENX Software Engineering GmbH
+ * Heiko Schocher <[email protected]>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+	model = "manroland,mucmc52";
+	compatible = "manroland,mucmc52";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&mpc5200_pic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,5200@0 {
+			device_type = "cpu";
+			reg = <0>;
+			d-cache-line-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x4000>;	// L1, 16K
+			i-cache-size = <0x4000>;	// L1, 16K
+			timebase-frequency = <0>;	// from bootloader
+			bus-frequency = <0>;		// from bootloader
+			clock-frequency = <0>;		// from bootloader
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x04000000>;	// 64MB
+	};
+
+	soc5200@f0000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fsl,mpc5200-immr",
+				"fsl,mpc5200b-immr";
+		ranges = <0 0xf0000000 0x0000c000>;
+		reg = <0xf0000000 0x00000100>;
+		bus-frequency = <0>;		// from bootloader
+		system-frequency = <0>;		// from bootloader
+
+		cdm@200 {
+			compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
+			reg = <0x200 0x38>;
+		};
+
+		mpc5200_pic: interrupt-controller@500 {
+			// 5200 interrupts are encoded into two levels;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
+			reg = <0x500 0x80>;
+			interrupts = <0 0 3>;
+		};
+
+		gpt0: timer@600 {	// GPT 0 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x600 0x10>;
+			interrupts = <1 9 0>;
+			gpio-controller;
+		};
+
+		gpt1: timer@610 {	// GPT 1 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x610 0x10>;
+			interrupts = <1 10 0>;
+			gpio-controller;
+		};
+
+		gpt2: timer@620 {	// GPT 2 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x620 0x10>;
+			interrupts = <1 11 0>;
+			gpio-controller;
+		};
+
+		gpt3: timer@630 {	// GPT 3 in GPIO mode
+			compatible = "fsl,mpc5200b-gpt-gpio",
+					"fsl,mpc5200-gpt-gpio";
+			#gpio-cells = <2>;
+			reg = <0x630 0x10>;
+			interrupts = <1 12 0>;
+			gpio-controller;
+		};
+
+		gpio_simple: gpio@b00 {
+			compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
+			#gpio-cells = <2>;
+			reg = <0xb00 0x40>;
+			interrupts = <1 7 0>;
+			gpio-controller;
+		};
+
+		gpio_wkup: gpio@c00 {
+			compatible = "fsl,mpc5200b-gpio-wkup",
+					"fsl,mpc5200-gpio-wkup";
+			#gpio-cells = <2>;
+			reg = <0xc00 0x40>;
+			interrupts = <1 8 0 0 3 0>;
+			gpio-controller;
+		};
+
+		dma-controller@1200 {
+			device_type = "dma-controller";
+			compatible = "fsl,mpc5200b-bestcomm",
+					"fsl,mpc5200-bestcomm";
+			reg = <0x1200 0x80>;
+			interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
+			              3 4 0  3 5 0  3 6 0  3 7 0
+			              3 8 0  3 9 0  3 10 0  3 11 0
+			              3 12 0  3 13 0  3 14 0  3 15 0>;
+		};
+
+		xlb@1f00 {
+			compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
+			reg = <0x1f00 0x100>;
+		};
+
+		serial@2000 {		// PSC1
+			compatible = "fsl,mpc5200b-psc-uart",
+					"fsl,mpc5200-psc-uart";
+			reg = <0x2000 0x100>;
+			interrupts = <2 1 0>;
+		};
+
+		serial@2200 {		// PSC2
+			compatible = "fsl,mpc5200b-psc-uart",
+					"fsl,mpc5200-psc-uart";
+			reg = <0x2200 0x100>;
+			interrupts = <2 2 0>;
+		};
+
+		serial@2c00 {		// PSC6
+			compatible = "fsl,mpc5200b-psc-uart",
+					"fsl,mpc5200-psc-uart";
+			reg = <0x2c00 0x100>;
+			interrupts = <2 6 0>;
+		};
+
+		ethernet@3000 {
+			compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
+			reg = <0x3000 0x400>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <2 5 0>;
+			phy-handle = <&phy0>;
+		};
+
+		mdio@3000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
+			reg = <0x3000 0x400>; 	// fec range, since we need to
+						// setup fec interrupts
+			interrupts = <2 5 0>; 	// these are for "mii command
+						// finished", not link changes
+						//  & co.
+
+			phy0: ethernet-phy@0 {
+				compatible = "intel,lxt971";
+				reg = <0>;
+			};
+		};
+
+		ata@3a00 {
+			compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
+			reg = <0x3a00 0x100>;
+			interrupts = <2 7 0>;
+		};
+
+		i2c@3d40 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c",
+					"fsl-i2c";
+			reg = <0x3d40 0x40>;
+			interrupts = <2 16 0>;
+
+			hwmon@2c {
+				compatible = "ad,adm9240";
+				reg = <0x2c>;
+			};
+			rtc@51 {
+				compatible = "nxp,pcf8563";
+				reg = <0x51>;
+			};
+		};
+
+		sram@8000 {
+			compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
+			reg = <0x8000 0x4000>;
+		};
+
+		wdt {
+			compatible = "generic,gpio-wdt";
+			reg = <0x600 0x10>;
+			gpios = <&gpt0 0 0>;
+			period = <500>;	// WDT trigger period in msec
+		};
+	};
+
+	localbus {
+		compatible = "fsl,mpc5200b-lpb","simple-bus";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges = <0 0 0xff800000 0x00800000
+			  1 0 0x80000000 0x00800000
+			  3 0 0x80000000 0x00800000>;
+
+		flash@0,0 {
+			compatible = "cfi-flash";
+			reg = <0 0 0x00800000>;
+			bank-width = <4>;
+			device-width = <2>;
+			#size-cells = <1>;
+			#address-cells = <1>;
+			partition@0 {
+				label = "DTS";
+				reg = <0x0 0x00100000>;
+			};
+			partition@100000 {
+				label = "Kernel";
+				reg = <0x100000 0x00200000>;
+			};
+			partition@300000 {
+				label = "RootFS";
+				reg = <0x00300000 0x00200000>;
+			};
+			partition@500000 {
+				label = "user";
+				reg = <0x00500000 0x00200000>;
+			};
+			partition@700000 {
+				label = "U-Boot";
+				reg = <0x00700000 0x00040000>;
+			};
+			partition@740000 {
+				label = "Env";
+				reg = <0x00740000 0x00020000>;
+			};
+			partition@760000 {
+				label = "red. Env";
+				reg = <0x00760000 0x00020000>;
+			};
+			partition@780000 {
+				label = "reserve";
+				reg = <0x00780000 0x00080000>;
+			};
+		};
+
+		simple100: gpio-controller-100@3,600100 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600100 0x1>;
+				gpio-controller;
+		};
+		simple104: gpio-controller-104@3,600104 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600104 0x1>;
+				gpio-controller;
+		};
+		simple200: gpio-controller-200@3,600200 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600200 0x1>;
+				gpio-controller;
+		};
+		simple201: gpio-controller-201@3,600201 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600201 0x1>;
+				gpio-controller;
+		};
+		simple202: gpio-controller-202@3,600202 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600202 0x1>;
+				gpio-controller;
+		};
+		simple203: gpio-controller-203@3,600203 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600203 0x1>;
+				gpio-controller;
+		};
+		simple204: gpio-controller-204@3,600204 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600204 0x1>;
+				gpio-controller;
+		};
+		simple206: gpio-controller-206@3,600206 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600206 0x1>;
+				gpio-controller;
+		};
+		simple207: gpio-controller-207@3,600207 {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x00600207 0x1>;
+				gpio-controller;
+		};
+		simple20f: gpio-controller-20f@3,60020f {
+				#gpio-cells = <2>;
+				compatible = "manroland,mucmc52-aux-gpio";
+				reg = <3 0x0060020f 0x1>;
+				gpio-controller;
+		};
+
+	};
+
+	pci@f0000d00 {
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		device_type = "pci";
+		compatible = "fsl,mpc5200-pci";
+		reg = <0xf0000d00 0x100>;
+		interrupt-map-mask = <0xf800 0 0 7>;
+		interrupt-map = <
+				/* IDSEL 0x10 */
+				0x8000 0 0 1 &mpc5200_pic 0 3 3
+				0x8000 0 0 2 &mpc5200_pic 0 3 3
+				0x8000 0 0 3 &mpc5200_pic 0 2 3
+				0x8000 0 0 4 &mpc5200_pic 0 1 3
+				>;
+		clock-frequency = <0>; // From boot loader
+		interrupts = <2 8 0 2 9 0 2 10 0>;
+		bus-range = <0 0>;
+		ranges = <0x42000000 0 0x60000000 0x60000000 0 0x10000000
+			  0x02000000 0 0x90000000 0x90000000 0 0x10000000
+			  0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
+	};
+};

arch/powerpc/configs/mpc5200_defconfig +1 -1

index aaa4416..d035421 100644
@@ -205,7 +205,7 @@ CONFIG_RTAS_PROC=y
 CONFIG_PPC_BESTCOMM=y
 CONFIG_PPC_BESTCOMM_ATA=y
 CONFIG_PPC_BESTCOMM_FEC=y
-# CONFIG_SIMPLE_GPIO is not set
+CONFIG_SIMPLE_GPIO=y
 
 #
 # Kernel options

arch/powerpc/platforms/52xx/mpc5200_simple.c +1 -0

index caf6d92..d45be5b 100644
@@ -51,6 +51,7 @@ static void __init mpc5200_simple_setup_arch(void)
 /* list of the supported boards */
 static char *board[] __initdata = {
 	"intercontrol,digsy-mtc",
+	"manroland,mucmc52",
 	"manroland,uc101",
 	"phytec,pcm030",
 	"phytec,pcm032",

Signature · 5 lines

1.6.0.6

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Grant Likely

2009-09-14 13:43 UTC #18 lore raw

In reply to Heiko Schocher

Hi Heiko.

Comments below.

Quoted 11 lines · Heiko Schocher

- serial Console on PSC1
- 64MB SDRAM
- MTD CFI Flash
- Ethernet FEC
- I2C with PCF8563 and Temp. Sensor ADM9240
- IDE support
Signed-off-by Heiko Schocher <[email protected]>
=A0arch/powerpc/boot/dts/mucmc52.dts =A0 =A0 =A0 =A0 =A0 =A0| =A0231 ++++ =A0arch/powerpc/configs/52xx/mucmc52_defconfig =A0| 1476 ++++++++++++++++=

++++++++++

Same comment as on your other patch. Drop the defconfig and add the needed bits to mpc5200_defconfig (in a separate patch, and add drivers as modules).

arch/powerpc/boot/dts/mu=

Quoted 1 line

arch/powerpc/boot/dts/mu= renamed from arch/powerpc/boot/dts/mucmc52.dts +0 -0

cmc52.dts

arch/powerpc/boot/dts/mucmc52.dts line 7

Quoted 12 lines

new file mode 100644
index 0000000..a4a7a20

arch/powerpc/boot/dts/mucmc52.dts new file +7 -0

@@ -0,0 +1,231 @@
+/*
+ * mucmc52 board Device Tree Source
+ *
+ * Copyright (C) 2009 DENX Software Engineering GmbH
+ * Heiko Schocher <[email protected]>
+ *
+ * This program is free software; you can redistribute =A0it and/or modi=

fy it

arch/powerpc/boot/dts/mucmc52.dts line 8

Quoted 1 line

arch/powerpc/boot/dts/mucmc52.dts new file +1 -0
+ * under =A0the terms of =A0the GNU General =A0Public License as publish=

ed by the

arch/powerpc/boot/dts/mucmc52.dts line 9

Quoted 1 line

arch/powerpc/boot/dts/mucmc52.dts new file +1 -0
+ * Free Software Foundation; =A0either version 2 of the =A0License, or (=

at your

Quoted 12 lines

arch/powerpc/boot/dts/mucmc52.dts new file +12 -0

+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+ =A0 =A0 =A0 model =3D "man,mucmc52";
+ =A0 =A0 =A0 compatible =3D "man,mucmc52";
+ =A0 =A0 =A0 #address-cells =3D <1>;
+ =A0 =A0 =A0 #size-cells =3D <1>;
+ =A0 =A0 =A0 interrupt-parent =3D <&mpc5200_pic>;
+

arch/powerpc/boot/dts/mucmc52.dts line 31

Quoted 10 lines

arch/powerpc/boot/dts/mucmc52.dts new file +10 -0

+ =A0 =A0 =A0 cpus {
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 #address-cells =3D <1>;
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 #size-cells =3D <0>;
+
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 PowerPC,5200@0 {
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 device_type =3D "cpu";
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0>;
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 d-cache-line-size =3D <32>;
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 i-cache-line-size =3D <32>;
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 d-cache-size =3D <0x4000>; =

=A0 =A0 =A0 =A0// L1, 16K

arch/powerpc/boot/dts/mucmc52.dts line 32

Quoted 1 line

arch/powerpc/boot/dts/mucmc52.dts new file +1 -0
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 i-cache-size =3D <0x4000>; =

=A0 =A0 =A0 =A0// L1, 16K

arch/powerpc/boot/dts/mucmc52.dts line 33

Quoted 1 line

arch/powerpc/boot/dts/mucmc52.dts new file +1 -0
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 timebase-frequency =3D <0>;=

=A0 =A0 =A0 // from bootloader

arch/powerpc/boot/dts/mucmc52.dts line 34

Quoted 1 line

arch/powerpc/boot/dts/mucmc52.dts new file +1 -0
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 bus-frequency =3D <0>; =A0 =

=A0 =A0 =A0 =A0 =A0// from bootloader

arch/powerpc/boot/dts/mucmc52.dts line 35

Quoted 1 line

arch/powerpc/boot/dts/mucmc52.dts new file +1 -0
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 clock-frequency =3D <0>; =

=A0 =A0 =A0 =A0 =A0// from bootloader

arch/powerpc/boot/dts/mucmc52.dts line 47

Quoted 12 lines

arch/powerpc/boot/dts/mucmc52.dts new file +12 -0

+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
+ =A0 =A0 =A0 };
+
+ =A0 =A0 =A0 memory {
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 device_type =3D "memory";
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x00000000 0x04000000>; =A0// 64MB
+ =A0 =A0 =A0 };
+
+ =A0 =A0 =A0 soc5200@f0000000 {
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 #address-cells =3D <1>;
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 #size-cells =3D <1>;
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5200-immr";

Does this board use the older and rarer non-'B' mpc5200 part? If not, then fsl,mpc5200b-immr also needs to be in this list.

Cheers,
g.

--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Heiko Schocher

author

2009-09-14 14:18 UTC #19 lore raw

Hello Grant,

Quoted 10 lines · Grant Likely

Comments below.
Quoted 7 lines · Heiko Schocher
- serial Console on PSC1
- 64MB SDRAM
- MTD CFI Flash
- Ethernet FEC
- I2C with PCF8563 and Temp. Sensor ADM9240
- IDE support

Quoted 8 lines

Quoted 4 lines
Signed-off-by Heiko Schocher <[email protected]>
 arch/powerpc/boot/dts/mucmc52.dts            |  231 ++++
 arch/powerpc/configs/52xx/mucmc52_defconfig  | 1476 ++++++++++++++++++++++++++
Same comment as on your other patch. Drop the defconfig and add the needed bits to mpc5200_defconfig (in a separate patch, and add drivers as modules).

Yep, thanks. I look, how this works.

Quoted 48 lines

arch/powerpc/boot/dts/mucmc52.dts new file +42 -0

new file mode 100644
index 0000000..a4a7a20
@@ -0,0 +1,231 @@
+/*
+ * mucmc52 board Device Tree Source
+ *
+ * Copyright (C) 2009 DENX Software Engineering GmbH
+ * Heiko Schocher <[email protected]>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+       model = "man,mucmc52";
+       compatible = "man,mucmc52";
+       #address-cells = <1>;
+       #size-cells = <1>;
+       interrupt-parent = <&mpc5200_pic>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               PowerPC,5200@0 {
+                       device_type = "cpu";
+                       reg = <0>;
+                       d-cache-line-size = <32>;
+                       i-cache-line-size = <32>;
+                       d-cache-size = <0x4000>;        // L1, 16K
+                       i-cache-size = <0x4000>;        // L1, 16K
+                       timebase-frequency = <0>;       // from bootloader
+                       bus-frequency = <0>;            // from bootloader
+                       clock-frequency = <0>;          // from bootloader
+               };
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0x00000000 0x04000000>;  // 64MB
+       };

Quoted 8 lines

arch/powerpc/boot/dts/mucmc52.dts line 47
Quoted 5 lines
arch/powerpc/boot/dts/mucmc52.dts new file +5 -0
+
+       soc5200@f0000000 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "fsl,mpc5200-immr";
Does this board use the older and rarer non-'B' mpc5200 part? If not, then fsl,mpc5200b-immr also needs to be in this list.

OK, I add this too

Thanks

bye
Heiko

Signature · 2 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Grant Likely

2009-09-14 14:48 UTC #20 lore raw

Quoted 11 lines · Heiko Schocher

Quoted 8 lines · Grant Likely
Quoted 4 lines · Heiko Schocher
+ =A0 =A0 =A0 soc5200@f0000000 {
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 #address-cells =3D <1>;
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 #size-cells =3D <1>;
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5200-immr";
Does this board use the older and rarer non-'B' mpc5200 part? =A0If not, then fsl,mpc5200b-immr also needs to be in this list.
OK, I add this too

Okay, then before you resubmit, do a side-by-side comparison between this file and one of the existing mpc5200b dts files. There are numerous fsl,mpc5200b-* compatible values that need to be present.

--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.