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About ARM TCM patch

DISCUSSION Peter Chen 3 participants 5 messages Sep 25, 2009 – Sep 27, 2009

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Peter Chen

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#0 lore raw

Dear ML,

I read the TCM patch from http://lwn.net/Articles/353032/

It said:
Code executing inside the ITCM does not "see" any MMU mappings and e.g. register accesses must be made to physical addresses.

I am doubt it is correctly for all systems, at my SoC platform(arm1136JF, v6), the situation is difference.

1. After MMU open, the code running at ITCM can't see physical address for register.

2. After MMU open, the code can't run at physical addressed ITCM.

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Best regards,
Peter Chen
#1 lore raw

Hi Peter,

Quoted 8 lines · Peter Chen

Dear ML,

I read the TCM patch from http://lwn.net/Articles/353032/

It said:
Code executing inside the ITCM does not "see" any MMU mappings and e.g. register accesses must be made to physical addresses.

Quoted 7 lines

I am doubt it is correctly for all systems, at my SoC platform(arm1136JF, v6), the situation is difference.

1. After MMU open, the code running at ITCM can't see physical address for register.

2. After MMU open, the code can't run at physical addressed ITCM.

That's my understanding as well. Once the MMU is enabled, ALL access go through the MMU, whether they originate from the ITCM or not.

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Dave Hylands
Shuswap, BC, Canada
http://www.DaveHylands.com/
#3 lore raw

2009/9/25 Linus Walleij <[email protected]>:

Quoted 8 lines

2009/9/25 Peter Chen <[email protected]>:

Quoted 4 lines

1. After MMU open, the code running at ITCM can't see physical address for register.

2. After MMU open, the code can't run at physical addressed ITCM.

Could this be different between ARM9 (which I use) and ARM11?

Thinking about it this rings a bell. I know it behaves like described on ARM9, so code executing in TCM can only "see" physical memory.

But one difference between the ARM9 and ARM11 families is that the cache is mapped to virtual (MMU:ed) address space in ARM9 and to physical address space in ARM11 is it not? (Is this so already in ARM10 BTW?)

So just thinking intuitively about it, as a TCM memory is very close to what a cache is to the CPU I think it's something like this on ARM9:

     CPU
     / \
Cache   TCM
  |      |
 MMU     |
  |      |

External memory interface

But on ARM11 (ARM10?):

     CPU
      |
     MMU
     / \

Cache TCM
|
External memory interface

Is that correct more or less? Catalin would you happen to know this?

Anyway the code should still work actually, since we make a 1-1 memory map anyway. But you cannot place the TCM in the memory locations I chose for U300 since these are occupied on ARM11.

Linus Walleij

author
#4 lore raw
Quoted 34 lines · Linus Walleij

2009/9/25 Linus Walleij <[email protected]>:

Quoted 8 lines

2009/9/25 Peter Chen <[email protected]>:

Quoted 4 lines

1. After MMU open, the code running at ITCM can't see physical address for register.

2. After MMU open, the code can't run at physical addressed ITCM.

Could this be different between ARM9 (which I use) and ARM11?

Thinking about it this rings a bell. I know it behaves like described on ARM9, so code executing in TCM can only "see" physical memory.

But one difference between the ARM9 and ARM11 families is that the cache is mapped to virtual (MMU:ed) address space in ARM9 and to physical address space in ARM11 is it not? (Is this so already in ARM10 BTW?)

So just thinking intuitively about it, as a TCM memory is very close to what a cache is to the CPU I think it's something like this on ARM9:

     CPU
     / \
Cache   TCM
  |      |
 MMU     |
  |      |

External memory interface

But on ARM11 (ARM10?):

     CPU
      |
     MMU
     / \
Quoted 5 lines

Cache TCM
|
External memory interface

Is that correct more or less? Catalin would you happen to know this?

I think you are right.

Quoted 3 lines

Anyway the code should still work actually, since we make a 1-1 memory map anyway. But you cannot place the TCM in the memory locations I chose for U300 since these are occupied on ARM11.

Sorry, I haven't tried your patch at kernel, I just did experiments at u-boot.

Quoted 1 line

Linus Walleij

Signature · 2 lines
Best Regards
Peter Chen