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Why flush_cache_all() not including flushing L2 cache if the system has L2 cache?

DISCUSSION Peter Chen 3 participants 5 messages Nov 2, 2009 – Nov 3, 2009

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Peter Chen

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#0 lore raw

Dear list,

I met a problem if the address is first used by cachable, then uncachable. After that, the address will be filled with cachable value after that L2 cache line is evicted.

Thank you!

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Peter Chen
#1 lore raw
Quoted 6 lines · Peter Chen

Dear list,

I met a problem if the address is first used by cachable, then uncachable. After that, the address will be filled with cachable value after that L2 cache line is evicted.

L2 cache is usually physically tagged, and from the CPU POV, it's consistent once the L1 is flushed.

If you have problems with L2 not being flushed, it's most likely a device issue, which means you probably need the dma_ API.

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#2 lore raw
Quoted 10 lines · Eric Miao
Quoted 6 lines · Peter Chen

Dear list,

I met a problem if the address is first used by cachable, then uncachable. After that, the address will be filled with cachable value after that L2 cache line is evicted.

L2 cache is usually physically tagged, and from the CPU POV, it's consistent once the L1 is flushed.

My SoC platform is arm11, and L2 is PIPT. what do you mean " from the CPU POV, it's consistent once the L1 is flushed"?

Quoted 4 lines

If you have problems with L2 not being flushed, it's most likely a device issue, which means you probably need the dma_ API.

I know it can be fixed by using dma_ API for alloc uncachable address. But If someone uses uncachable memory address before flush it, it is problem. Since L1 should be flushed at code, why L2 not?

Thank you!

Signature · 2 lines
Best regards,
Peter Chen
#3 lore raw
In reply to Peter Chen
Quoted 3 lines · Peter Chen

I met a problem if the address is first used by cachable, then uncachable. After that, the address will be filled with cachable value after that L2 cache line is evicted.

What _exactly_ are you trying to do? Why are you apparantly mapping something in as cacheable, and then making it uncacheable?

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#4 lore raw
Quoted 8 lines · Russell King - ARM Linux
Quoted 3 lines · Peter Chen

I met a problem if the address is first used by cachable, then uncachable. After that, the address will be filled with cachable value after that L2 cache line is evicted.

What _exactly_ are you trying to do? Why are you apparantly mapping something in as cacheable, and then making it uncacheable?

This is 3rd party released code

This problem happens at device driver wants to alloc uncachable memory, but it doesn't alloc it using dma_ API.

Signature · 2 lines
Best regards,
Peter Chen