ep93xx: define magic numbers for pll1 and pll2

PATCH New H Hartley Sweeten 2 participants 5 messages Dec 30, 2009 – Jan 11, 2010

Subsystems (3)

Arm (32-bit) Arm sub-architectures Arm/Cirrus logic EP93XX Arm architecture

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H Hartley Sweeten

author

2009-12-30 16:56 UTC #0 lore raw

PATCH 1/1 ep93xx: define magic numbers for pll1 and pll2

Add defines for the pll register magic numbers that determine if the pll's are bypassed and if pll2 is enabled. Rename the clock set registers to more closely match the datasheet. Also, remove the unnecessary braces since each conditional statement is a single statement.

Signed-off-by H Hartley Sweeten <[email protected]>

Cc Ryan Mallon <[email protected]>

---

arch/arm/mach-ep93xx/clock.c +12 -8

index 1d0f9d8..f77c410 100644
@@ -447,25 +447,29 @@ static int __init ep93xx_clock_init(void)
 	u32 value;
 	int i;
 
-	value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1);
-	if (!(value & 0x00800000)) {			/* PLL1 bypassed?  */
+	/* Determine the bootloader configured pll1 rate */
+	value = __raw_readl(EP93XX_SYSCON_CLKSET1);
+	if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1))
 		clk_pll1.rate = clk_xtali.rate;
-	} else {
+	else
 		clk_pll1.rate = calc_pll_rate(value);
-	}
+
+	/* Initialize the pll1 derived clocks */
 	clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
 	clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
 	clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
 	ep93xx_dma_clock_init();
 
+	/* Determine the bootloader configured pll2 rate */
 	value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2);
-	if (!(value & 0x00080000)) {			/* PLL2 bypassed?  */
+	if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2))
 		clk_pll2.rate = clk_xtali.rate;
-	} else if (value & 0x00040000) {		/* PLL2 enabled?  */
+	else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)
 		clk_pll2.rate = calc_pll_rate(value);
-	} else {
+	else
 		clk_pll2.rate = 0;
-	}
+
+	/* Initialize the pll2 derived clocks */
 	clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);
 
 	printk(KERN_INFO "ep93xx: PLL1 running at %ld MHz, PLL2 at %ld MHz\n",

arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h +5 -2

index d55194a..cd35912 100644
@@ -167,8 +167,11 @@
 #define EP93XX_SYSCON_PWRCNT_DMA_M2P1	(1<<16)
 #define EP93XX_SYSCON_HALT		EP93XX_SYSCON_REG(0x08)
 #define EP93XX_SYSCON_STANDBY		EP93XX_SYSCON_REG(0x0c)
-#define EP93XX_SYSCON_CLOCK_SET1	EP93XX_SYSCON_REG(0x20)
-#define EP93XX_SYSCON_CLOCK_SET2	EP93XX_SYSCON_REG(0x24)
+#define EP93XX_SYSCON_CLKSET1		EP93XX_SYSCON_REG(0x20)
+#define EP93XX_SYSCON_CLKSET1_NBYP1	(1<<23)
+#define EP93XX_SYSCON_CLKSET2		EP93XX_SYSCON_REG(0x24)
+#define EP93XX_SYSCON_CLKSET2_NBYP2	(1<<19)
+#define EP93XX_SYSCON_CLKSET2_PLL2_EN	(1<<18)
 #define EP93XX_SYSCON_DEVCFG		EP93XX_SYSCON_REG(0x80)
 #define EP93XX_SYSCON_DEVCFG_SWRST	(1<<31)
 #define EP93XX_SYSCON_DEVCFG_D1ONG	(1<<30)

Ryan Mallon

2010-01-11 01:05 UTC #1 lore raw

PATCH 1/1 ep93xx: define magic numbers for pll1 and pll2

Quoted 61 lines · H Hartley Sweeten

Signed-off-by H Hartley Sweeten <[email protected]>

Cc Ryan Mallon <[email protected]>

---

arch/arm/mach-ep93xx/clock.c +12 -8

index 1d0f9d8..f77c410 100644
@@ -447,25 +447,29 @@ static int __init ep93xx_clock_init(void)
 	u32 value;
 	int i;
 
-	value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1);
-	if (!(value & 0x00800000)) {			/* PLL1 bypassed?  */
+	/* Determine the bootloader configured pll1 rate */
+	value = __raw_readl(EP93XX_SYSCON_CLKSET1);
+	if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1))
 		clk_pll1.rate = clk_xtali.rate;
-	} else {
+	else
 		clk_pll1.rate = calc_pll_rate(value);
-	}
+
+	/* Initialize the pll1 derived clocks */
 	clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
 	clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
 	clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
 	ep93xx_dma_clock_init();
 
+	/* Determine the bootloader configured pll2 rate */
 	value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2);
-	if (!(value & 0x00080000)) {			/* PLL2 bypassed?  */
+	if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2))
 		clk_pll2.rate = clk_xtali.rate;
-	} else if (value & 0x00040000) {		/* PLL2 enabled?  */
+	else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)
 		clk_pll2.rate = calc_pll_rate(value);
-	} else {
+	else
 		clk_pll2.rate = 0;
-	}
+
+	/* Initialize the pll2 derived clocks */
 	clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);
 
 	printk(KERN_INFO "ep93xx: PLL1 running at %ld MHz, PLL2 at %ld MHz\n",

arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h +0 -0

index d55194a..cd35912 100644
@@ -167,8 +167,11 @@
 #define EP93XX_SYSCON_PWRCNT_DMA_M2P1	(1<<16)
 #define EP93XX_SYSCON_HALT		EP93XX_SYSCON_REG(0x08)
 #define EP93XX_SYSCON_STANDBY		EP93XX_SYSCON_REG(0x0c)

arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h line 177

Quoted 10 lines

arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h +5 -2

-#define EP93XX_SYSCON_CLOCK_SET1	EP93XX_SYSCON_REG(0x20)
-#define EP93XX_SYSCON_CLOCK_SET2	EP93XX_SYSCON_REG(0x24)
+#define EP93XX_SYSCON_CLKSET1		EP93XX_SYSCON_REG(0x20)
+#define EP93XX_SYSCON_CLKSET1_NBYP1	(1<<23)
+#define EP93XX_SYSCON_CLKSET2		EP93XX_SYSCON_REG(0x24)
+#define EP93XX_SYSCON_CLKSET2_NBYP2	(1<<19)
+#define EP93XX_SYSCON_CLKSET2_PLL2_EN	(1<<18)
 #define EP93XX_SYSCON_DEVCFG		EP93XX_SYSCON_REG(0x80)
 #define EP93XX_SYSCON_DEVCFG_SWRST	(1<<31)
 #define EP93XX_SYSCON_DEVCFG_D1ONG	(1<<30)

Looks okay. If the clock registers are only ever used inside clock.c should we move them there to cut down the size of ep93xx-regs.h?

~Ryan

Signature · 7 lines

Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
[email protected]         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934

H Hartley Sweeten

author

2010-01-11 18:31 UTC #2 lore raw

PATCH 1/1 ep93xx: define magic numbers for pll1 and pll2

Quoted 12 lines · Ryan Mallon

Quoted 11 lines · H Hartley Sweeten
Add defines for the pll register magic numbers that determine if the pll's are bypassed and if pll2 is enabled. Rename the clock set registers to more closely match the datasheet. Also, remove the unnecessary braces since each conditional statement is a single statement.
Signed-off-by H Hartley Sweeten <[email protected]>
Cc Ryan Mallon <[email protected]>
---

[snip]

Quoted 13 lines

arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h +3 -2

index d55194a..cd35912 100644
@@ -167,8 +167,11 @@
 #define EP93XX_SYSCON_PWRCNT_DMA_M2P1	(1<<16)
 #define EP93XX_SYSCON_HALT		EP93XX_SYSCON_REG(0x08)
 #define EP93XX_SYSCON_STANDBY		EP93XX_SYSCON_REG(0x0c)
-#define EP93XX_SYSCON_CLOCK_SET1	EP93XX_SYSCON_REG(0x20)
-#define EP93XX_SYSCON_CLOCK_SET2	EP93XX_SYSCON_REG(0x24)
+#define EP93XX_SYSCON_CLKSET1		EP93XX_SYSCON_REG(0x20)
+#define EP93XX_SYSCON_CLKSET1_NBYP1	(1<<23)
+#define EP93XX_SYSCON_CLKSET2		EP93XX_SYSCON_REG(0x24)

Quoted 8 lines

arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h line 177
Quoted 5 lines
arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h +2 -0
+#define EP93XX_SYSCON_CLKSET2_NBYP2	(1<<19)
+#define EP93XX_SYSCON_CLKSET2_PLL2_EN	(1<<18)
 #define EP93XX_SYSCON_DEVCFG		EP93XX_SYSCON_REG(0x80)
 #define EP93XX_SYSCON_DEVCFG_SWRST	(1<<31)
 #define EP93XX_SYSCON_DEVCFG_D1ONG	(1<<30) 
Looks okay. If the clock registers are only ever used inside clock.c should we move them there to cut down the size of ep93xx-regs.h?

For right now I would like to keep all the 'SYSCON' defines in the header. All of the other peripherals have a specific driver that it makes sense to move the register defines into and then access them using the offset from the base address. The SysCon registers are a bit unique in that many subsystems need access for various reasons.

Eventually a lot of them can be moved into clock.c but for right now lets just leave them in the header.

Is that an Acked-by?

Regards,
Hartley

Ryan Mallon

2010-01-11 19:43 UTC #3 lore raw

PATCH 1/1 ep93xx: define magic numbers for pll1 and pll2

Quoted 37 lines · H Hartley Sweeten

Quoted 12 lines · Ryan Mallon
Quoted 11 lines · H Hartley Sweeten
Add defines for the pll register magic numbers that determine if the pll's are bypassed and if pll2 is enabled. Rename the clock set registers to more closely match the datasheet. Also, remove the unnecessary braces since each conditional statement is a single statement.
Signed-off-by H Hartley Sweeten <[email protected]>
Cc Ryan Mallon <[email protected]>
---
[snip]
Quoted 12 lines
Quoted 12 lines
arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h +2 -2
index d55194a..cd35912 100644
@@ -167,8 +167,11 @@
 #define EP93XX_SYSCON_PWRCNT_DMA_M2P1	(1<<16)
 #define EP93XX_SYSCON_HALT		EP93XX_SYSCON_REG(0x08)
 #define EP93XX_SYSCON_STANDBY		EP93XX_SYSCON_REG(0x0c)
-#define EP93XX_SYSCON_CLOCK_SET1	EP93XX_SYSCON_REG(0x20)
-#define EP93XX_SYSCON_CLOCK_SET2	EP93XX_SYSCON_REG(0x24)
+#define EP93XX_SYSCON_CLKSET1		EP93XX_SYSCON_REG(0x20)
+#define EP93XX_SYSCON_CLKSET1_NBYP1	(1<<23)
Quoted 8 lines
arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h line 177
Quoted 6 lines
arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h +3 -0
+#define EP93XX_SYSCON_CLKSET2		EP93XX_SYSCON_REG(0x24)
+#define EP93XX_SYSCON_CLKSET2_NBYP2	(1<<19)
+#define EP93XX_SYSCON_CLKSET2_PLL2_EN	(1<<18)
 #define EP93XX_SYSCON_DEVCFG		EP93XX_SYSCON_REG(0x80)
 #define EP93XX_SYSCON_DEVCFG_SWRST	(1<<31)
 #define EP93XX_SYSCON_DEVCFG_D1ONG	(1<<30) 
Looks okay. If the clock registers are only ever used inside clock.c should we move them there to cut down the size of ep93xx-regs.h?

Quoted 8 lines

For right now I would like to keep all the 'SYSCON' defines in the header. All of the other peripherals have a specific driver that it makes sense to move the register defines into and then access them using the offset from the base address. The SysCon registers are a bit unique in that many subsystems need access for various reasons.
Eventually a lot of them can be moved into clock.c but for right now lets just leave them in the header.

Fair enough. We can look at this at some point in the future.

Quoted 1 line

Is that an Acked-by?

Yup.

Acked-by Ryan Mallon <[email protected]>

Signature · 7 lines

Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934

H Hartley Sweeten

author

2010-01-11 20:43 UTC #4 lore raw

PATCH 1/1 ep93xx: define magic numbers for pll1 and pll2

Quoted 9 lines · Ryan Mallon

Quoted 8 lines · H Hartley Sweeten
Quoted 7 lines · Ryan Mallon
Quoted 6 lines · H Hartley Sweeten
Add defines for the pll register magic numbers that determine if the pll's are bypassed and if pll2 is enabled. Rename the clock set registers to more closely match the datasheet. Also, remove the unnecessary braces since each conditional statement is a single statement.

Quoted 5 lines

Quoted 5 lines
Quoted 5 lines
Quoted 5 lines
Signed-off-by H Hartley Sweeten <[email protected]>
Cc Ryan Mallon <[email protected]>
---

Acked-by Ryan Mallon <[email protected]>

Thanks. This and the other ones are now in the patch system.

Regards,
Hartley