Initial support for Marvell Orion5x SoC

V4: all files licensed GPLv2-only removed;
RAM bank size detection now uses getm_ram_size().

-----Original Message-----
From: u-boot-bounces at lists.denx.de [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Albert Aribaud
Sent: Sunday, January 10, 2010 9:34 PM
To: U-Boot at lists.denx.de
Subject: [U-Boot] [PATCH V4 3/3] Add support for the LaCie ED Mini V2 board

This patch adds support for the LaCie ED Mini V2 product which is based on the Marvell Orion5x SoC. Current support is limited to console and Flash. Flash support uses CONFIG_FLASH_CFI_LEGACY as the Macronix MX29LV400 used on ED Mini V2 is not CFI compliant (mixes 16 and 8 bit behaviors).

Signed-off-by Albert Aribaud <[email protected]>

---
 MAINTAINERS                          |    4 +
 MAKEALL                              |    1 +
 Makefile                             |    3 +
 board/LaCie/edminiv2/Makefile        |   58 ++++++
 board/LaCie/edminiv2/config.mk       |   27 +++
 board/LaCie/edminiv2/edminiv2.c      |   88 +++++++++
 board/LaCie/edminiv2/edminiv2.h      |   59 ++++++
 board/LaCie/edminiv2/lowlevel_init.S |  324
++++++++++++++++++++++++++++++++++
 include/configs/edminiv2.h           |  147 +++++++++++++++
 9 files changed, 711 insertions(+), 0 deletions(-)
 create mode 100644 board/LaCie/edminiv2/Makefile
 create mode 100644 board/LaCie/edminiv2/config.mk
 create mode 100644 board/LaCie/edminiv2/edminiv2.c
 create mode 100644 board/LaCie/edminiv2/edminiv2.h
 create mode 100644 board/LaCie/edminiv2/lowlevel_init.S
 create mode 100644 include/configs/edminiv2.h

board/LaCie/edminiv2/config.mk new file +17 -0

new file mode 100644
index 0000000..91f2db9
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2009 Albert ARIBAUD <[email protected]>
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <[email protected]>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of

board/LaCie/edminiv2/edminiv2.c new file +40 -0

new file mode 100644
index 0000000..988de52
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2009 Albert ARIBAUD <[email protected]>
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/orion5x.h>
+#include "edminiv2.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * The ED Mini V2 is equipped with a Macronix MXLV400CB FLASH
+ * which CFI does not properly detect, hence the LEGACY config.
+ */
+#if defined(CONFIG_FLASH_CFI_LEGACY)
+#include <flash.h>
+ulong board_flash_get_legacy(ulong base, int banknum,

flash_info_t *info)

board/LaCie/edminiv2/edminiv2.c new file +23 -0

+{
+     int sectsz[] = CONFIG_SYS_FLASH_SECTSZ;
+     int sect;
+
+     if (base != CONFIG_SYS_FLASH_BASE)
+             return 0;
+
+     info->size = 0;
+     info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+     for (sect = 0; sect < CONFIG_SYS_MAX_FLASH_SECT; sect++) {
+             info->start[sect] = base+info->size;
+             info->size += sectsz[sect];
+     }
+     info->flash_id                  = 0x01000000;
+     info->portwidth = FLASH_CFI_8BIT;
+     info->chipwidth = FLASH_CFI_BY8;
+     info->buffer_size = 0;
+     info->erase_blk_tout = 1000;
+     info->write_tout = 10;
+     info->buffer_write_tout = 300;
+     info->vendor = CFI_CMDSET_AMD_LEGACY;
+     info->cmd_reset = 0xF0;
+     info->interface = FLASH_CFI_X8;

board/LaCie/edminiv2/edminiv2.c new file +15 -0

+
+     return 1;
+}
+#endif                               /* CONFIG_SYS_FLASH_CFI */
+
+int board_init(void)
+{
+     /* arch number of board */
+     gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2;
+
+     /* adress of boot parameters */
+     gd->bd->bi_boot_params = orion5x_sdram_bar(0) + 0x100;
+
+     return 0;
+}

board/LaCie/edminiv2/edminiv2.h new file +59 -0

new file mode 100644
index 0000000..88f4cee
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2009 Albert ARIBAUD <[email protected]>
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __EDMINIV2_H
+#define __EDMINIV2_H
+
+/*
+ * Internal register base - Linux expects 0xf1000000
+ */
+
+#define EDMINIV2_INTERNAL_BASE       0xf1000000
+
+/*
+ * MPPs:
+ * - MPPs 12 to 15 are SATA LEDs (mode 5)
+ * - Others are GPIO/unused (mode 3 for MPP0, mode 0 for others
+ */
+
+#define EDMINIV2_MPP0_7              0x00000003
+#define EDMINIV2_MPP8_15     0x55550000
+#define EDMINIV2_MPP16_23    0x00000000
+
+/*
+ * GPIOs:
+ * - GPIO3 is input (RTC interrupt)
+ * - GPIO16 is Power LED control (0 = on, 1 = off)
+ * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
+ * - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
+ * - Last GPIO is 26, further bits are supposed to be 0.
+ * Default is LED ON
+ */
+
+#define EDMINIV2_OE          0x03fcffff
+#define EDMINIV2_OE_VAL              0x00020000
+
+#endif /* __EDMINIV2_H */

board/LaCie/edminiv2/lowlevel_init.S new file +0 -0

new file mode 100644
index 0000000..891423f

board/LaCie/edminiv2/lowlevel_init.S new file +91 -0

+
+/*
+ * Low-level init happens right after start.S has switched to SVC32,
+ * flushed and disabled caches and disabled MMU. We're still running
+ * from the boot chip select, so the first thing we should do is set
+ * up RAM for us to relocate into.
+ */
+
+.globl lowlevel_init
+
+lowlevel_init:
+
+     /* Use 'r4 as the base for internal register accesses */
+     ldr     r4, =EDMINIV2_INTERNAL_BASE
+
+     /* move internal registers from the default 0xD0000000
+      * to their intended location of 0xf1000000 */
+     ldr     r3, =0xD0000000
+     add     r3, r3, #0x20000
+        str  r4, [r3, #0x80]
+
+     /* Use R3 as the base for Device Bus registers */
+     add     r3, r4, #0x10000
+
+     /* init MPPs */
+     ldr     r6, =EDMINIV2_MPP0_7
+     str     r6, [r3, #0x000]
+     ldr     r6, =EDMINIV2_MPP8_15
+     str     r6, [r3, #0x004]
+     ldr     r6, =EDMINIV2_MPP16_23
+     str     r6, [r3, #0x050]
+
+     /* init GPIOs */
+     ldr     r6, =EDMINIV2_GPIO_OUT_ENABLE
+     str     r6, [r3, #0x104]
+
+     /* Use R3 as the base for DRAM registers */
+     add     r3, r4, #0x01000
+
+     /*DDR SDRAM Initialization Control */
+     ldr     r6, =0x00000001
+     str     r6, [r3, #0x480]
+
+     /* Use R3 as the base for PCI registers */
+     add     r3, r4, #0x31000
+
+     /* Disable arbiter */
+     ldr     r6, =0x00000030
+     str     r6, [r3, #0xd00]
+
+     /* Use R3 as the base for DRAM registers */
+     add     r3, r4, #0x01000
+
+     /* set all dram windows to 0 */
+     mov     r6, #0
+     str     r6, [r3, #0x504]
+     str     r6, [r3, #0x50C]
+     str     r6, [r3, #0x514]
+     str     r6, [r3, #0x51C]
+
+     /* 1) Configure SDRAM  */
+     ldr     r6, =SDRAM_CONFIG
+     str     r6, [r3, #0x400]
+
+     /* 2) Set SDRAM Control reg */
+     ldr     r6, =SDRAM_CONTROL
+     str     r6, [r3, #0x404]
+
+        /* 3) Write SDRAM address control register */
+     ldr     r6, =SDRAM_ADDR_CTRL
+     str     r6, [r3, #0x410]
+
+        /* 4) Write SDRAM bank 0 size register */
+     ldr     r6, =SDRAM_BANK0_SIZE
+     str     r6, [r3, #0x504]
+     /* keep other banks disabled */
+
+        /* 5) Write SDRAM open pages control register */
+     ldr     r6, =SDRAM_OPEN_PAGE_EN
+     str     r6, [r3, #0x414]
+
+        /* 6) Write SDRAM timing Low register */
+     ldr     r6, =SDRAM_TIME_CTRL_LOW
+     str     r6, [r3, #0x408]
+
+        /* 7) Write SDRAM timing High register */
+     ldr     r6, =SDRAM_TIME_CTRL_HI
+     str     r6, [r3, #0x40C]
+
+        /* 8) Write SDRAM mode register */
+        /* The CPU must not attempt to change the SDRAM Mode

register setting */
+ /* prior to DRAM controller completion of the DRAM
initialization */
+ /* sequence. To guarantee this restriction, it is
recommended that */
+ /* the CPU sets the SDRAM Operation register to NOP
command, performs */
+ /* read polling until the register is back in Normal
operation value, */
+ /* and then sets SDRAM Mode register to its new
value. */

board/LaCie/edminiv2/lowlevel_init.S new file +12 -0

+
+     /* 8.1 write 'nop' to SDRAM operation */
+        ldr  r6, =SDRAM_OP_NOP
+     str     r6, [r3, #0x418]
+
+        /* 8.2 poll SDRAM operation until back in 'normal' mode.  */
+1:
+     ldr     r6, [r3, #0x418]
+     cmp     r6, #0
+     bne     1b
+
+        /* 8.3 Now its safe to write new value to SDRAM Mode

register */

board/LaCie/edminiv2/lowlevel_init.S new file +26 -0

+     ldr     r6, =SDRAM_MODE
+     str     r6, [r3, #0x41C]
+
+        /* 8.4 Set new mode */
+        ldr  r6, =SDRAM_OP_SETMODE
+     str     r6, [r3, #0x418]
+
+        /* 8.5 poll SDRAM operation until back in 'normal' mode.  */
+2:
+     ldr     r6, [r3, #0x418]
+     cmp     r6, #0
+     bne     2b
+
+        /* DDR SDRAM Address/Control Pads Calibration */
+     ldr     r6, [r3, #0x4C0]
+
+        /* Set Bit [31] to make the register writable
           */
+     orr     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     str     r6, [r3, #0x4C0]
+
+     bic     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     bic     r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
+     bic     r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
+     bic     r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
+
+        /* Get the final N locked value of driving strength

[22:17] */

board/LaCie/edminiv2/lowlevel_init.S new file +3 -0

+        mov   r1, r6
+        mov   r1, r1, LSL #9
+        mov   r1, r1, LSR #26    /* r1[5:0]<DrvN>  =

r3[22:17]<LockN> */
+ orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> =
r1[5:0]<DrvN> */

board/LaCie/edminiv2/lowlevel_init.S new file +2 -0

+
+        /* Write to both <DrvN> bits [5:0] and <DrvP> bits

[11:6] */

board/LaCie/edminiv2/lowlevel_init.S new file +16 -0

+     orr     r6, r6, r1
+     str     r6, [r3, #0x4C0]
+
+        /* DDR SDRAM Data Pads Calibration
              */
+     ldr     r6, [r3, #0x4C4]
+
+        /* Set Bit [31] to make the register writable
           */
+     orr     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     str     r6, [r3, #0x4C4]
+
+     bic     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     bic     r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
+     bic     r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
+     bic     r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
+
+        /* Get the final N locked value of driving strength

[22:17] */

board/LaCie/edminiv2/lowlevel_init.S new file +6 -0

+        mov   r1, r6
+        mov   r1, r1, LSL #9
+        mov   r1, r1, LSR #26
+        orr   r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN>  */
+
+        /* Write to both <DrvN> bits [5:0] and <DrvP> bits

[11:6] */

board/LaCie/edminiv2/lowlevel_init.S new file +5 -0

+     orr     r6, r6, r1
+
+     str     r6, [r3, #0x4C4]
+
+        /* Implement Guideline (GL# MEM-3) Drive Strength

Value */

board/LaCie/edminiv2/lowlevel_init.S new file +5 -0

+        /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0
           */
+
+        ldr     r1, =DDR1_PAD_STRENGTH_DEFAULT
+
+     /* Enable writes to DDR SDRAM Addr/Ctrl Pads

Calibration register */

board/LaCie/edminiv2/lowlevel_init.S new file +22 -0

+     ldr     r6, [r3, #0x4C0]
+     orr     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     str     r6, [r3, #0x4C0]
+
+     /* Correct strength and disable writes again */
+     bic     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     bic     r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
+     orr     r6, r6, r1
+     str     r6, [r3, #0x4C0]
+
+     /* Enable writes to DDR SDRAM Data Pads Calibration register */
+     ldr     r6, [r3, #0x4C4]
+     orr     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     str     r6, [r3, #0x4C4]
+
+     /* Correct strength and disable writes again */
+     bic     r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
+     bic     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     orr     r6, r6, r1
+     str     r6, [r3, #0x4C4]
+
+        /* Implement Guideline (GL# MEM-4) DQS Reference

Delay Tuning */

board/LaCie/edminiv2/lowlevel_init.S new file +3 -0

+        /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0
           */
+
+        /* Get the "sample on reset" register for the DDR

frequancy */

board/LaCie/edminiv2/lowlevel_init.S new file +13 -0

+     ldr     r3, =0x10000
+        ldr  r6, [r3, #0x010]
+        ldr  r1, =MSAR_ARMDDRCLCK_MASK
+        and  r1, r6, r1
+
+        ldr  r6, =FTDLL_DDR1_166MHZ
+        cmp  r1, #MSAR_ARMDDRCLCK_333_167
+        beq  3f
+        cmp  r1, #MSAR_ARMDDRCLCK_500_167
+        beq  3f
+        cmp  r1, #MSAR_ARMDDRCLCK_667_167
+        beq  3f
+

board/LaCie/edminiv2/lowlevel_init.S new file +12 -0

+        ldr  r6, =0
+
+3:
+     /* Use R3 as the base for DRAM registers */
+     add     r3, r4, #0x01000
+
+     ldr     r2, [r3, #0x484]
+     orr     r2, r2, r6
+     str     r2, [r3, #0x484]
+
+     /* Return to U-boot via saved link register */
+     mov pc, lr

include/configs/edminiv2.h new file +0 -0

new file mode 100644
index 0000000..53e0046

include/configs/edminiv2.h new file +8 -0

+/*
+ * FLASH configuration
+ */
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_LEGACY
+#define CONFIG_SYS_MAX_FLASH_BANKS   1  /* max num of flash

banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects
on one chip */
+#define CONFIG_SYS_FLASH_BASE 0xfff80000

I still do not understand who will fectch u-boot binary to TEXT_BASE? (reported earlier) Is this flash XIP? Does u-boot binary below 16k? What is the size of flash? Pls refer my comments for v3

-----Original Message-----
From: Albert ARIBAUD [mailto:albert.aribaud at free.fr]
Sent: Monday, January 11, 2010 5:42 PM
To: Prafulla Wadaskar
Cc: U-Boot at lists.denx.de
Subject: Re: [U-Boot] [PATCH V4 3/3] Add support for the LaCie ED Mini V2 board

Prafulla Wadaskar a ?crit :

Quoted 1 line

I still do not understand who will fectch u-boot binary to

TEXT_BASE? (reported earlier)

Quoted 1 line

Is this flash XIP? Does u-boot binary below 16k? What is

the size of flash?

Quoted 1 line

Pls refer my comments for v3

I thought I'd explained that already, haven't I? At power-up a ROM code
at FFFF0000 (64KB of ROM taking precedence over CS0, as seen from JTAG)
does a few checks then jumps to FFF90000, which is the NOR Flash. The U-boot image is mapped and flashed so that the entry point is at FFF90000. The entry point then does further inits (some under condition
that SKIP_CONFIG_LOWLEVEL_INIT is not defined), initializes RAM, relocates code to TEXT_BASE (if CONFIG_SKIP_RELOCATE_UBOOT is not defined) and then jumps to it.

Amicalement,

Signature · 1 line

Albert.

Quoted 17 lines

-----Original Message-----
From: Albert ARIBAUD [mailto:albert.aribaud at free.fr]
Sent: Monday, January 11, 2010 5:42 PM
To: Prafulla Wadaskar
Cc: U-Boot at lists.denx.de
Subject: Re: [U-Boot] [PATCH V4 3/3] Add support for the LaCie ED Mini V2 board

Prafulla Wadaskar a ?crit :

Quoted 1 line

I still do not understand who will fectch u-boot binary to

TEXT_BASE? (reported earlier)

Quoted 1 line

Is this flash XIP? Does u-boot binary below 16k? What is

the size of flash?

Quoted 1 line

Pls refer my comments for v3

Quoted 12 lines

I thought I'd explained that already, haven't I? At power-up a ROM code
at FFFF0000 (64KB of ROM taking precedence over CS0, as seen from JTAG)
does a few checks then jumps to FFF90000, which is the NOR Flash. The U-boot image is mapped and flashed so that the entry point is at FFF90000. The entry point then does further inits (some under condition
that SKIP_CONFIG_LOWLEVEL_INIT is not defined), initializes RAM, relocates code to TEXT_BASE (if CONFIG_SKIP_RELOCATE_UBOOT is not defined) and then jumps to it.

Okay.
I am referring to 5281 users manual section 17.2.1 and that does not have these details.

Or
is ROM sitting at 0xffff0000 already have a code that does above? Or
Are you pointing to Boot ROM Support that 5281 have?

Do you have any reference for all this explanation? Or can you point any reference for me to look for?

Regards..
Prafulla . .

Review

Quoted 3 lines

(quoted diff) +1 -0

 
+TEXT_BASE = 0x00600000

??? As reported earlier, is this okay for you? And do not want to lower it?

Quoted 12 lines

board/LaCie/edminiv2/edminiv2.c new file +10 -0

 
+     info->flash_id                  = 0x01000000;
+     info->portwidth = FLASH_CFI_8BIT;
+     info->chipwidth = FLASH_CFI_BY8;
+     info->buffer_size = 0;
+     info->erase_blk_tout = 1000;
+     info->write_tout = 10;
+     info->buffer_write_tout = 300;
+     info->vendor = CFI_CMDSET_AMD_LEGACY;
+     info->cmd_reset = 0xF0;
+     info->interface = FLASH_CFI_X8;

board/LaCie/edminiv2/edminiv2.c line 73

Quoted 10 lines

board/LaCie/edminiv2/edminiv2.c new file +10 -0

+     info->legacy_unlock = 0;
+     info->manufacturer_id = 0x22;
+     info->device_id = 0xBA;
+     info->device_id2 = 0;
+     info->ext_addr = 0;
+     info->cfi_version = 0x3133;
+     info->cfi_offset = 0x0000;
+     info->addr_unlock1 = 0x00000aaa;
+     info->addr_unlock2 = 0x00000555;
+     info->name = "MX29LV400CB";

initialization with magic numbers should be provided with some comments for better understanding.

Quoted 1 line

+ info->device_id = 0xBA; /* device ID of the MX29LV400CB is 0xBA */

Quoted 5 lines

+++ b/board/LaCie/edminiv2/edminiv2.h

board/LaCie/edminiv2/edminiv2.h new file +3 -0

+#define EDMINIV2_MPP0_7              0x00000003
+#define EDMINIV2_MPP8_15     0x55550000
+#define EDMINIV2_MPP16_23    0x00000000

board/LaCie/edminiv2/lowlevel_init.S line 82

Quoted 5 lines

+++ b/board/LaCie/edminiv2/lowlevel_init.S

board/LaCie/edminiv2/lowlevel_init.S new file +3 -0

+#define EDMINIV2_MPP0_7                      0x00000003
+#define EDMINIV2_MPP8_15             0x55550000
+#define EDMINIV2_MPP16_19            0x00005555

Code repeated, this is already defined in edminiv2.h (reported earlier for V3)

Please defined all GPIO stuff at one place

Quoted 237 lines

board/LaCie/edminiv2/lowlevel_init.S new file +91 -0

+
+/*
+ * Low-level init happens right after start.S has switched to SVC32,
+ * flushed and disabled caches and disabled MMU. We're still running
+ * from the boot chip select, so the first thing we should do is set
+ * up RAM for us to relocate into.
+ */
+
+.globl lowlevel_init
+
+lowlevel_init:
+
+     /* Use 'r4 as the base for internal register accesses */
+     ldr     r4, =EDMINIV2_INTERNAL_BASE
+
+     /* move internal registers from the default 0xD0000000
+      * to their intended location of 0xf1000000 */
+     ldr     r3, =0xD0000000
+     add     r3, r3, #0x20000
+        str  r4, [r3, #0x80]
+
+     /* Use R3 as the base for Device Bus registers */
+     add     r3, r4, #0x10000
+
+     /* init MPPs */
+     ldr     r6, =EDMINIV2_MPP0_7
+     str     r6, [r3, #0x000]
+     ldr     r6, =EDMINIV2_MPP8_15
+     str     r6, [r3, #0x004]
+     ldr     r6, =EDMINIV2_MPP16_23
+     str     r6, [r3, #0x050]
+
+     /* init GPIOs */
+     ldr     r6, =EDMINIV2_GPIO_OUT_ENABLE
+     str     r6, [r3, #0x104]
+
+     /* Use R3 as the base for DRAM registers */
+     add     r3, r4, #0x01000
+
+     /*DDR SDRAM Initialization Control */
+     ldr     r6, =0x00000001
+     str     r6, [r3, #0x480]
+
+     /* Use R3 as the base for PCI registers */
+     add     r3, r4, #0x31000
+
+     /* Disable arbiter */
+     ldr     r6, =0x00000030
+     str     r6, [r3, #0xd00]
+
+     /* Use R3 as the base for DRAM registers */
+     add     r3, r4, #0x01000
+
+     /* set all dram windows to 0 */
+     mov     r6, #0
+     str     r6, [r3, #0x504]
+     str     r6, [r3, #0x50C]
+     str     r6, [r3, #0x514]
+     str     r6, [r3, #0x51C]
+
+     /* 1) Configure SDRAM  */
+     ldr     r6, =SDRAM_CONFIG
+     str     r6, [r3, #0x400]
+
+     /* 2) Set SDRAM Control reg */
+     ldr     r6, =SDRAM_CONTROL
+     str     r6, [r3, #0x404]
+
+        /* 3) Write SDRAM address control register */
+     ldr     r6, =SDRAM_ADDR_CTRL
+     str     r6, [r3, #0x410]
+
+        /* 4) Write SDRAM bank 0 size register */
+     ldr     r6, =SDRAM_BANK0_SIZE
+     str     r6, [r3, #0x504]
+     /* keep other banks disabled */
+
+        /* 5) Write SDRAM open pages control register */
+     ldr     r6, =SDRAM_OPEN_PAGE_EN
+     str     r6, [r3, #0x414]
+
+        /* 6) Write SDRAM timing Low register */
+     ldr     r6, =SDRAM_TIME_CTRL_LOW
+     str     r6, [r3, #0x408]
+
+        /* 7) Write SDRAM timing High register */
+     ldr     r6, =SDRAM_TIME_CTRL_HI
+     str     r6, [r3, #0x40C]
+
+        /* 8) Write SDRAM mode register */
+        /* The CPU must not attempt to change the SDRAM Mode

register setting */
+ /* prior to DRAM controller completion of the DRAM
initialization */
+ /* sequence. To guarantee this restriction, it is
recommended that */
+ /* the CPU sets the SDRAM Operation register to NOP
command, performs */
+ /* read polling until the register is back in Normal
operation value, */
+ /* and then sets SDRAM Mode register to its new
value. */

board/LaCie/edminiv2/lowlevel_init.S new file +12 -0

+
+     /* 8.1 write 'nop' to SDRAM operation */
+        ldr  r6, =SDRAM_OP_NOP
+     str     r6, [r3, #0x418]
+
+        /* 8.2 poll SDRAM operation until back in 'normal' mode.  */
+1:
+     ldr     r6, [r3, #0x418]
+     cmp     r6, #0
+     bne     1b
+
+        /* 8.3 Now its safe to write new value to SDRAM Mode

register */

board/LaCie/edminiv2/lowlevel_init.S new file +26 -0

+     ldr     r6, =SDRAM_MODE
+     str     r6, [r3, #0x41C]
+
+        /* 8.4 Set new mode */
+        ldr  r6, =SDRAM_OP_SETMODE
+     str     r6, [r3, #0x418]
+
+        /* 8.5 poll SDRAM operation until back in 'normal' mode.  */
+2:
+     ldr     r6, [r3, #0x418]
+     cmp     r6, #0
+     bne     2b
+
+        /* DDR SDRAM Address/Control Pads Calibration */
+     ldr     r6, [r3, #0x4C0]
+
+        /* Set Bit [31] to make the register writable
           */
+     orr     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     str     r6, [r3, #0x4C0]
+
+     bic     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     bic     r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
+     bic     r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
+     bic     r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
+
+        /* Get the final N locked value of driving strength

[22:17] */

board/LaCie/edminiv2/lowlevel_init.S new file +3 -0

+        mov   r1, r6
+        mov   r1, r1, LSL #9
+        mov   r1, r1, LSR #26    /* r1[5:0]<DrvN>  =

r3[22:17]<LockN> */
+ orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> =
r1[5:0]<DrvN> */

(quoted diff) +2 -0

+
+        /* Write to both <DrvN> bits [5:0] and <DrvP> bits

[11:6] */

board/LaCie/edminiv2/lowlevel_init.S new file +16 -0

+     orr     r6, r6, r1
+     str     r6, [r3, #0x4C0]
+
+        /* DDR SDRAM Data Pads Calibration
              */
+     ldr     r6, [r3, #0x4C4]
+
+        /* Set Bit [31] to make the register writable
           */
+     orr     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     str     r6, [r3, #0x4C4]
+
+     bic     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     bic     r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
+     bic     r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
+     bic     r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
+
+        /* Get the final N locked value of driving strength

[22:17] */

board/LaCie/edminiv2/lowlevel_init.S new file +6 -0

+        mov   r1, r6
+        mov   r1, r1, LSL #9
+        mov   r1, r1, LSR #26
+        orr   r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN>  */
+
+        /* Write to both <DrvN> bits [5:0] and <DrvP> bits

[11:6] */

board/LaCie/edminiv2/lowlevel_init.S new file +5 -0

+     orr     r6, r6, r1
+
+     str     r6, [r3, #0x4C4]
+
+        /* Implement Guideline (GL# MEM-3) Drive Strength

Value */

board/LaCie/edminiv2/lowlevel_init.S new file +5 -0

+        /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0
           */
+
+        ldr     r1, =DDR1_PAD_STRENGTH_DEFAULT
+
+     /* Enable writes to DDR SDRAM Addr/Ctrl Pads

Calibration register */

board/LaCie/edminiv2/lowlevel_init.S new file +22 -0

+     ldr     r6, [r3, #0x4C0]
+     orr     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     str     r6, [r3, #0x4C0]
+
+     /* Correct strength and disable writes again */
+     bic     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     bic     r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
+     orr     r6, r6, r1
+     str     r6, [r3, #0x4C0]
+
+     /* Enable writes to DDR SDRAM Data Pads Calibration register */
+     ldr     r6, [r3, #0x4C4]
+     orr     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     str     r6, [r3, #0x4C4]
+
+     /* Correct strength and disable writes again */
+     bic     r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
+     bic     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     orr     r6, r6, r1
+     str     r6, [r3, #0x4C4]
+
+        /* Implement Guideline (GL# MEM-4) DQS Reference

Delay Tuning */

(quoted diff) +3 -0

+        /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0
           */
+
+        /* Get the "sample on reset" register for the DDR

frequancy */

board/LaCie/edminiv2/lowlevel_init.S new file +18 -0

+     ldr     r3, =0x10000
+        ldr  r6, [r3, #0x010]
+        ldr  r1, =MSAR_ARMDDRCLCK_MASK
+        and  r1, r6, r1
+
+        ldr  r6, =FTDLL_DDR1_166MHZ
+        cmp  r1, #MSAR_ARMDDRCLCK_333_167
+        beq  3f
+        cmp  r1, #MSAR_ARMDDRCLCK_500_167
+        beq  3f
+        cmp  r1, #MSAR_ARMDDRCLCK_667_167
+        beq  3f
+
+        ldr  r6, =FTDLL_DDR1_200MHZ
+        cmp  r1, #MSAR_ARMDDRCLCK_400_200_1
+        beq  3f
+        cmp  r1, #MSAR_ARMDDRCLCK_400_200
+        beq  3f

board/LaCie/edminiv2/lowlevel_init.S line 312

Quoted 5 lines

board/LaCie/edminiv2/lowlevel_init.S new file +5 -0

+        cmp  r1, #MSAR_ARMDDRCLCK_600_200
+        beq  3f
+        cmp  r1, #MSAR_ARMDDRCLCK_800_200
+        beq  3f
+

As reported earlier comment for v3,
this should only have simple DRAM initialization, which is only dependency to copy and start binary.

MPP and GPIO inits should be moved to edminv2.c.

Common to SoC stuff to be moved to cpu.c/h

Regards..
Prafulla . .

-----Original Message-----
From: Albert ARIBAUD [mailto:albert.aribaud at free.fr]
Sent: Wednesday, January 13, 2010 6:08 PM
To: Prafulla Wadaskar
Cc: U-Boot at lists.denx.de
Subject: Re: [U-Boot] [PATCH V4 3/3] Add support for the LaCie ED Mini V2 board

Quoted 21 lines

Quoted 10 lines

board/LaCie/edminiv2/edminiv2.c new file +10 -0

+     info->flash_id                  = 0x01000000;
+     info->portwidth = FLASH_CFI_8BIT;
+     info->chipwidth = FLASH_CFI_BY8;
+     info->buffer_size = 0;
+     info->erase_blk_tout = 1000;
+     info->write_tout = 10;
+     info->buffer_write_tout = 300;
+     info->vendor = CFI_CMDSET_AMD_LEGACY;
+     info->cmd_reset = 0xF0;
+     info->interface = FLASH_CFI_X8;

board/LaCie/edminiv2/edminiv2.c line 73

Quoted 10 lines

board/LaCie/edminiv2/edminiv2.c new file +10 -0

+     info->legacy_unlock = 0;
+     info->manufacturer_id = 0x22;
+     info->device_id = 0xBA;
+     info->device_id2 = 0;
+     info->ext_addr = 0;
+     info->cfi_version = 0x3133;
+     info->cfi_offset = 0x0000;
+     info->addr_unlock1 = 0x00000aaa;
+     info->addr_unlock2 = 0x00000555;
+     info->name = "MX29LV400CB";

Quoted 1 line

initialization with magic numbers should be provided with

some comments for better understanding.

I can add some comments, although here most of the comments would simply
paraphrase the code one way or the other, e.g.

Quoted 1 line

Quoted 1 line

+ info->device_id = 0xBA; /* device ID of the

MX29LV400CB is 0xBA */

Quoted 91 lines

Quoted 91 lines

board/LaCie/edminiv2/lowlevel_init.S new file +82 -0

+
+lowlevel_init:
+
+     /* Use 'r4 as the base for internal register accesses */
+     ldr     r4, =EDMINIV2_INTERNAL_BASE
+
+     /* move internal registers from the default 0xD0000000
+      * to their intended location of 0xf1000000 */
+     ldr     r3, =0xD0000000
+     add     r3, r3, #0x20000
+        str  r4, [r3, #0x80]
+
+     /* Use R3 as the base for Device Bus registers */
+     add     r3, r4, #0x10000
+
+     /* init MPPs */
+     ldr     r6, =EDMINIV2_MPP0_7
+     str     r6, [r3, #0x000]
+     ldr     r6, =EDMINIV2_MPP8_15
+     str     r6, [r3, #0x004]
+     ldr     r6, =EDMINIV2_MPP16_23
+     str     r6, [r3, #0x050]
+
+     /* init GPIOs */
+     ldr     r6, =EDMINIV2_GPIO_OUT_ENABLE
+     str     r6, [r3, #0x104]
+
+     /* Use R3 as the base for DRAM registers */
+     add     r3, r4, #0x01000
+
+     /*DDR SDRAM Initialization Control */
+     ldr     r6, =0x00000001
+     str     r6, [r3, #0x480]
+
+     /* Use R3 as the base for PCI registers */
+     add     r3, r4, #0x31000
+
+     /* Disable arbiter */
+     ldr     r6, =0x00000030
+     str     r6, [r3, #0xd00]
+
+     /* Use R3 as the base for DRAM registers */
+     add     r3, r4, #0x01000
+
+     /* set all dram windows to 0 */
+     mov     r6, #0
+     str     r6, [r3, #0x504]
+     str     r6, [r3, #0x50C]
+     str     r6, [r3, #0x514]
+     str     r6, [r3, #0x51C]
+
+     /* 1) Configure SDRAM  */
+     ldr     r6, =SDRAM_CONFIG
+     str     r6, [r3, #0x400]
+
+     /* 2) Set SDRAM Control reg */
+     ldr     r6, =SDRAM_CONTROL
+     str     r6, [r3, #0x404]
+
+        /* 3) Write SDRAM address control register */
+     ldr     r6, =SDRAM_ADDR_CTRL
+     str     r6, [r3, #0x410]
+
+        /* 4) Write SDRAM bank 0 size register */
+     ldr     r6, =SDRAM_BANK0_SIZE
+     str     r6, [r3, #0x504]
+     /* keep other banks disabled */
+
+        /* 5) Write SDRAM open pages control register */
+     ldr     r6, =SDRAM_OPEN_PAGE_EN
+     str     r6, [r3, #0x414]
+
+        /* 6) Write SDRAM timing Low register */
+     ldr     r6, =SDRAM_TIME_CTRL_LOW
+     str     r6, [r3, #0x408]
+
+        /* 7) Write SDRAM timing High register */
+     ldr     r6, =SDRAM_TIME_CTRL_HI
+     str     r6, [r3, #0x40C]
+
+        /* 8) Write SDRAM mode register */
+        /* The CPU must not attempt to change the SDRAM Mode

register setting */
+ /* prior to DRAM controller completion of the DRAM
initialization */
+ /* sequence. To guarantee this restriction, it is
recommended that */
+ /* the CPU sets the SDRAM Operation register to NOP
command, performs */
+ /* read polling until the register is back in Normal
operation value, */

Quoted 8 lines

board/LaCie/edminiv2/lowlevel_init.S

Quoted 8 lines

+ /* and then sets SDRAM Mode register to its new
value. */

board/LaCie/edminiv2/lowlevel_init.S new file +6 -0

+
+     /* 8.1 write 'nop' to SDRAM operation */
+        ldr  r6, =SDRAM_OP_NOP
+     str     r6, [r3, #0x418]
+
+        /* 8.2 poll SDRAM operation until back in 

'normal' mode. */

Quoted 7 lines

Quoted 7 lines

+1:

board/LaCie/edminiv2/lowlevel_init.S new file +5 -0

+     ldr     r6, [r3, #0x418]
+     cmp     r6, #0
+     bne     1b
+
+        /* 8.3 Now its safe to write new value to SDRAM Mode

register */

Quoted 8 lines

board/LaCie/edminiv2/lowlevel_init.S

Quoted 8 lines

board/LaCie/edminiv2/lowlevel_init.S new file +8 -0

+     ldr     r6, =SDRAM_MODE
+     str     r6, [r3, #0x41C]
+
+        /* 8.4 Set new mode */
+        ldr  r6, =SDRAM_OP_SETMODE
+     str     r6, [r3, #0x418]
+
+        /* 8.5 poll SDRAM operation until back in 

'normal' mode. */

Quoted 71 lines

Quoted 71 lines

+2:

board/LaCie/edminiv2/lowlevel_init.S new file +17 -0

+     ldr     r6, [r3, #0x418]
+     cmp     r6, #0
+     bne     2b
+
+        /* DDR SDRAM Address/Control Pads Calibration */
+     ldr     r6, [r3, #0x4C0]
+
+        /* Set Bit [31] to make the register writable
           */
+     orr     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     str     r6, [r3, #0x4C0]
+
+     bic     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     bic     r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
+     bic     r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
+     bic     r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
+
+        /* Get the final N locked value of driving strength

[22:17] */

board/LaCie/edminiv2/lowlevel_init.S new file +3 -0

+        mov   r1, r6
+        mov   r1, r1, LSL #9
+        mov   r1, r1, LSR #26    /* r1[5:0]<DrvN>  =

r3[22:17]<LockN> */
+ orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> =
r1[5:0]<DrvN> */

(quoted diff) +2 -0

+
+        /* Write to both <DrvN> bits [5:0] and <DrvP> bits

[11:6] */

board/LaCie/edminiv2/lowlevel_init.S new file +16 -0

+     orr     r6, r6, r1
+     str     r6, [r3, #0x4C0]
+
+        /* DDR SDRAM Data Pads Calibration
              */
+     ldr     r6, [r3, #0x4C4]
+
+        /* Set Bit [31] to make the register writable
           */
+     orr     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     str     r6, [r3, #0x4C4]
+
+     bic     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     bic     r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
+     bic     r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
+     bic     r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
+
+        /* Get the final N locked value of driving strength

[22:17] */

board/LaCie/edminiv2/lowlevel_init.S new file +6 -0

+        mov   r1, r6
+        mov   r1, r1, LSL #9
+        mov   r1, r1, LSR #26
+        orr   r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN>  */
+
+        /* Write to both <DrvN> bits [5:0] and <DrvP> bits

[11:6] */

board/LaCie/edminiv2/lowlevel_init.S new file +5 -0

+     orr     r6, r6, r1
+
+     str     r6, [r3, #0x4C4]
+
+        /* Implement Guideline (GL# MEM-3) Drive Strength

Value */

board/LaCie/edminiv2/lowlevel_init.S new file +5 -0

+        /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0
           */
+
+        ldr     r1, =DDR1_PAD_STRENGTH_DEFAULT
+
+     /* Enable writes to DDR SDRAM Addr/Ctrl Pads

Calibration register */

board/LaCie/edminiv2/lowlevel_init.S new file +3 -0

+     ldr     r6, [r3, #0x4C0]
+     orr     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     str     r6, [r3, #0x4C0]

Quoted 8 lines

board/LaCie/edminiv2/lowlevel_init.S

Quoted 8 lines

board/LaCie/edminiv2/lowlevel_init.S new file +8 -0

+
+     /* Correct strength and disable writes again */
+     bic     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     bic     r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
+     orr     r6, r6, r1
+     str     r6, [r3, #0x4C0]
+
+     /* Enable writes to DDR SDRAM Data Pads Calibration 

register */

Quoted 35 lines

Quoted 35 lines

board/LaCie/edminiv2/lowlevel_init.S new file +11 -0

+     ldr     r6, [r3, #0x4C4]
+     orr     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     str     r6, [r3, #0x4C4]
+
+     /* Correct strength and disable writes again */
+     bic     r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
+     bic     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     orr     r6, r6, r1
+     str     r6, [r3, #0x4C4]
+
+        /* Implement Guideline (GL# MEM-4) DQS Reference

Delay Tuning */

(quoted diff) +3 -0

+        /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0
           */
+
+        /* Get the "sample on reset" register for the DDR

frequancy */

board/LaCie/edminiv2/lowlevel_init.S new file +18 -0

+     ldr     r3, =0x10000
+        ldr  r6, [r3, #0x010]
+        ldr  r1, =MSAR_ARMDDRCLCK_MASK
+        and  r1, r6, r1
+
+        ldr  r6, =FTDLL_DDR1_166MHZ
+        cmp  r1, #MSAR_ARMDDRCLCK_333_167
+        beq  3f
+        cmp  r1, #MSAR_ARMDDRCLCK_500_167
+        beq  3f
+        cmp  r1, #MSAR_ARMDDRCLCK_667_167
+        beq  3f
+
+        ldr  r6, =FTDLL_DDR1_200MHZ
+        cmp  r1, #MSAR_ARMDDRCLCK_400_200_1
+        beq  3f
+        cmp  r1, #MSAR_ARMDDRCLCK_400_200
+        beq  3f

Quoted 8 lines

board/LaCie/edminiv2/lowlevel_init.S line 312

Quoted 5 lines

board/LaCie/edminiv2/lowlevel_init.S new file +5 -0

+        cmp  r1, #MSAR_ARMDDRCLCK_600_200
+        beq  3f
+        cmp  r1, #MSAR_ARMDDRCLCK_800_200
+        beq  3f
+

As reported earlier comment for v3,
this should only have simple DRAM initialization, which is

only dependency to copy and start binary.

Hmm... Those are fixes to allow/ensure DDRAM access, so I'd say this is
a dependency to copy and start the binary.

Quoted 2 lines

MPP and GPIO inits should be moved to edminv2.c.

Why move them? They must be board-specific, and they are indeed in board-specific code.

Quoted 1 line

Common to SoC stuff to be moved to cpu.c/h

This I can agree upon, however I don't see much that is common across SoCs here. Does that warrant creating a function at SoC level which will
do practically nothing?

Quoted 6 lines

I can add some comments, although here most of the comments would simply
paraphrase the code one way or the other, e.g.

Quoted 1 line

Quoted 1 line

+ info->device_id = 0xBA; /* device ID of the

MX29LV400CB is 0xBA */

This level documentation is good rather than nothing :-)

...snip...

Quoted 238 lines

Quoted 91 lines

Quoted 91 lines

board/LaCie/edminiv2/lowlevel_init.S new file +82 -0

+
+lowlevel_init:
+
+     /* Use 'r4 as the base for internal register accesses */
+     ldr     r4, =EDMINIV2_INTERNAL_BASE
+
+     /* move internal registers from the default 0xD0000000
+      * to their intended location of 0xf1000000 */
+     ldr     r3, =0xD0000000
+     add     r3, r3, #0x20000
+        str  r4, [r3, #0x80]
+
+     /* Use R3 as the base for Device Bus registers */
+     add     r3, r4, #0x10000
+
+     /* init MPPs */
+     ldr     r6, =EDMINIV2_MPP0_7
+     str     r6, [r3, #0x000]
+     ldr     r6, =EDMINIV2_MPP8_15
+     str     r6, [r3, #0x004]
+     ldr     r6, =EDMINIV2_MPP16_23
+     str     r6, [r3, #0x050]
+
+     /* init GPIOs */
+     ldr     r6, =EDMINIV2_GPIO_OUT_ENABLE
+     str     r6, [r3, #0x104]
+
+     /* Use R3 as the base for DRAM registers */
+     add     r3, r4, #0x01000
+
+     /*DDR SDRAM Initialization Control */
+     ldr     r6, =0x00000001
+     str     r6, [r3, #0x480]
+
+     /* Use R3 as the base for PCI registers */
+     add     r3, r4, #0x31000
+
+     /* Disable arbiter */
+     ldr     r6, =0x00000030
+     str     r6, [r3, #0xd00]
+
+     /* Use R3 as the base for DRAM registers */
+     add     r3, r4, #0x01000
+
+     /* set all dram windows to 0 */
+     mov     r6, #0
+     str     r6, [r3, #0x504]
+     str     r6, [r3, #0x50C]
+     str     r6, [r3, #0x514]
+     str     r6, [r3, #0x51C]
+
+     /* 1) Configure SDRAM  */
+     ldr     r6, =SDRAM_CONFIG
+     str     r6, [r3, #0x400]
+
+     /* 2) Set SDRAM Control reg */
+     ldr     r6, =SDRAM_CONTROL
+     str     r6, [r3, #0x404]
+
+        /* 3) Write SDRAM address control register */
+     ldr     r6, =SDRAM_ADDR_CTRL
+     str     r6, [r3, #0x410]
+
+        /* 4) Write SDRAM bank 0 size register */
+     ldr     r6, =SDRAM_BANK0_SIZE
+     str     r6, [r3, #0x504]
+     /* keep other banks disabled */
+
+        /* 5) Write SDRAM open pages control register */
+     ldr     r6, =SDRAM_OPEN_PAGE_EN
+     str     r6, [r3, #0x414]
+
+        /* 6) Write SDRAM timing Low register */
+     ldr     r6, =SDRAM_TIME_CTRL_LOW
+     str     r6, [r3, #0x408]
+
+        /* 7) Write SDRAM timing High register */
+     ldr     r6, =SDRAM_TIME_CTRL_HI
+     str     r6, [r3, #0x40C]
+
+        /* 8) Write SDRAM mode register */
+        /* The CPU must not attempt to change the SDRAM Mode

register setting */
+ /* prior to DRAM controller completion of the DRAM
initialization */
+ /* sequence. To guarantee this restriction, it is
recommended that */
+ /* the CPU sets the SDRAM Operation register to NOP
command, performs */
+ /* read polling until the register is back in Normal
operation value, */

Quoted 8 lines

board/LaCie/edminiv2/lowlevel_init.S

Quoted 8 lines

+ /* and then sets SDRAM Mode register to its new
value. */

board/LaCie/edminiv2/lowlevel_init.S new file +6 -0

+
+     /* 8.1 write 'nop' to SDRAM operation */
+        ldr  r6, =SDRAM_OP_NOP
+     str     r6, [r3, #0x418]
+
+        /* 8.2 poll SDRAM operation until back in 

'normal' mode. */

Quoted 7 lines

Quoted 7 lines

+1:

board/LaCie/edminiv2/lowlevel_init.S new file +5 -0

+     ldr     r6, [r3, #0x418]
+     cmp     r6, #0
+     bne     1b
+
+        /* 8.3 Now its safe to write new value to SDRAM Mode

register */

Quoted 8 lines

board/LaCie/edminiv2/lowlevel_init.S

Quoted 8 lines

board/LaCie/edminiv2/lowlevel_init.S new file +8 -0

+     ldr     r6, =SDRAM_MODE
+     str     r6, [r3, #0x41C]
+
+        /* 8.4 Set new mode */
+        ldr  r6, =SDRAM_OP_SETMODE
+     str     r6, [r3, #0x418]
+
+        /* 8.5 poll SDRAM operation until back in 

'normal' mode. */

Quoted 71 lines

Quoted 71 lines

+2:

board/LaCie/edminiv2/lowlevel_init.S new file +17 -0

+     ldr     r6, [r3, #0x418]
+     cmp     r6, #0
+     bne     2b
+
+        /* DDR SDRAM Address/Control Pads Calibration */
+     ldr     r6, [r3, #0x4C0]
+
+        /* Set Bit [31] to make the register writable
           */
+     orr     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     str     r6, [r3, #0x4C0]
+
+     bic     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     bic     r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
+     bic     r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
+     bic     r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
+
+        /* Get the final N locked value of driving strength

[22:17] */

board/LaCie/edminiv2/lowlevel_init.S new file +3 -0

+        mov   r1, r6
+        mov   r1, r1, LSL #9
+        mov   r1, r1, LSR #26    /* r1[5:0]<DrvN>  =

r3[22:17]<LockN> */
+ orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> =
r1[5:0]<DrvN> */

(quoted diff) +2 -0

+
+        /* Write to both <DrvN> bits [5:0] and <DrvP> bits

[11:6] */

board/LaCie/edminiv2/lowlevel_init.S new file +16 -0

+     orr     r6, r6, r1
+     str     r6, [r3, #0x4C0]
+
+        /* DDR SDRAM Data Pads Calibration
              */
+     ldr     r6, [r3, #0x4C4]
+
+        /* Set Bit [31] to make the register writable
           */
+     orr     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     str     r6, [r3, #0x4C4]
+
+     bic     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     bic     r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
+     bic     r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
+     bic     r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
+
+        /* Get the final N locked value of driving strength

[22:17] */

board/LaCie/edminiv2/lowlevel_init.S new file +6 -0

+        mov   r1, r6
+        mov   r1, r1, LSL #9
+        mov   r1, r1, LSR #26
+        orr   r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN>  */
+
+        /* Write to both <DrvN> bits [5:0] and <DrvP> bits

[11:6] */

board/LaCie/edminiv2/lowlevel_init.S new file +5 -0

+     orr     r6, r6, r1
+
+     str     r6, [r3, #0x4C4]
+
+        /* Implement Guideline (GL# MEM-3) Drive Strength

Value */

board/LaCie/edminiv2/lowlevel_init.S new file +5 -0

+        /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0
           */
+
+        ldr     r1, =DDR1_PAD_STRENGTH_DEFAULT
+
+     /* Enable writes to DDR SDRAM Addr/Ctrl Pads

Calibration register */

board/LaCie/edminiv2/lowlevel_init.S new file +3 -0

+     ldr     r6, [r3, #0x4C0]
+     orr     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     str     r6, [r3, #0x4C0]

Quoted 8 lines

board/LaCie/edminiv2/lowlevel_init.S

Quoted 8 lines

board/LaCie/edminiv2/lowlevel_init.S new file +8 -0

+
+     /* Correct strength and disable writes again */
+     bic     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     bic     r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
+     orr     r6, r6, r1
+     str     r6, [r3, #0x4C0]
+
+     /* Enable writes to DDR SDRAM Data Pads Calibration 

register */

Quoted 34 lines

Quoted 34 lines

board/LaCie/edminiv2/lowlevel_init.S new file +11 -0

+     ldr     r6, [r3, #0x4C4]
+     orr     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     str     r6, [r3, #0x4C4]
+
+     /* Correct strength and disable writes again */
+     bic     r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
+     bic     r6, r6, #SDRAM_PAD_CTRL_WR_EN
+     orr     r6, r6, r1
+     str     r6, [r3, #0x4C4]
+
+        /* Implement Guideline (GL# MEM-4) DQS Reference

Delay Tuning */

(quoted diff) +3 -0

+        /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0
           */
+
+        /* Get the "sample on reset" register for the DDR

frequancy */

board/LaCie/edminiv2/lowlevel_init.S new file +17 -0

+     ldr     r3, =0x10000
+        ldr  r6, [r3, #0x010]
+        ldr  r1, =MSAR_ARMDDRCLCK_MASK
+        and  r1, r6, r1
+
+        ldr  r6, =FTDLL_DDR1_166MHZ
+        cmp  r1, #MSAR_ARMDDRCLCK_333_167
+        beq  3f
+        cmp  r1, #MSAR_ARMDDRCLCK_500_167
+        beq  3f
+        cmp  r1, #MSAR_ARMDDRCLCK_667_167
+        beq  3f
+
+        ldr  r6, =FTDLL_DDR1_200MHZ
+        cmp  r1, #MSAR_ARMDDRCLCK_400_200_1
+        beq  3f
+        cmp  r1, #MSAR_ARMDDRCLCK_400_200

Quoted 8 lines

board/LaCie/edminiv2/lowlevel_init.S line 312

Quoted 6 lines

board/LaCie/edminiv2/lowlevel_init.S new file +6 -0

+        beq  3f
+        cmp  r1, #MSAR_ARMDDRCLCK_600_200
+        beq  3f
+        cmp  r1, #MSAR_ARMDDRCLCK_800_200
+        beq  3f
+

As reported earlier comment for v3,
this should only have simple DRAM initialization, which is

Quoted 5 lines

only dependency to copy and start binary.

Hmm... Those are fixes to allow/ensure DDRAM access, so I'd say this is
a dependency to copy and start the binary.

The code here looks very long
It's purpose is to initialize certain CPU registers.
For specific board there is no need of any conditional initializations.

Similar to board/Marvell/Sheevaplug/kwbimage.cfg, can you abstract a data for CPU registers and values to be initialized through some data structures and a small function to read and copy them to respective registers?

That will give better readability and easy updates for future users.

lets keep least ASM code.

We cannot avoid lowlevel_init otherwise I could have preferred to omit it.

Quoted 5 lines

Quoted 1 line

Common to SoC stuff to be moved to cpu.c/h

This I can agree upon, however I don't see much that is common across SoCs here. Does that warrant creating a function at SoC level which will
do practically nothing?

For ex. Mpp_init, GPIO_init and other init can go in cpu.c,
You can declare respective init macros in edminv2.h and function calls in edminv2.c Thus those will be re-usable for other orion5X boards.

Also you can do basic CPU registers initialization as suggested above and
Further tuning like reading "sample on reset" and updating some specific registers can be pushed in cpu.c Because this will be a standard need to all board using this SoC

What do you think?

Regards.
Prafulla . .

This patch adds support for the LaCie ED Mini V2 product which is based on the Marvell Orion5x SoC. Current support is limited to console and Flash. Flash support uses CONFIG_FLASH_CFI_LEGACY as the Macronix MX29LV400 used on ED Mini V2 is not CFI compliant (mixes 16 and 8 bit behaviors).

Signed-off-by Albert Aribaud <[email protected]>

---
 MAINTAINERS                          |    4 +
 MAKEALL                              |    1 +
 Makefile                             |    3 +
 board/LaCie/edminiv2/Makefile        |   58 ++++++
 board/LaCie/edminiv2/config.mk       |   27 +++
 board/LaCie/edminiv2/edminiv2.c      |   88 +++++++++
 board/LaCie/edminiv2/edminiv2.h      |   59 ++++++
 board/LaCie/edminiv2/lowlevel_init.S |  324 ++++++++++++++++++++++++++++++++++

 include/configs/edminiv2.h           |  147 +++++++++++++++
 9 files changed, 711 insertions(+), 0 deletions(-)
 create mode 100644 board/LaCie/edminiv2/Makefile
 create mode 100644 board/LaCie/edminiv2/config.mk
 create mode 100644 board/LaCie/edminiv2/edminiv2.c
 create mode 100644 board/LaCie/edminiv2/edminiv2.h
 create mode 100644 board/LaCie/edminiv2/lowlevel_init.S
 create mode 100644 include/configs/edminiv2.h

-----Original Message-----
From: u-boot-bounces at lists.denx.de [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Albert Aribaud
Sent: Sunday, January 10, 2010 9:34 PM
To: U-Boot at lists.denx.de
Subject: [U-Boot] [PATCH V4 1/3] Initial support for Marvell Orion5x SoC

This patch adds support for the Marvell Orion5x SoC. It has no use alone, and must be followed by a patch to add Orion5x support for serial, then support for the ED Mini V2, an Orion5x-based product from LaCie.

Signed-off-by Albert Aribaud <[email protected]>

---
Patchset history

V1: Initial monolithic patch.
V2: split in three patches : orion, serial, edmini;
checkpatch'ed, with only 6 errors, in patch 1/3, all 6 errors being false positives.
V3: useless GPIO and MPP programming support removed;
low level init added/CONFIG_SKIP_LOW_LEVEL_INIT removed.
V4: all files licensed GPLv2-only removed;
RAM bank size detection now uses getm_ram_size().

 cpu/arm926ejs/orion5x/Makefile           |   51 ++++++
 cpu/arm926ejs/orion5x/cpu.c              |  258 
++++++++++++++++++++++++++++++
 cpu/arm926ejs/orion5x/dram.c             |   62 +++++++
 cpu/arm926ejs/orion5x/timer.c            |  181 +++++++++++++++++++++
 include/asm-arm/arch-orion5x/cpu.h       |  187 +++++++++++++++++++++
 include/asm-arm/arch-orion5x/mv88f5182.h |   40 +++++
 include/asm-arm/arch-orion5x/orion5x.h   |   67 ++++++++
 7 files changed, 846 insertions(+), 0 deletions(-)
 create mode 100644 cpu/arm926ejs/orion5x/Makefile
 create mode 100644 cpu/arm926ejs/orion5x/cpu.c
 create mode 100644 cpu/arm926ejs/orion5x/dram.c
 create mode 100644 cpu/arm926ejs/orion5x/timer.c
 create mode 100644 include/asm-arm/arch-orion5x/cpu.h
 create mode 100644 include/asm-arm/arch-orion5x/mv88f5182.h
 create mode 100644 include/asm-arm/arch-orion5x/orion5x.h

cpu/arm926ejs/orion5x/dram.c new file +34 -0

new file mode 100644
index 0000000..af4a788
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2009 Albert ARIBAUD <[email protected]>
+ *
+ * Based on original Kirkwood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/arch/orion5x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ORION5X_REG_CPUCS_WIN_BAR(x) 

(ORION5X_REGISTER(0x1500) + (x * 0x08))
+#define ORION5X_REG_CPUCS_WIN_SZ(x)
(ORION5X_REGISTER(0x1504) + (x * 0x08))

cpu/arm926ejs/orion5x/dram.c new file +14 -0

+/*
+ * orion5x_sdram_bar - reads SDRAM Base Address Register
+ */
+u32 orion5x_sdram_bar(enum memory_bank bank)
+{
+	u32 result = 0;
+	u32 enable = 0x01 & readl(ORION5X_REG_CPUCS_WIN_SZ(bank));
+
+	if ((!enable) || (bank > BANK3))
+		return 0;
+
+	result = readl(ORION5X_REG_CPUCS_WIN_BAR(bank));
+	return result;
+}

include/asm-arm/arch-orion5x/cpu.h new file +35 -0

new file mode 100644
index 0000000..0a33999
@@ -0,0 +1,187 @@
+/*
+ * Copyright (C) 2009 Albert ARIBAUD <[email protected]>
+ *
+ * Based on original Kirorion5x_ood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ORION5X_CPU_H
+#define _ORION5X_CPU_H
+
+#include <asm/system.h>
+
+#ifndef __ASSEMBLY__
+
+#define ORION5X_CPU_WIN_CTRL_DATA(size, target, attr, en) 

(en | (target << 4) \

include/asm-arm/arch-orion5x/cpu.h new file +1 -0

+			| (attr << 8) | 

(orion5x_winctrl_calcsize(size) << 16))

include/asm-arm/arch-orion5x/cpu.h new file +3 -0

+
+#define ORION5XGBE_PORT_SERIAL_CONTROL1_REG(_x)	\
+		((_x ? ORION5X_EGIGA0_BASE : 

ORION5X_EGIGA1_BASE) + 0x44c)

include/asm-arm/arch-orion5x/cpu.h new file +80 -0

+
+enum memory_bank {
+	BANK0,
+	BANK1,
+	BANK2,
+	BANK3
+};
+
+enum orion5x_cpu_winen {
+	ORION5X_WIN_DISABLE,
+	ORION5X_WIN_ENABLE
+};
+
+enum orion5x_cpu_target {
+	ORION5X_TARGET_DRAM = 0,
+	ORION5X_TARGET_DEVICE = 1,
+	ORION5X_TARGET_PCI = 3,
+	ORION5X_TARGET_PCIE = 4,
+	ORION5X_TARGET_SASRAM = 9
+};
+
+enum orion5x_cpu_attrib {
+	ORION5X_ATTR_DRAM_CS0 = 0x0e,
+	ORION5X_ATTR_DRAM_CS1 = 0x0d,
+	ORION5X_ATTR_DRAM_CS2 = 0x0b,
+	ORION5X_ATTR_DRAM_CS3 = 0x07,
+	ORION5X_ATTR_PCI_MEM = 0x59,
+	ORION5X_ATTR_PCI_IO = 0x51,
+	ORION5X_ATTR_PCIE_MEM = 0x59,
+	ORION5X_ATTR_PCIE_IO = 0x51,
+	ORION5X_ATTR_SASRAM = 0x00,
+	ORION5X_ATTR_DEV_CS0 = 0x1e,
+	ORION5X_ATTR_DEV_CS1 = 0x1d,
+	ORION5X_ATTR_DEV_CS2 = 0x1b,
+	ORION5X_ATTR_BOOTROM = 0x0f
+};
+
+/*
+ * Default Device Address MAP BAR values
+ */
+#define ORION5X_DEFADR_PCIE_MEM	0x90000000
+#define ORION5X_DEFADR_PCIE_MEM_REMAP_LO	0x90000000
+#define ORION5X_DEFADR_PCIE_MEM_REMAP_HI	0
+#define ORION5X_DEFSZ_PCIE_MEM	(128*1024*1024)
+
+#define ORION5X_DEFADR_PCIE_IO	0xf0000000
+#define ORION5X_DEFADR_PCIE_IO_REMAP_LO	0x90000000
+#define ORION5X_DEFADR_PCIE_IO_REMAP_HI	0
+#define ORION5X_DEFSZ_PCIE_IO	(64*1024)
+
+#define ORION5X_DEFADR_PCI_MEM	0x98000000
+#define ORION5X_DEFSZ_PCI_MEM	(128*1024*1024)
+
+#define ORION5X_DEFADR_PCI_IO	0xf0100000
+#define ORION5X_DEFSZ_PCI_IO	(64*1024)
+
+#define ORION5X_DEFADR_DEV_CS0	0xfa000000
+#define ORION5X_DEFSZ_DEV_CS0	(2*1024*1024)
+
+#define ORION5X_DEFADR_DEV_CS1	0xf8000000
+#define ORION5X_DEFSZ_DEV_CS1	(32*1024*1024)
+
+#define ORION5X_DEFADR_DEV_CS2	0xfa800000
+#define ORION5X_DEFSZ_DEV_CS2	(1*1024*1024)
+
+#define ORION5X_DEFADR_BOOTROM	0xFFF80000
+#define ORION5X_DEFSZ_BOOTROM	(512*1024)
+
+/*
+ * PCIE registers are used for SoC device ID and revision
+ */
+#define PCIE_DEV_ID_OFF         (ORION5X_REG_PCIE_BASE + 0x0000)
+#define PCIE_DEV_REV_OFF        (ORION5X_REG_PCIE_BASE + 0x0008)
+
+/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
+#define MV88F5181_DEV_ID        0x5181
+#define MV88F5181_REV_B1        3
+#define MV88F5181L_REV_A0       8
+#define MV88F5181L_REV_A1       9
+/* Orion-NAS (88F5182) */

Quoted 4 lines

+#define ORION5X_REG_CPUCS_WIN_BAR(x)
(ORION5X_REGISTER(0x1500) + (x * 0x08))
+#define ORION5X_REG_CPUCS_WIN_SZ(x)
(ORION5X_REGISTER(0x1504) + (x * 0x08))

As pointed by wolfgang earlier, you can use c-structures here too.

(quoted diff) +0 -2

-Magic numbers 1500, 1504 can be replaced by appropreate macros like- CPU_CS0_BAR, CPU_CS0_SZ
-Struct pointer can be declared in cpu.h like
   #define ORION5X_SDRAM_ADRDEC_BASE  (ORION5X_REGISTER(0x1500))
   ref( table 114 in 5182 users manual)

I know it's coming from referenced code but lets make new code the best. Also I will be updating old code too.

Quoted 10 lines

include/asm-arm/arch-orion5x/cpu.h new file +10 -0

+/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
+#define MV88F5181_DEV_ID        0x5181
+#define MV88F5181_REV_B1        3
+#define MV88F5181L_REV_A0       8
+#define MV88F5181L_REV_A1       9
+/* Orion-NAS (88F5182) */
+#define MV88F5182_DEV_ID        0x5182
+#define MV88F5182_REV_A2        2
+/* Orion-2 (88F5281) */
+#define MV88F5281_DEV_ID        0x5281

include/asm-arm/arch-orion5x/cpu.h line 129

Quoted 6 lines

include/asm-arm/arch-orion5x/cpu.h new file +6 -0

+#define MV88F5281_REV_D0        4
+#define MV88F5281_REV_D1        5
+#define MV88F5281_REV_D2        6
+/* Orion-1-90 (88F6183) */
+#define MV88F6183_DEV_ID        0x6183
+#define MV88F6183_REV_B0        3

These are Chip specific, should be moved to mv88f5182.h and similar headers for other Supported Chips

Regards.
Prafulla . .

-----Original Message-----
From: u-boot-bounces at lists.denx.de [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Albert Aribaud
Sent: Sunday, January 10, 2010 9:34 PM
To: U-Boot at lists.denx.de
Subject: [U-Boot] [PATCH V4 1/3] Initial support for Marvell Orion5x SoC

This patch adds support for the Marvell Orion5x SoC. It has no use alone, and must be followed by a patch to add Orion5x support for serial, then support for the ED Mini V2, an Orion5x-based product from LaCie.

Signed-off-by Albert Aribaud <[email protected]>

---
Patchset history

V1: Initial monolithic patch.
V2: split in three patches : orion, serial, edmini;
checkpatch'ed, with only 6 errors, in patch 1/3, all 6 errors being false positives.
V3: useless GPIO and MPP programming support removed;
low level init added/CONFIG_SKIP_LOW_LEVEL_INIT removed.
V4: all files licensed GPLv2-only removed;
RAM bank size detection now uses getm_ram_size().

 cpu/arm926ejs/orion5x/Makefile           |   51 ++++++
 cpu/arm926ejs/orion5x/cpu.c              |  258 

cpu/arm926ejs/orion5x/cpu.c new file +28 -0

+int print_cpuinfo(void)
+{
+	char dev_str[] = "0x0000";
+	char rev_str[] = "0x00";
+	char *dev_name = NULL;
+	char *rev_name = NULL;
+
+	u32 dev = orion5x_device_id();
+	u32 rev = orion5x_device_rev();
+
+	if (dev == MV88F5181_DEV_ID) {
+		dev_name = "MV88F5181";
+		if (rev == MV88F5181_REV_B1)
+			rev_name = "B1";
+		else if (rev == MV88F5181L_REV_A1) {
+			dev_name = "MV88F5181L";
+			rev_name = "A1";
+		} else if (rev == MV88F5181L_REV_A0) {
+			dev_name = "MV88F5181L";
+			rev_name = "A0";
+		}
+	} else if (dev == MV88F5182_DEV_ID) {
+		dev_name = "MV88F5182";
+		if (rev == MV88F5182_REV_A2)
+			rev_name = "A2";
+	} else if (dev == MV88F5281_DEV_ID) {
+		dev_name = "MV88F5281";
+		if (rev == MV88F5281_REV_D2)

Quoted 1 line

 cpu/arm926ejs/orion5x/cpu.c              |  258 

....snip....

Quoted 1 line

+int print_cpuinfo(void)

The above checks should be #ifdefed with CONFIG_88FXXXX (SOC type) There is no need to check for all SoC names, this will also reduce code size.