arm: msm: set L2CR1 to enable prefetch and burst on Scorpion.
RFC PATCH 6/12 arm: msm: set L2CR1 to enable prefetch and burst on Scorpion.
From: Larry Bassel <[email protected]>
This change improves the following LMBench benchmarks by over 15%:
System Call Latency
Signal Handling Latency
Fault Latency
Inter-process Communication Latency Inter-process Communication Bandwidth Random Number Generation Latency
--- arch/arm/mm/proc-v7.S | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-)
arch/arm/mm/proc-v7.S +5 -0
@@ -2,6 +2,7 @@ * linux/arch/arm/mm/proc-v7.S * * Copyright (C) 2001 Deep Blue Solutions Ltd. + * Copyright (c) 2009, Code Aurora Forum. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as
@@ -242,6 +243,10 @@ __v7_setup: mcr p15, 0, r4, c2, c0, 1 @ load TTB1 mov r10, #0x1f @ domains 0, 1 = manager mcr p15, 0, r10, c3, c0, 0 @ load domain access register +#ifdef CONFIG_ARCH_MSM_SCORPION + mov r0, #0x77 + mcr p15, 3, r0, c15, c0, 3 @ set L2CR1 +#endif /* * Memory region attributes with SCTLR.TRE=1 *
Signature · 1 line
1.6.3.3
RFC PATCH 6/12 arm: msm: set L2CR1 to enable prefetch and burst on Scorpion.
Quoted 28 lines · Daniel Walker
From: Larry Bassel <[email protected]>
This change improves the following LMBench benchmarks by over 15%:
System Call Latency
Signal Handling Latency
Fault Latency
Inter-process Communication Latency Inter-process Communication Bandwidth Random Number Generation LatencyAcked-by Steve Muckle <[email protected]>Cc Catalin Marinas <[email protected]>Cc Shilimkar, Santosh <[email protected]>Cc Nicolas Pitre <[email protected]>Cc Bohan, Michael <[email protected]>Signed-off-by Larry Bassel <[email protected]>Signed-off-by Daniel Walker <[email protected]>--- arch/arm/mm/proc-v7.S | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-)arch/arm/mm/proc-v7.S +0
-0
arch/arm/mm/proc-v7.S line 5
Quoted 4 lines
arch/arm/mm/proc-v7.S +1
-0@@ -2,6 +2,7 @@ * linux/arch/arm/mm/proc-v7.S * * Copyright (C) 2001 Deep Blue Solutions Ltd. + * Copyright (c) 2009, Code Aurora Forum. All rights reserved.
Do you really think the addition of only 4 lines in a file that contains 348 lines justifies the addition of such copyright notice? What would the kernel source looks like if everyone adding/modifying 4 lines in every random files did the same?
Just a thought.
Quoted 16 lines
arch/arm/mm/proc-v7.S +4
-0* This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as@@ -242,6 +243,10 @@ __v7_setup: mcr p15, 0, r4, c2, c0, 1 @ load TTB1 mov r10, #0x1f @ domains 0, 1 = manager mcr p15, 0, r10, c3, c0, 0 @ load domain access register +#ifdef CONFIG_ARCH_MSM_SCORPION + mov r0, #0x77 + mcr p15, 3, r0, c15, c0, 3 @ set L2CR1 +#endif /* * Memory region attributes with SCTLR.TRE=1 *Signature · 1 line
1.6.3.3
RFC PATCH 6/12 arm: msm: set L2CR1 to enable prefetch and burst on Scorpion.
Quoted 7 lines · Nicolas Pitre
Do you really think the addition of only 4 lines in a file that contains 348 lines justifies the addition of such copyright notice? What would the kernel source looks like if everyone adding/modifying 4 lines in every random files did the same?
Just a thought.
I don't disagree with you. It's actually a legal policy .. I can ask some questions regard it tho ..
Daniel
RFC PATCH 6/12 arm: msm: set L2CR1 to enable prefetch and burst on Scorpion.
Quoted 7 lines · Daniel Walker
Quoted 5 lines · Nicolas Pitre
Do you really think the addition of only 4 lines in a file that contains 348 lines justifies the addition of such copyright notice? What would the kernel source looks like if everyone adding/modifying 4 lines in every random files did the same?
Quoted 5 lines
Quoted 2 lines
Just a thought.
I don't disagree with you. It's actually a legal policy .. I can ask some questions regard it tho ..
The legalese is usually satisfied by the attribution and the meaning attached to the SOB carried in the commit message.
Nicolas
RFC PATCH 6/12 arm: msm: set L2CR1 to enable prefetch and burst on Scorpion.
In reply to Daniel WalkerQuoted 5 lines
I don't disagree with you. It's actually a legal policy .. I can ask some questions regard it tho ..
Daniel
It's fine to remove the Code Aurora copyright from this patch. As Nicolas noted, it shouldn't have been in there in the first place.
- Bryan
RFC PATCH 6/12 arm: msm: set L2CR1 to enable prefetch and burst on Scorpion.
In reply to Daniel WalkerHi!
Quoted 4 lines
From: Larry Bassel <[email protected]>
This change improves the following LMBench benchmarks by over 15%:
But what does this change do?
arch/arm/mm/proc-v7.S __v7_setup: · line 249
Quoted 8 lines
arch/arm/mm/proc-v7.S +4
-0@@ -242,6 +243,10 @@ __v7_setup: mcr p15, 0, r4, c2, c0, 1 @ load TTB1 mov r10, #0x1f @ domains 0, 1 = manager mcr p15, 0, r10, c3, c0, 0 @ load domain access register +#ifdef CONFIG_ARCH_MSM_SCORPION + mov r0, #0x77 + mcr p15, 3, r0, c15, c0, 3 @ set L2CR1 +#endif
...probably should be explained here...
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
RFC PATCH 6/12 arm: msm: set L2CR1 to enable prefetch and burst on Scorpion.
In reply to Daniel Walkerarch/arm/mm/proc-v7.S __v7_setup: · line 249
Quoted 8 lines · Daniel Walker
arch/arm/mm/proc-v7.S +4
-0@@ -242,6 +243,10 @@ __v7_setup: mcr p15, 0, r4, c2, c0, 1 @ load TTB1 mov r10, #0x1f @ domains 0, 1 = manager mcr p15, 0, r10, c3, c0, 0 @ load domain access register +#ifdef CONFIG_ARCH_MSM_SCORPION + mov r0, #0x77 + mcr p15, 3, r0, c15, c0, 3 @ set L2CR1 +#endif
I thought we want to move these out of the kernel into the boot loader (or boot monitor or bios or whatever it's called).
Signature · 1 line
Catalin
RFC PATCH 6/12 arm: msm: set L2CR1 to enable prefetch and burst on Scorpion.
Quoted 12 lines · Catalin Marinas
arch/arm/mm/proc-v7.S __v7_setup: · line 249
Quoted 8 lines · Daniel Walker
arch/arm/mm/proc-v7.S +4
-0@@ -242,6 +243,10 @@ __v7_setup: mcr p15, 0, r4, c2, c0, 1 @ load TTB1 mov r10, #0x1f @ domains 0, 1 = manager mcr p15, 0, r10, c3, c0, 0 @ load domain access register +#ifdef CONFIG_ARCH_MSM_SCORPION + mov r0, #0x77 + mcr p15, 3, r0, c15, c0, 3 @ set L2CR1 +#endifI thought we want to move these out of the kernel into the boot loader (or boot monitor or bios or whatever it's called).
I left it in cause it still felt like an open question the last time I submitted it ..
Honestly, I feel like we should keep as much control in Linux as possible.. Having it in Linux is just one place for it to get screwed up, vs. having it in many different boot loaders.
Daniel