change s3c24x0 register struct members to lower case

index afaa568..5464798 100644
@@ -30,6 +30,7 @@
 #include <asm/arch/s3c24x0_cpu.h>
 #include <stdio_dev.h>
 #include <i2c.h>
+#include <asm/io.h>
 
 #include "vcma9.h"
 #include "../common/common_util.h"

@@ -78,43 +79,44 @@ int board_init(void)
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
 	/* to reduce PLL lock time, adjust the LOCKTIME register */
-	clk_power->LOCKTIME = 0xFFFFFF;
+	writel(0xFFFFFF, &clk_power->locktime);
 
 	/* configure MPLL */
-	clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+	writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV, &clk_power->mpllcon);
 
 	/* some delay between MPLL and UPLL */
 	delay(4000);
 
 	/* configure UPLL */
-	clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+	writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV,
+	       &clk_power->upllcon);
 
 	/* some delay between MPLL and UPLL */
 	delay(8000);
 
 	/* set up the I/O ports */
-	gpio->GPACON = 0x007FFFFF;
-	gpio->GPBCON = 0x002AAAAA;
-	gpio->GPBUP = 0x000002BF;
-	gpio->GPCCON = 0xAAAAAAAA;
-	gpio->GPCUP = 0x0000FFFF;
-	gpio->GPDCON = 0xAAAAAAAA;
-	gpio->GPDUP = 0x0000FFFF;
-	gpio->GPECON = 0xAAAAAAAA;
-	gpio->GPEUP = 0x000037F7;
-	gpio->GPFCON = 0x00000000;
-	gpio->GPFUP = 0x00000000;
-	gpio->GPGCON = 0xFFEAFF5A;
-	gpio->GPGUP = 0x0000F0DC;
-	gpio->GPHCON = 0x0028AAAA;
-	gpio->GPHUP = 0x00000656;
+	writel(0x007FFFFF, &gpio->gpacon);
+	writel(0x002AAAAA, &gpio->gpbcon);
+	writel(0x000002BF, &gpio->gpbup);
+	writel(0xAAAAAAAA, &gpio->gpccon);
+	writel(0x0000FFFF, &gpio->gpcup);
+	writel(0xAAAAAAAA, &gpio->gpdcon);
+	writel(0x0000FFFF, &gpio->gpdup);
+	writel(0xAAAAAAAA, &gpio->gpecon);
+	writel(0x000037F7, &gpio->gpeup);
+	writel(0x00000000, &gpio->gpfcon);
+	writel(0x00000000, &gpio->gpfup);
+	writel(0xFFEAFF5A, &gpio->gpgcon);
+	writel(0x0000F0DC, &gpio->gpgup);
+	writel(0x0028AAAA, &gpio->gphcon);
+	writel(0x00000656, &gpio->gphup);
 
 	/* setup correct IRQ modes for NIC */
 	/* rising edge mode */
-	gpio->EXTINT2 = (gpio->EXTINT2 & ~(7 << 8)) | (4 << 8);
+	writel((readl(&gpio->extint2) & ~(7 << 8)) | (4 << 8), &gpio->extint2);
 
 	/* select USB port 2 to be host or device (fix to host for now) */
-	gpio->MISCCR |= 0x08;
+	writel(readl(&gpio->misccr) | 0x08, &gpio->misccr);
 
 	/* init serial */
 	gd->baudrate = CONFIG_BAUDRATE;

index 51dc050..2992b72 100644
@@ -41,14 +41,14 @@ inline void nf_conf(u16 conf)
 {
 	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
 
-	nand->NFCONF = conf;
+	writel(conf, &nand->nfconf);
 }
 
 inline void nf_cmd(u8 cmd)
 {
 	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
 
-	nand->NFCMD = cmd;
+	writel(cmd, &nand->nfcmd);
 }
 
 inline void nf_cmd_w(u8 cmd)

@@ -61,7 +61,7 @@ inline void nf_addr(u8 addr)
 {
 	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
 
-	nand->NFADDR = addr;
+	writel(addr, &nand->nfaddr);
 }
 
 inline void nf_set_ce(enum nfce_state s)

@@ -70,10 +70,10 @@ inline void nf_set_ce(enum nfce_state s)
 
 	switch (s) {
 	case nfce_low:
-		nand->NFCONF &= ~(1 << 11);
+		writel(readl(&nand->nfconf) & ~(1 << 11), &nand->nfconf);
 		break;
 	case nfce_high:
-		nand->NFCONF |= (1 << 11);
+		writel(readl(&nand->nfconf) | (1 << 11), &nand->nfconf);
 		break;
 	}
 }

@@ -82,7 +82,7 @@ inline void nf_wait_rb(void)
 {
 	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
 
-	while (!(nand->NFSTAT & (1 << 0)))
+	while (!(readl(&nand->nfstat) & (1 << 0)))
 		/* Wait */;
 }
 

@@ -90,28 +90,28 @@ inline void nf_write(u8 data)
 {
 	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
 
-	nand->NFDATA = data;
+	writel(data, &nand->nfdata);
 }
 
 inline u8 nf_read(void)
 {
 	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
 
-	return (nand->NFDATA);
+	return readl(&nand->nfdata);
 }
 
 inline void nf_init_ecc(void)
 {
 	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
 
-	nand->NFCONF |= (1 << 12);
+	writel(readl(&nand->nfconf) | (1 << 12), &nand->nfconf);
 }
 
 inline u32 nf_read_ecc(void)
 {
 	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
 
-	return (nand->NFECC);
+	return readl(&nand->nfecc);
 }
 
 #endif

index c2ce2ca..74ca08b 100644
@@ -28,6 +28,7 @@
 #include <common.h>
 #include <netdev.h>
 #include <asm/arch/s3c24x0_cpu.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -47,30 +48,30 @@ int board_init(void)
 
 	/* memory and cpu-speed are setup before relocation */
 	/* change the clock to be 50 MHz 1:1:1 */
-	clk_power->MPLLCON = 0x5c042;
-	clk_power->CLKDIVN = 0;
+	writel(0x5c042, &clk_power->mpllcon);
+	writel(0, &clk_power->clkdivn);
 	/* set up the I/O ports */
-	gpio->PACON = 0x3ffff;
-	gpio->PBCON = 0xaaaaaaaa;
-	gpio->PBUP = 0xffff;
-	gpio->PECON = 0x0;
-	gpio->PEUP = 0x0;
+	writel(0x3ffff, &gpio->pacon);
+	writel(0xaaaaaaaa, &gpio->pbcon);
+	writel(0xffff, &gpio->pbup);
+	writel(0x0, &gpio->pecon);
+	writel(0x0, &gpio->peup);
 #ifdef CONFIG_HWFLOW
 	/*CTS[0] RTS[0] INPUT INPUT TXD[0] INPUT RXD[0] */
 	/*   10,   10,   00,   00,    10,   00,    10 */
-	gpio->PFCON = 0xa22;
+	writel(0xa22, &gpio->pfcon);
 	/* Disable pull-up on Rx, Tx, CTS and RTS pins */
-	gpio->PFUP = 0x35;
+	writel(0x35, &gpio->pfup);
 #else
 	/*INPUT INPUT INPUT INPUT TXD[0] INPUT RXD[0] */
 	/*   00,   00,   00,   00,    10,   00,    10 */
-	gpio->PFCON = 0x22;
+	writel(0x22, &gpio->pfcon);
 	/* Disable pull-up on Rx and Tx pins */
-	gpio->PFUP = 0x5;
+	writel(0x5, &gpio->pfup);
 #endif	/* CONFIG_HWFLOW */
-	gpio->PGCON = 0x0;
-	gpio->PGUP = 0x0;
-	gpio->OPENCR = 0x0;
+	writel(0x0, &gpio->pgcon);
+	writel(0x0, &gpio->pgup);
+	writel(0x0, &gpio->opencr);
 
 	/* arch number of SAMSUNG-Board to MACH_TYPE_SMDK2400 */
 	gd->bd->bi_arch_number = MACH_TYPE_SMDK2400;

index e3a4490..7b64408 100644
@@ -28,6 +28,7 @@
 #include <common.h>
 #include <netdev.h>
 #include <asm/arch/s3c24x0_cpu.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -72,36 +73,37 @@ int board_init(void)
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
 	/* to reduce PLL lock time, adjust the LOCKTIME register */
-	clk_power->LOCKTIME = 0xFFFFFF;
+	writel(0xFFFFFF, &clk_power->locktime);
 
 	/* configure MPLL */
-	clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+	writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV, &clk_power->mpllcon);
 
 	/* some delay between MPLL and UPLL */
 	delay(4000);
 
 	/* configure UPLL */
-	clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+	writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV,
+	       &clk_power->upllcon);
 
 	/* some delay between MPLL and UPLL */
 	delay(8000);
 
 	/* set up the I/O ports */
-	gpio->GPACON = 0x007FFFFF;
-	gpio->GPBCON = 0x00044555;
-	gpio->GPBUP = 0x000007FF;
-	gpio->GPCCON = 0xAAAAAAAA;
-	gpio->GPCUP = 0x0000FFFF;
-	gpio->GPDCON = 0xAAAAAAAA;
-	gpio->GPDUP = 0x0000FFFF;
-	gpio->GPECON = 0xAAAAAAAA;
-	gpio->GPEUP = 0x0000FFFF;
-	gpio->GPFCON = 0x000055AA;
-	gpio->GPFUP = 0x000000FF;
-	gpio->GPGCON = 0xFF95FFBA;
-	gpio->GPGUP = 0x0000FFFF;
-	gpio->GPHCON = 0x002AFAAA;
-	gpio->GPHUP = 0x000007FF;
+	writel(0x007FFFFF, &gpio->gpacon);
+	writel(0x00044555, &gpio->gpbcon);
+	writel(0x000007FF, &gpio->gpbup);
+	writel(0xAAAAAAAA, &gpio->gpccon);
+	writel(0x0000FFFF, &gpio->gpcup);
+	writel(0xAAAAAAAA, &gpio->gpdcon);
+	writel(0x0000FFFF, &gpio->gpdup);
+	writel(0xAAAAAAAA, &gpio->gpecon);
+	writel(0x0000FFFF, &gpio->gpeup);
+	writel(0x000055AA, &gpio->gpfcon);
+	writel(0x000000FF, &gpio->gpfup);
+	writel(0xFF95FFBA, &gpio->gpgcon);
+	writel(0x0000FFFF, &gpio->gpgup);
+	writel(0x002AFAAA, &gpio->gphcon);
+	writel(0x000007FF, &gpio->gphup);
 
 	/* arch number of SMDK2410-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;

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index 4f30c23..27507ec 100644
@@ -31,6 +31,7 @@
 #include <i2c.h>
 #include <flash.h>
 #include <asm/arch/s3c24x0_cpu.h>
+#include <asm/io.h>
 #include "tsc2000.h"
 #include "trab.h"
 

index 2c31d50..5d686fe 100644
@@ -26,6 +26,7 @@
 #include <common.h>
 #include <command.h>
 #include <asm/arch/s3c24x0_cpu.h>
+#include <asm/io.h>
 #include <rtc.h>
 #include <i2c.h>
 #include "tsc2000.h"

@@ -604,28 +605,33 @@ static int adc_read(unsigned int channel)
 
 	adc_init();
 
-	padc->ADCCON &= ~ADC_STDBM;	/* select normal mode */
-	padc->ADCCON &= ~(0x7 << 3);	/* clear the channel bits */
-	padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START);
+	/* select normal mode */
+	writel(readl(&padc->adccon) & ~ADC_STDBM, &padc->adccon);
+	/* clear the channel bits */
+	writel(readl(&padc->adccon) & ~(0x7 << 3), &padc->adccon);
+	writel(readl(&padc->adccon) | ((channel << 3) | ADC_ENABLE_START),
+	       &padc->adccon);
 
 	while (j--) {
-		if ((padc->ADCCON & ADC_ENABLE_START) == 0)
+		if ((readl(&padc->adccon) & ADC_ENABLE_START) == 0)
 			break;
 		udelay(1);
 	}
 
 	if (j == 0) {
 		printf("%s: ADC timeout\n", __FUNCTION__);
-		padc->ADCCON |= ADC_STDBM;	/* select standby mode */
+		/* select standby mode */
+		writel(readl(&padc->adccon) | ADC_STDBM, &padc->adccon);
 		return -1;
 	}
 
-	result = padc->ADCDAT & 0x3FF;
+	result = readl(&padc->adcdat) & 0x3FF;
 
-	padc->ADCCON |= ADC_STDBM;	/* select standby mode */
+	/* select standby mode */
+	writel(readl(&padc->adccon) | ADC_STDBM, &padc->adccon);
 
 	debug("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__,
-	      (padc->ADCCON >> 3) & 0x7, result);
+	      (readl(&padc->adccon) >> 3) & 0x7, result);
 
 	/*
 	 * Wait for ADC to be ready for next conversion. This delay value was

@@ -642,8 +648,10 @@ static void adc_init(void)
 
 	padc = s3c2400_get_base_adc();
 
-	padc->ADCCON &= ~(0xff << 6);	/* clear prescaler bits */
-	padc->ADCCON |= ((65 << 6) | ADC_PRSCEN);	/* set prescaler */
+	/* clear prescaler bits */
+	writel(readl(&padc->adccon) & ~(0xff << 6), &padc->adccon);
+	/* set prescaler */
+	writel(readl(&padc->adccon) | ((65 << 6) | ADC_PRSCEN), &padc->adccon);
 
 	/*
 	 * Wait some time to avoid problem with very first call of

@@ -664,10 +672,10 @@ static void led_set(unsigned int state)
 
 	switch (state) {
 	case 0:	/* turn LED off */
-		gpio->PADAT |= (1 << 12);
+		writel(readl(&gpio->padat) | (1 << 12), &gpio->padat);
 		break;
 	case 1:	/* turn LED on */
-		gpio->PADAT &= ~(1 << 12);
+		writel(readl(&gpio->padat) & ~(1 << 12), &gpio->padat);
 		break;
 	default:
 		break;

@@ -693,8 +701,8 @@ static void led_init(void)
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
 	/* configure GPA12 as output and set to High -> LED off */
-	gpio->PACON &= ~(1 << 12);
-	gpio->PADAT |= (1 << 12);
+	writel(readl(&gpio->pacon) & ~(1 << 12), &gpio->pacon);
+	writel(readl(&gpio->padat) | (1 << 12), &gpio->padat);
 }
 
 static void sdelay(unsigned long seconds)

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index 2855825..c07b4df 100644
@@ -50,23 +50,23 @@ void tsc2000_spi_init(void)
 	int i;
 
 	/* Configure I/O ports. */
-	gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
-	gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000;
-	gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000;
-	gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000;
+	writel((readl(&gpio->pdcon) & 0xF3FFFF) | 0x040000, &gpio->pdcon);
+	writel((readl(&gpio->pgcon) & 0x0F3FFF) | 0x008000, &gpio->pgcon);
+	writel((readl(&gpio->pgcon) & 0x0CFFFF) | 0x020000, &gpio->pgcon);
+	writel((readl(&gpio->pgcon) & 0x03FFFF) | 0x080000, &gpio->pgcon);
 
 	CLR_CS_TOUCH();
 
 	/* Baud-rate ca. 514kHz */
-	spi->ch[0].SPPRE = 0x1F;
+	writel(0x1F, &spi->ch[0].sppre);
 	/* SPI-MOSI holds Level after last bit */
-	spi->ch[0].SPPIN = 0x01;
+	writel(0x01, &spi->ch[0].sppin);
 	/* Polling, Prescaler, Master, CPOL=0, CPHA=1 */
-	spi->ch[0].SPCON = 0x1A;
+	writel(0x1A, &spi->ch[0].spcon);
 
 	/* Dummy byte ensures clock to be low. */
 	for (i = 0; i < 10; i++)
-		spi->ch[0].SPTDAT = 0xFF;
+		writel(0xFF, &spi->ch[0].sptdat);
 	spi_wait_transmit_done();
 }
 

@@ -74,7 +74,7 @@ void spi_wait_transmit_done(void)
 {
 	struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
 
-	while (!(spi->ch[0].SPSTA & 0x01))
+	while (!(readl(&spi->ch[0].spsta) & 0x01))
 		/* wait until transfer is done */;
 }
 

@@ -85,13 +85,13 @@ void tsc2000_write(unsigned short reg, unsigned short data)
 
 	SET_CS_TOUCH();
 	command = reg;
-	spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+	writel((command & 0xFF00) >> 8, &spi->ch[0].sptdat);
 	spi_wait_transmit_done();
-	spi->ch[0].SPTDAT = (command & 0x00FF);
+	writel(command & 0x00FF, &spi->ch[0].sptdat);
 	spi_wait_transmit_done();
-	spi->ch[0].SPTDAT = (data & 0xFF00) >> 8;
+	writeb((data & 0xFF00) >> 8, &spi->ch[0].sptdat);
 	spi_wait_transmit_done();
-	spi->ch[0].SPTDAT = (data & 0x00FF);
+	writeb(data & 0x00FF, &spi->ch[0].sptdat);
 	spi_wait_transmit_done();
 
 	CLR_CS_TOUCH();

@@ -105,19 +105,19 @@ unsigned short tsc2000_read(unsigned short reg)
 	SET_CS_TOUCH();
 	command = 0x8000 | reg;
 
-	spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+	writel((command & 0xFF00) >> 8, &spi->ch[0].sptdat);
 	spi_wait_transmit_done();
-	spi->ch[0].SPTDAT = (command & 0x00FF);
+	writel(command & 0x00FF, &spi->ch[0].sptdat);
 	spi_wait_transmit_done();
 
-	spi->ch[0].SPTDAT = 0xFF;
+	writel(0xFF, &spi->ch[0].sptdat);
 	spi_wait_transmit_done();
-	data = spi->ch[0].SPRDAT;
-	spi->ch[0].SPTDAT = 0xFF;
+	data = readl(&spi->ch[0].sprdat);
+	writel(0xFF, &spi->ch[0].sptdat);
 	spi_wait_transmit_done();
 
 	CLR_CS_TOUCH();
-	return (spi->ch[0].SPRDAT & 0x0FF) | (data << 8);
+	return (readl(&spi->ch[0].sprdat) & 0x0FF) | (data << 8);
 }
 
 void tsc2000_set_mux(unsigned int channel)

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index 879fda6..5d7b05e 100644
@@ -33,10 +33,11 @@
 
 #include <asm/arch/s3c24x0_cpu.h>
 #include <asm/proc-armv/ptrace.h>
+#include <asm/io.h>
 
 void do_irq (struct pt_regs *pt_regs)
 {
 	struct s3c24x0_interrupt *irq = s3c24x0_get_base_interrupt();
-	u_int32_t intpnd = readl(&irq->INTPND);
+	u_int32_t intpnd = readl(&irq->intpnd);
 
 }

index b13283a..58e8865 100644
@@ -54,9 +54,9 @@ static ulong get_PLLCLK(int pllreg)
 	ulong r, m, p, s;
 
 	if (pllreg == MPLL)
-		r = readl(&clk_power->MPLLCON);
+		r = readl(&clk_power->mpllcon);
 	else if (pllreg == UPLL)
-		r = readl(&clk_power->UPLLCON);
+		r = readl(&clk_power->upllcon);
 	else
 		hang();
 

@@ -78,7 +78,7 @@ ulong get_HCLK(void)
 {
 	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
 
-	return (readl(&clk_power->CLKDIVN) & 2) ? get_FCLK() / 2 : get_FCLK();
+	return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK();
 }
 
 /* return PCLK frequency */

@@ -86,7 +86,7 @@ ulong get_PCLK(void)
 {
 	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
 
-	return (readl(&clk_power->CLKDIVN) & 1) ? get_HCLK() / 2 : get_HCLK();
+	return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 : get_HCLK();
 }
 
 /* return UCLK frequency */

index 7d47354..9fcfec2 100644
@@ -43,7 +43,7 @@ static inline ulong READ_TIMER(void)
 {
 	struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
 
-	return readl(&timers->TCNTO4) & 0xffff;
+	return readl(&timers->tcnto4) & 0xffff;
 }
 
 static ulong timestamp;

@@ -56,7 +56,7 @@ int timer_init(void)
 
 	/* use PWM Timer 4 because it has no output */
 	/* prescaler for Timer 4 is 16 */
-	writel(0x0f00, &timers->TCFG0);
+	writel(0x0f00, &timers->tcfg0);
 	if (timer_load_val == 0) {
 		/*
 		 * for 10 ms clock period @ PCLK with 4 bit divider = 1/2

@@ -68,13 +68,13 @@ int timer_init(void)
 	}
 	/* load value for 10 ms timeout */
 	lastdec = timer_load_val;
-	writel(timer_load_val, &timers->TCNTB4);
+	writel(timer_load_val, &timers->tcntb4);
 	/* auto load, manual update of Timer 4 */
-	tmr = (readl(&timers->TCON) & ~0x0700000) | 0x0600000;
-	writel(tmr, &timers->TCON);
+	tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
+	writel(tmr, &timers->tcon);
 	/* auto load, start Timer 4 */
 	tmr = (tmr & ~0x0700000) | 0x0500000;
-	writel(tmr, &timers->TCON);
+	writel(tmr, &timers->tcon);
 	timestamp = 0;
 
 	return (0);

@@ -206,13 +206,13 @@ void reset_cpu(ulong ignored)
 	watchdog = s3c24x0_get_base_watchdog();
 
 	/* Disable watchdog */
-	writel(0x0000, &watchdog->WTCON);
+	writel(0x0000, &watchdog->wtcon);
 
 	/* Initialize watchdog timer count register */
-	writel(0x0001, &watchdog->WTCNT);
+	writel(0x0001, &watchdog->wtcnt);
 
 	/* Enable watchdog timer; assert reset at timer timeout */
-	writel(0x0021, &watchdog->WTCON);
+	writel(0x0021, &watchdog->wtcon);
 
 	while (1)
 		/* loop forever and wait for reset to happen */;

index e468ed0..2033965 100644
@@ -39,14 +39,15 @@ int usb_cpu_init(void)
 	 * Set the 48 MHz UPLL clocking. Values are taken from
 	 * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
 	 */
-	writel((40 << 12) + (1 << 4) + 2, &clk_power->UPLLCON);
+	writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon);
+
 	/* 1 = use pads related USB for USB host */
-	writel(readl(&gpio->MISCCR) | 0x8, &gpio->MISCCR);
+	writel(readl(&gpio->misccr) | 0x8, &gpio->misccr);
 
 	/*
 	 * Enable USB host clock.
 	 */
-	writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON);
+	writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
 
 	return 0;
 }

@@ -55,14 +56,14 @@ int usb_cpu_stop(void)
 {
 	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
 	/* may not want to do this */
-	writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
+	writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
 	return 0;
 }
 
 int usb_cpu_init_fail(void)
 {
 	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-	writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
+	writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
 	return 0;
 }
 

index 5aa8d64..4799610 100644
@@ -1666,13 +1666,14 @@ int usb_lowlevel_init(void)
 	 * Set the 48 MHz UPLL clocking. Values are taken from
 	 * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
 	 */
-	clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
-	gpio->MISCCR |= 0x8;	/* 1 = use pads related USB for USB host */
+	writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon);
+	/* 1 = use pads related USB for USB host */
+	writel(readl(&gpio->misccr) | 0x8, &gpio->misccr);
 
 	/*
 	 * Enable USB host clock.
 	 */
-	clk_power->CLKCON |= (1 << 4);
+	writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
 
 	memset(&gohci, 0, sizeof(struct ohci));
 	memset(&urb_priv, 0, sizeof(struct urb_priv));

@@ -1709,7 +1710,8 @@ int usb_lowlevel_init(void)
 	if (hc_reset(&gohci) < 0) {
 		hc_release_ohci(&gohci);
 		/* Initialization failed */
-		clk_power->CLKCON &= ~(1 << 4);
+		writel(readl(&clk_power->clkcon) & ~(1 << 4),
+		       &clk_power->clkcon);
 		return -1;
 	}
 

@@ -1722,7 +1724,8 @@ int usb_lowlevel_init(void)
 		err("can't start usb-%s", gohci.slot_name);
 		hc_release_ohci(&gohci);
 		/* Initialization failed */
-		clk_power->CLKCON &= ~(1 << 4);
+		writel(readl(&clk_power->clkcon) & ~(1 << 4),
+		       &clk_power->clkcon);
 		return -1;
 	}
 #ifdef	DEBUG

@@ -1748,7 +1751,7 @@ int usb_lowlevel_stop(void)
 	/* call hc_release_ohci() here ? */
 	hc_reset(&gohci);
 	/* may not want to do this */
-	clk_power->CLKCON &= ~(1 << 4);
+	writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
 	return 0;
 }
 

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index a27d47e..ccc771f 100644
@@ -69,11 +69,11 @@ static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 		chip->IO_ADDR_W = (void *)IO_ADDR_W;
 
 		if (ctrl & NAND_NCE)
-			writel(readl(&nand->NFCONF) & ~S3C2410_NFCONF_nFCE,
-			       &nand->NFCONF);
+			writel(readl(&nand->nfconf) & ~S3C2410_NFCONF_nFCE,
+			       &nand->nfconf);
 		else
-			writel(readl(&nand->NFCONF) | S3C2410_NFCONF_nFCE,
-			       &nand->NFCONF);
+			writel(readl(&nand->nfconf) | S3C2410_NFCONF_nFCE,
+			       &nand->nfconf);
 	}
 
 	if (cmd != NAND_CMD_NONE)

@@ -84,7 +84,7 @@ static int s3c2410_dev_ready(struct mtd_info *mtd)
 {
 	struct s3c2410_nand *nand = s3c2410_get_base_nand();
 	debugX(1, "dev_ready\n");
-	return readl(&nand->NFSTAT) & 0x01;
+	return readl(&nand->nfstat) & 0x01;
 }
 
 #ifdef CONFIG_S3C2410_NAND_HWECC

@@ -92,16 +92,16 @@ void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 {
 	struct s3c2410_nand *nand = s3c2410_get_base_nand();
 	debugX(1, "s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode);
-	writel(readl(&nand->NFCONF) | S3C2410_NFCONF_INITECC, &nand->NFCONF);
+	writel(readl(&nand->nfconf) | S3C2410_NFCONF_INITECC, &nand->nfconf);
 }
 
 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 				      u_char *ecc_code)
 {
 	struct s3c2410_nand *nand = s3c2410_get_base_nand();
-	ecc_code[0] = readb(&nand->NFECC);
-	ecc_code[1] = readb(&nand->NFECC + 1);
-	ecc_code[2] = readb(&nand->NFECC + 2);
+	ecc_code[0] = readb(&nand->nfecc);
+	ecc_code[1] = readb(&nand->nfecc + 1);
+	ecc_code[2] = readb(&nand->nfecc + 2);
 	debugX(1, "s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n",
 	       mtd , ecc_code[0], ecc_code[1], ecc_code[2]);
 

@@ -130,7 +130,7 @@ int board_nand_init(struct nand_chip *nand)
 
 	debugX(1, "board_nand_init()\n");
 
-	writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON);
+	writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
 
 	/* initialize hardware */
 	twrph0 = 3;

@@ -141,10 +141,10 @@ int board_nand_init(struct nand_chip *nand)
 	cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
 	cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
 	cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
-	writel(cfg, &nand_reg->NFCONF);
+	writel(cfg, &nand_reg->nfconf);
 
 	/* initialize nand_chip data structure */
-	nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->NFDATA;
+	nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->nfdata;
 
 	nand->select_chip = NULL;
 

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index 5dd4dd8..a613229 100644
@@ -100,7 +100,7 @@ void _serial_setbrg(const int dev_index)
 	/* value is calculated so : (int)(PCLK/16./baudrate) -1 */
 	reg = get_PCLK() / (16 * gd->baudrate) - 1;
 
-	writel(reg, &uart->UBRDIV);
+	writel(reg, &uart->ubrdiv);
 	for (i = 0; i < 100; i++)
 		/* Delay */ ;
 }

@@ -130,26 +130,26 @@ static int serial_init_dev(const int dev_index)
 #endif
 
 	/* FIFO enable, Tx/Rx FIFO clear */
-	writel(0x07, &uart->UFCON);
-	writel(0x0, &uart->UMCON);
+	writel(0x07, &uart->ufcon);
+	writel(0x0, &uart->umcon);
 
 	/* Normal,No parity,1 stop,8 bit */
-	writel(0x3, &uart->ULCON);
+	writel(0x3, &uart->ulcon);
 	/*
 	 * tx=level,rx=edge,disable timeout int.,enable rx error int.,
 	 * normal,interrupt or polling
 	 */
-	writel(0x245, &uart->UCON);
+	writel(0x245, &uart->ucon);
 
 #ifdef CONFIG_HWFLOW
-	writel(0x1, &uart->UMCON);	/* RTS up */
+	writel(0x1, &uart->umcon);	/* RTS up */
 #endif
 
 	/* FIXME: This is sooooooooooooooooooo ugly */
 #if defined(CONFIG_ARCH_GTA02_v1) || defined(CONFIG_ARCH_GTA02_v2)
 	/* we need auto hw flow control on the gsm and gps port */
 	if (dev_index == 0 || dev_index == 1)
-		writel(0x10, &uart->UMCON);
+		writel(0x10, &uart->umcon);
 #endif
 	_serial_setbrg(dev_index);
 

@@ -175,10 +175,10 @@ int _serial_getc(const int dev_index)
 {
 	struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
 
-	while (!(readl(&uart->UTRSTAT) & 0x1))
+	while (!(readl(&uart->utrstat) & 0x1))
 		/* wait for character to arrive */ ;
 
-	return readb(&uart->URXH) & 0xff;
+	return readb(&uart->urxh) & 0xff;
 }
 
 #if defined(CONFIG_SERIAL_MULTI)

@@ -236,15 +236,15 @@ void _serial_putc(const char c, const int dev_index)
 		return;
 #endif
 
-	while (!(readl(&uart->UTRSTAT) & 0x2))
+	while (!(readl(&uart->utrstat) & 0x2))
 		/* wait for room in the tx FIFO */ ;
 
 #ifdef CONFIG_HWFLOW
-	while (hwflow && !(readl(&uart->UMSTAT) & 0x1))
+	while (hwflow && !(readl(&uart->umstat) & 0x1))
 		/* Wait for CTS up */ ;
 #endif
 
-	writeb(c, &uart->UTXH);
+	writeb(c, &uart->utxh);
 
 	/* If \n, also do \r */
 	if (c == '\n')

@@ -271,7 +271,7 @@ int _serial_tstc(const int dev_index)
 {
 	struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
 
-	return readl(&uart->UTRSTAT) & 0x1;
+	return readl(&uart->utrstat) & 0x1;
 }
 
 #if defined(CONFIG_SERIAL_MULTI)

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