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MX51: Moved board specific values in config file

PATCH New Stefano Babic 3 participants 7 messages Mar 16, 2010 – Apr 23, 2010 Arm/actions semi architecture

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Stefano Babic

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#0 lore raw

PATCH 1/1 MX51: Moved board specific values in config file

The lowlevel_init file contained some hard-coded values to setup the RAM. These board related values are moved into the board configuration file.

Signed-off-by Stefano Babic <[email protected]>
---
 cpu/arm_cortexa8/mx51/lowlevel_init.S |    5 ++++-
 include/configs/mx51evk.h             |    3 +++
 2 files changed, 7 insertions(+), 1 deletions(-)
cpu/arm_cortexa8/mx51/lowlevel_init.S +4 -1
index 31af9e2..1e393bb 100644
@@ -158,6 +158,7 @@
 	/* Switch peripheral to PLL 3 */
 	ldr r0, =CCM_BASE_ADDR
 	ldr r1, =0x000010C0
+ 	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
 	str r1, [r0, #CLKCTL_CBCMR]
 	ldr r1, =0x13239145
 	str r1, [r0, #CLKCTL_CBCDR]

@@ -171,6 +172,7 @@
 	ldr r1, =0x19239145
 	str r1, [r0, #CLKCTL_CBCDR]
 	ldr r1, =0x000020C0
+	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
 	str r1, [r0, #CLKCTL_CBCMR]
 
 	mov r3, #DP_OP_216

@@ -201,9 +203,10 @@
 	/* setup the rest */
 	/* Use lp_apm (24MHz) source for perclk */
 	ldr r1, =0x000020C2
+	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
 	str r1, [r0, #CLKCTL_CBCMR]
 	/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
-	ldr r1, =0x59E35100
+	ldr r1, =CONFIG_SYS_CLKTL_CBCDR
 	str r1, [r0, #CLKCTL_CBCDR]
 
 	/* Restore the default values in the Gate registers */
include/configs/mx51evk.h +3 -0
index e2daeca..5096ab7 100644
@@ -177,6 +177,9 @@
 #define PHYS_SDRAM_1		CSD0_BASE_ADDR
 #define PHYS_SDRAM_1_SIZE	(512 * 1024 * 1024)
 
+#define CONFIG_SYS_DDR_CLKSEL	0
+#define CONFIG_SYS_CLKTL_CBCDR	0x59E35100
+
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
Signature · 1 line
1.6.3.3
#1 lore raw

PATCH 1/1 MX51: Moved board specific values in config file

Quoted 3 lines · Stefano Babic

The lowlevel_init file contained some hard-coded values to setup the RAM. These board related values are moved into the board configuration file.

Why was only one value cleaned up?
Just from the patch, there are at least 4 more.

Quoted 12 lines
Signed-off-by Stefano Babic <[email protected]>
---
 cpu/arm_cortexa8/mx51/lowlevel_init.S |    5 ++++-
 include/configs/mx51evk.h             |    3 +++
 2 files changed, 7 insertions(+), 1 deletions(-)
cpu/arm_cortexa8/mx51/lowlevel_init.S +0 -0
index 31af9e2..1e393bb 100644

cpu/arm_cortexa8/mx51/lowlevel_init.S line 161

Quoted 4 lines
cpu/arm_cortexa8/mx51/lowlevel_init.S +1 -0
@@ -158,6 +158,7 @@
 	/* Switch peripheral to PLL 3 */
 	ldr r0, =CCM_BASE_ADDR
 	ldr r1, =0x000010C0
+ 	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL

git am complains about the leading space
Please remove

cpu/arm_cortexa8/mx51/lowlevel_init.S line 175

Quoted 8 lines
cpu/arm_cortexa8/mx51/lowlevel_init.S +1 -0
 	str r1, [r0, #CLKCTL_CBCMR]
 	ldr r1, =0x13239145
 	str r1, [r0, #CLKCTL_CBCDR]

@@ -171,6 +172,7 @@
 	ldr r1, =0x19239145
 	str r1, [r0, #CLKCTL_CBCDR]
 	ldr r1, =0x000020C0
+	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL

This is a noop as it is defined as 0.
Is the value going to change ?

Tom

author
#2 lore raw

PATCH 1/1 MX51: Moved board specific values in config file

Quoted 7 lines · Tom
Quoted 3 lines · Stefano Babic

The lowlevel_init file contained some hard-coded values to setup the RAM. These board related values are moved into the board configuration file.

Why was only one value cleaned up?
Just from the patch, there are at least 4 more.

Well, I prefer do not move a lot of configuration values inside the board config file and add only what it is really needed and when it is needed.

The fixed values you have seen set the CCM in a known status before updating it to the final value, and this procedure should be the same for all boards, as I undestood from Freescale's doc.

The patch adds configuration values to select the clock for DDR and the value of the related divider, and both depends on the board implementation.

Quoted 1 line
Quoted 1 line

+ orr r1,r1,#CONFIG_SYS_DDR_CLKSEL

I'll fix it, thanks.

Quoted 14 lines

git am complains about the leading space
Please remove

cpu/arm_cortexa8/mx51/lowlevel_init.S line 175

Quoted 8 lines
     str r1, [r0, #CLKCTL_CBCMR]
     ldr r1, =0x13239145
     str r1, [r0, #CLKCTL_CBCDR]
cpu/arm_cortexa8/mx51/lowlevel_init.S +1 -0
@@ -171,6 +172,7 @@
     ldr r1, =0x19239145
     str r1, [r0, #CLKCTL_CBCDR]
     ldr r1, =0x000020C0
+    orr r1,r1,#CONFIG_SYS_DDR_CLKSEL

This is a noop as it is defined as 0.
Is the value going to change ?

That is correct. The value selects which clock must be used for the DDR. On the mx51evk, this value must be set to 0. However, I know already another target that uses another clock source for the RAM.

Stefano

Signature · 5 lines
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DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
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#3 lore raw

PATCH 1/1 MX51: Moved board specific values in config file

Quoted 36 lines · Stefano Babic
Quoted 6 lines · Tom
Quoted 3 lines · Stefano Babic

The lowlevel_init file contained some hard-coded values to setup the RAM. These board related values are moved into the board configuration file.

Why was only one value cleaned up?
Just from the patch, there are at least 4 more.

Well, I prefer do not move a lot of configuration values inside the board config file and add only what it is really needed and when it is needed.

The fixed values you have seen set the CCM in a known status before updating it to the final value, and this procedure should be the same for all boards, as I undestood from Freescale's doc.

The patch adds configuration values to select the clock for DDR and the value of the related divider, and both depends on the board implementation.

Quoted 1 line
Quoted 1 line

+ orr r1,r1,#CONFIG_SYS_DDR_CLKSEL

I'll fix it, thanks.

Quoted 12 lines

git am complains about the leading space
Please remove

cpu/arm_cortexa8/mx51/lowlevel_init.S line 175

Quoted 8 lines
     str r1, [r0, #CLKCTL_CBCMR]
     ldr r1, =0x13239145
     str r1, [r0, #CLKCTL_CBCDR]
cpu/arm_cortexa8/mx51/lowlevel_init.S +1 -0
@@ -171,6 +172,7 @@
     ldr r1, =0x19239145
     str r1, [r0, #CLKCTL_CBCDR]
     ldr r1, =0x000020C0
+    orr r1,r1,#CONFIG_SYS_DDR_CLKSEL

This is a noop as it is defined as 0.
Is the value going to change ?

Quoted 4 lines

That is correct. The value selects which clock must be used for the DDR. On the mx51evk, this value must be set to 0. However, I know already another target that uses another clock source for the RAM.

That is a good reason.
Just a cleanup is needed
Tom

Quoted 2 lines

Stefano

author
#4 lore raw

PATCH v2 1/1 Moved board specific values in config file

In reply to Stefano Babic

The lowlevel_init file contained some hard-coded values to setup the RAM. These board related values are moved into the board configuration file.

Signed-off-by Stefano Babic <[email protected]>
---
 cpu/arm_cortexa8/mx51/lowlevel_init.S |    5 ++++-
 include/configs/mx51evk.h             |    3 +++
 2 files changed, 7 insertions(+), 1 deletions(-)
cpu/arm_cortexa8/mx51/lowlevel_init.S +4 -1
index 31af9e2..783c81f 100644
@@ -158,6 +158,7 @@
 	/* Switch peripheral to PLL 3 */
 	ldr r0, =CCM_BASE_ADDR
 	ldr r1, =0x000010C0
+	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
 	str r1, [r0, #CLKCTL_CBCMR]
 	ldr r1, =0x13239145
 	str r1, [r0, #CLKCTL_CBCDR]

@@ -171,6 +172,7 @@
 	ldr r1, =0x19239145
 	str r1, [r0, #CLKCTL_CBCDR]
 	ldr r1, =0x000020C0
+	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
 	str r1, [r0, #CLKCTL_CBCMR]
 
 	mov r3, #DP_OP_216

@@ -201,9 +203,10 @@
 	/* setup the rest */
 	/* Use lp_apm (24MHz) source for perclk */
 	ldr r1, =0x000020C2
+	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
 	str r1, [r0, #CLKCTL_CBCMR]
 	/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
-	ldr r1, =0x59E35100
+	ldr r1, =CONFIG_SYS_CLKTL_CBCDR
 	str r1, [r0, #CLKCTL_CBCDR]
 
 	/* Restore the default values in the Gate registers */
include/configs/mx51evk.h +3 -0
index e2daeca..5096ab7 100644
@@ -177,6 +177,9 @@
 #define PHYS_SDRAM_1		CSD0_BASE_ADDR
 #define PHYS_SDRAM_1_SIZE	(512 * 1024 * 1024)
 
+#define CONFIG_SYS_DDR_CLKSEL	0
+#define CONFIG_SYS_CLKTL_CBCDR	0x59E35100
+
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
Signature · 1 line
1.6.3.3
#5 lore raw

PATCH v2 1/1 Moved board specific values in config file

Stefano ,

Quoted 57 lines

-----Original Message-----
From: u-boot-bounces at lists.denx.de [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Stefano Babic
Sent: 2010?3?28? 19:43
To: u-boot at lists.denx.de
Subject: [U-Boot] [PATCH V2] Moved board specific values in config file

The lowlevel_init file contained some hard-coded values to setup the RAM. These board related values are moved into the board configuration file.

Signed-off-by Stefano Babic <[email protected]>
---
 cpu/arm_cortexa8/mx51/lowlevel_init.S |    5 ++++-
 include/configs/mx51evk.h             |    3 +++
 2 files changed, 7 insertions(+), 1 deletions(-)
cpu/arm_cortexa8/mx51/lowlevel_init.S +3 -0
index 31af9e2..783c81f 100644
@@ -158,6 +158,7 @@
 	/* Switch peripheral to PLL 3 */
 	ldr r0, =CCM_BASE_ADDR
 	ldr r1, =0x000010C0
+	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
 	str r1, [r0, #CLKCTL_CBCMR]
 	ldr r1, =0x13239145
 	str r1, [r0, #CLKCTL_CBCDR]

@@ -171,6 +172,7 @@
 	ldr r1, =0x19239145
 	str r1, [r0, #CLKCTL_CBCDR]
 	ldr r1, =0x000020C0
+	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
 	str r1, [r0, #CLKCTL_CBCMR]
 
 	mov r3, #DP_OP_216

@@ -201,9 +203,10 @@
 	/* setup the rest */
 	/* Use lp_apm (24MHz) source for perclk */
 	ldr r1, =0x000020C2
+	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
 	str r1, [r0, #CLKCTL_CBCMR]
 	/* ddr clock from PLL 1, all perclk dividers are 1

since using 24MHz */

cpu/arm_cortexa8/mx51/lowlevel_init.S +1 -1
-	ldr r1, =0x59E35100
+	ldr r1, =CONFIG_SYS_CLKTL_CBCDR
 	str r1, [r0, #CLKCTL_CBCDR]
 
 	/* Restore the default values in the Gate registers */
(quoted diff) +0 -0

b/include/configs/mx51evk.h index e2daeca..5096ab7 100644

include/configs/mx51evk.h line 181

Quoted 5 lines
include/configs/mx51evk.h +2 -0
@@ -177,6 +177,9 @@
 #define PHYS_SDRAM_1		CSD0_BASE_ADDR
 #define PHYS_SDRAM_1_SIZE	(512 * 1024 * 1024)
 
+#define CONFIG_SYS_DDR_CLKSEL	0
+#define CONFIG_SYS_CLKTL_CBCDR	0x59E35100

It's nice to have some comments about the value selected.

Quoted 15 lines
include/configs/mx51evk.h +1 -2
+
 
 /*------------------------------------------------------------
-----------
  * FLASH and environment organization
  */
--

1.6.3.3

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author
#6 lore raw

PATCH v2 1/1 Moved board specific values in config file

Quoted 2 lines · Liu Hui-R64343 wrote:

Stefano ,

Hi Jason,

Quoted 5 lines

include/configs/mx51evk.h line 181

Quoted 3 lines
include/configs/mx51evk.h +2 -0
+#define CONFIG_SYS_DDR_CLKSEL	0
+#define CONFIG_SYS_CLKTL_CBCDR	0x59E35100

It's nice to have some comments about the value selected.

This patch is more as one month old and was already merged into the mainline, so we need a new patch to for setting a comment. As your comment regards only the description to a configuration value, I will not do it now. However, I write down your comment for the next time this file will be changed ;)

Regards,
Stefano

Signature · 5 lines
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================