sh: fix clock framework on SH7757
PATCH 1/1 sh: fix clock framework on SH7757
- fix the recalc function's prototype
- This CPU don't have FRQCR
--- arch/sh/kernel/cpu/sh4a/clock-sh7757.c | 30 +++++++++--------------------- 1 files changed, 9 insertions(+), 21 deletions(-)
arch/sh/kernel/cpu/sh4a/clock-sh7757.c +9 -21
@@ -3,7 +3,7 @@* * SH7757 support for the clock framework * -* Copyright (C) 2009 Renesas Solutions Corp. +* Copyright (C) 2009-2010 Renesas Solutions Corp. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive
@@ -15,38 +15,28 @@#include <asm/clock.h> #include <asm/freq.h> -static int ifc_divisors[] = {2 ,1 ,4 ,1 ,1 ,8 ,1 ,1 , -16 ,1 ,1 ,32 ,1 ,1 ,1 ,1 }; -static int sfc_divisors[] = {2 ,1 ,4 ,1 ,1 ,8 ,1 ,1 , -16 ,1 ,1 ,32 ,1 ,1 ,1 ,1 }; -static int bfc_divisors[] = {2 ,1 ,4 ,1 ,1 ,8 ,1 ,1 , -16 ,1 ,1 ,32 ,1 ,1 ,1 ,1 }; -static int p1fc_divisors[] = {2 ,1 ,4 ,1 ,1 ,8 ,1 ,1 , -16 ,1 ,1 ,32 ,1 ,1 ,1 ,1 }; -static void master_clk_init (struct clk *clk) { - clk->rate =CONFIG_SH_PCLK_FREQ *16 ; + clk->rate =CONFIG_SH_PCLK_FREQ *12 ; }static struct clk_ops sh7757_master_clk_ops = { .init = master_clk_init, }; -static void module_clk_recalc (struct clk *clk) +static unsigned long module_clk_recalc (struct clk *clk) { -int idx =__raw_readl (FRQCR ) &0x0000000f ; - clk->rate = clk->parent->rate / p1fc_divisors[idx]; +return clk->parent->rate /12 ; }static struct clk_ops sh7757_module_clk_ops = { .recalc = module_clk_recalc, }; -static void bus_clk_recalc (struct clk *clk) +static unsigned long bus_clk_recalc (struct clk *clk) { -int idx = (__raw_readl (FRQCR ) >>8 ) &0x0000000f ; - clk->rate = clk->parent->rate / bfc_divisors[idx]; +/* Bus clock = P clock */ +return clk->parent->rate /12 ; }static struct clk_ops sh7757_bus_clk_ops = {
@@ -55,8 +45,7 @@ static struct clk_ops sh7757_bus_clk_ops = {static void cpu_clk_recalc (struct clk *clk) { -int idx = (__raw_readl (FRQCR ) >>20 ) &0x0000000f ; - clk->rate = clk->parent->rate / ifc_divisors[idx]; +return clk->parent->rate; }static struct clk_ops sh7757_cpu_clk_ops = {
@@ -78,8 +67,7 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)static void shyway_clk_recalc (struct clk *clk) { -int idx = (__raw_readl (FRQCR ) >>12 ) &0x0000000f ; - clk->rate = clk->parent->rate / sfc_divisors[idx]; +return clk->parent->rate /3 ; }static struct clk_ops sh7757_shyway_clk_ops = {
Signature · 1 line
1.5.5
Quoted 3 lines · Yoshihiro Shimoda
- fix the recalc function's prototype
- This CPU don't have FRQCR
Does it have FRQMR?
Does it support variable settings? If so, this just breaks it even further since you're just limiting it to one arbitrary configuration.
You can look at the updated SH7785 and SH7786 clock frameworks for an idea of how to deal with the FRQMR handling and MSTP-bits-as-clocks.
Any updates to existing subtypes in the clock framework should be moving them over to the new interfaces, rather than perpetuating a hardcoded pclk and divisors/multipliers for values that aren't fixed by the PLL.
Quoted 5 lines · Paul Mundt
Quoted 3 lines · Yoshihiro Shimoda
- fix the recalc function's prototype
- This CPU don't have FRQCRDoes it have FRQMR?
No, it doesn't have FRQMR.
But datasheet wasn't written it, actually this cpu may has this register. I will ask persion in charge about it.
Quoted 2 lines
Does it support variable settings? If so, this just breaks it even further since you're just limiting it to one arbitrary configuration.
This CPU has two clock mode. So I have to implement those mode.
Quoted 6 lines
You can look at the updated SH7785 and SH7786 clock frameworks for an idea of how to deal with the FRQMR handling and MSTP-bits-as-clocks.
Any updates to existing subtypes in the clock framework should be moving them over to the new interfaces, rather than perpetuating a hardcoded pclk and divisors/multipliers for values that aren't fixed by the PLL.
OK. I will study new clock framework and modify this code next week.
Thanks,
Yoshihiro Shimoda