ARM1136: Fix cache_flush() error and correct cpu_init_crit() comments

The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0" instruction which means "Invalidate Both Caches

" when in fact the intent
is to "Clean and Invalidate Entire Data Cache".

Hi George,

Quoted 3 lines · George G. Davis

The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0" instruction which means "Invalidate Both Caches

... Also flushes the branch target cache"

Quoted 2 lines

" when in fact the intent
is to "Clean and Invalidate Entire Data Cache".

Why don't we have to invalidate/flush the I- and BT-Cache here? I.e. why is it sufficient to clean & invalidate the D-Cache here, only, and remove the existing I- and BT-Cache invalidation/flushing?

What's about just adding an additional clean of the data cache before the 'invalidate all':

+ asm ("mcr p15, 0, %0, c7, c10, 0": :"r" (i)); ?/* clean entire data cache */ asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); ?/* invalidate both caches and flush btb */ asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */

?

Thanks for finding this and best regards

Dirk

Quoted 2 lines

Why don't we have to invalidate/flush the I- and BT-Cache here? I.e. why

is it sufficient to clean & invalidate the D-Cache here, only, and remove the existing I- and BT-Cache invalidation/flushing?

Quite frankly I thought for sure that it was handled elsewhere but now that I look I see that it's not. Meanwhile, I don't think U-Boot is typically susceptible to self-modifying-code issues anyway (?) and

this isn't likely required but I suppose lack of I+BTB invalidation

Dear "George G. Davis",

In message <[email protected]>

Quoted 2 lines · you

Quoted 2 lines

Why don't we have to invalidate/flush the I- and BT-Cache here? I.e.

why

Quoted 6 lines

is it sufficient to clean & invalidate the D-Cache here, only, and remove the existing I- and BT-Cache invalidation/flushing?

Quite frankly I thought for sure that it was handled elsewhere but now that I look I see that it's not. Meanwhile, I don't think U-Boot is typically susceptible to self-modifying-code issues anyway (?) and

What has self-modifying-code to do with it? Proper cache handling is mandatory in manyother siutuations as well, including when you load code (Linux kernel, standalone applications) and then try to execute these, or when dealing with I/O buffers, DMA, etc.

Quoted 1 line

this isn't likely required but I suppose lack of I+BTB invalidation

I think it is mandatory.

Best regards,

Wolfgang Denk

--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de A direct quote from the Boss: "We passed over a lot of good people to get the ones we hired."

From: George G. Davis<[email protected]>

The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0" instruction which means "Invalidate Both Caches" when in fact the intent is to clean and invalidate all caches. So add an "mcr p15, 0, %0, c7, c10, 0" instruction to "Clean Entire Data Cache" prior to the "Invalidate Both Caches" instruction to insure that memory is consistent with any dirty cache lines.

Also fix a couple of "flush v*" comments in ARM1136 cpu_init_crit() so that they correctly describe the actual ARM1136 CP15 C7 Cache Operations used.

Signed-off-by George G. Davis<[email protected]>

---
  arch/arm/cpu/arm1136/cpu.c   |    1 +
  arch/arm/cpu/arm1136/start.S |    4 ++--
  2 files changed, 3 insertions(+), 2 deletions(-)

arch/arm/cpu/arm1136/cpu.c +1 -0

index ade7f46..2b91631 100644
@@ -71,6 +71,7 @@ static void cache_flush(void)
  {
  	unsigned long i = 0;
 
+	asm ("mcr p15, 0, %0, c7, c10, 0": :"r" (i)); /* clean entire data cache */
  	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));  /* invalidate both caches and flush btb */
  	asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */
  }

arch/arm/cpu/arm1136/start.S +2 -2

index 957f438..922d01c 100644
@@ -226,8 +226,8 @@ cpu_init_crit:
  	 * flush v4 I/D caches
  	 */
  	mov	r0, #0
-	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
-	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+	mcr	p15, 0, r0, c7, c7, 0	/* Invalidate I+D+BTB caches */
+	mcr	p15, 0, r0, c8, c7, 0	/* Invalidate Unified TLB */
 
  	/*
  	 * disable MMU stuff and caches

Quoted 9 lines · gdavis at mvista.com

From: George G. Davis<[email protected]>

The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0" instruction which means "Invalidate Both Caches" when in fact the intent is to clean and invalidate all caches. So add an "mcr p15, 0, %0, c7, c10, 0" instruction to "Clean Entire Data Cache" prior to the "Invalidate Both Caches" instruction to insure that memory is consistent with any dirty cache lines.

Quoted 5 lines

Also fix a couple of "flush v*" comments in ARM1136 cpu_init_crit() so that they correctly describe the actual ARM1136 CP15 C7 Cache Operations used.

Signed-off-by George G. Davis<[email protected]>

Acked-by Dirk Behme <[email protected]>

Thanks

Dirk

Quoted 32 lines

---
 arch/arm/cpu/arm1136/cpu.c   |    1 +
 arch/arm/cpu/arm1136/start.S |    4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

arch/arm/cpu/arm1136/cpu.c +1 -0

index ade7f46..2b91631 100644
@@ -71,6 +71,7 @@ static void cache_flush(void)
 {
 	unsigned long i = 0;
 
+	asm ("mcr p15, 0, %0, c7, c10, 0": :"r" (i)); /* clean entire data cache */
 	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));  /* invalidate both caches and flush btb */
 	asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */
 }

arch/arm/cpu/arm1136/start.S +2 -2

index 957f438..922d01c 100644
@@ -226,8 +226,8 @@ cpu_init_crit:
 	 * flush v4 I/D caches
 	 */
 	mov	r0, #0
-	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
-	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+	mcr	p15, 0, r0, c7, c7, 0	/* Invalidate I+D+BTB caches */
+	mcr	p15, 0, r0, c8, c7, 0	/* Invalidate Unified TLB */
 
 	/*
 	 * disable MMU stuff and caches

From: George G. Davis <[email protected]>

The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0" instruction which means "Invalidate Both Caches" when in fact the intent is to clean and invalidate all caches. So add an "mcr p15, 0, %0, c7, c10, 0" instruction to "Clean Entire Data Cache" prior to the "Invalidate Both Caches" instruction to insure that memory is consistent with any dirty cache lines.

Also fix a couple of "flush v*" comments in ARM1136 cpu_init_crit() so that they correctly describe the actual ARM1136 CP15 C7 Cache Operations used.

Signed-off-by George G. Davis <[email protected]>

Quoted 9 lines · gdavis at mvista.com

From: George G. Davis <[email protected]>

The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0" instruction which means "Invalidate Both Caches" when in fact the intent is to clean and invalidate all caches. So add an "mcr p15, 0, %0, c7, c10, 0" instruction to "Clean Entire Data Cache" prior to the "Invalidate Both Caches" instruction to insure that memory is consistent with any dirty cache lines.

Quoted 5 lines

Also fix a couple of "flush v*" comments in ARM1136 cpu_init_crit() so that they correctly describe the actual ARM1136 CP15 C7 Cache Operations used.

Signed-off-by George G. Davis <[email protected]>

Applied to arm/master

Thanks
Tom