PPC LBC/TLB cleanups; reginfo command for 85xx

PATCH Superseded Becky Bruce 4 participants 25 messages Jun 2, 2010 – Jun 8, 2010

Subsystems (7)

USB PowerPC Kbuild Memory technology devices (MTD) +3 more subsystems

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Becky Bruce

author

2010-06-02 18:11 UTC #0 lore raw

v2 cover PPC LBC/TLB cleanups; reginfo command for 85xx

This somewhat random patch series got its start when I was asked to create a reginfo command for 85xx by one of the internal teams here at FSL to dump the BR/ORs, LAWs, and the TLBCAM entries. As I started doing that, I began to notice that there was a lot of duplicated and inconsistent code for manipulating the TLBs and LBC registers, which, in some cases, would have caused me to have to write extra code to make reginfo useful on multiple platforms. So I decided to clean this up. The bulk of these patches are just merges of duplicated code and renames of things to get to a consistent naming scheme.

These really need to be picked up by a single maintainer, as there's a definite dependency chain here; I'll let Kumar and Wolfgang decide who wants it.

Wolfgang, my makefile changes are going to conflict with your top-level makefile changes that are posted on the list but not yet in the tree - you should be able to just incorporate my changes, or you can poke me when yours are in the tree and I can deal with it.

NOTE: Updated from the original version to incorporate feedback - removed unnecessary volatiles in the upmconfig code, made the definition of FSL_LBC dependent on 85xx/86xx/83xx, and moved the ohci readl/writel defs into a header.

Diffstat below.

Cheers,
Becky

 MAKEALL                                        |    2 +
 Makefile                                       |    1 +
 arch/powerpc/cpu/mpc83xx/cpu.c                 |   66 ------------
 arch/powerpc/cpu/mpc83xx/cpu_init.c            |   53 ++--------
 arch/powerpc/cpu/mpc83xx/nand_init.c           |    4 +-
 arch/powerpc/cpu/mpc83xx/speed.c               |    2 +-
 arch/powerpc/cpu/mpc85xx/cpu.c                 |   78 +++-----------
 arch/powerpc/cpu/mpc85xx/cpu_init.c            |   58 +----------
 arch/powerpc/cpu/mpc85xx/cpu_init_nand.c       |    6 +-
 arch/powerpc/cpu/mpc85xx/speed.c               |    5 +-
 arch/powerpc/cpu/mpc85xx/tlb.c                 |   70 ++++++++-----
 arch/powerpc/cpu/mpc86xx/cpu.c                 |   15 +---
 arch/powerpc/cpu/mpc86xx/cpu_init.c            |   55 +----------
 arch/powerpc/cpu/mpc86xx/speed.c               |    5 +-
 arch/powerpc/cpu/mpc8xxx/Makefile              |    3 +
 arch/powerpc/cpu/mpc8xxx/fsl_lbc.c             |  135 ++++++++++++++++++++++++
 arch/powerpc/include/asm/config.h              |    6 +
 arch/powerpc/include/asm/fsl_law.h             |    1 +
 arch/powerpc/include/asm/fsl_lbc.h             |  112 ++++++++++++--------
 arch/powerpc/include/asm/immap_83xx.h          |   13 ++-
 arch/powerpc/include/asm/immap_85xx.h          |   46 +--------
 arch/powerpc/include/asm/immap_86xx.h          |   49 +--------
 arch/powerpc/include/asm/mmu.h                 |    2 +
 board/atum8548/atum8548.c                      |    2 +-
 board/esd/vme8349/vme8349.c                    |    2 +-
 board/freescale/mpc8313erdb/sdram.c            |    2 +-
 board/freescale/mpc8349emds/mpc8349emds.c      |    2 +-
 board/freescale/mpc8349itx/mpc8349itx.c        |    7 +-
 board/freescale/mpc8360emds/mpc8360emds.c      |    6 +-
 board/freescale/mpc8360erdk/nand.c             |    6 +-
 board/freescale/mpc8540ads/mpc8540ads.c        |    8 +-
 board/freescale/mpc8541cds/mpc8541cds.c        |   13 +--
 board/freescale/mpc8544ds/mpc8544ds.c          |    2 +-
 board/freescale/mpc8548cds/mpc8548cds.c        |   13 +--
 board/freescale/mpc8555cds/mpc8555cds.c        |   12 +--
 board/freescale/mpc8560ads/mpc8560ads.c        |    8 +-
 board/freescale/mpc8568mds/mpc8568mds.c        |   11 +--
 board/freescale/mpc8569mds/mpc8569mds.c        |    2 +-
 board/mpc8540eval/mpc8540eval.c                |    6 +-
 board/pm854/pm854.c                            |    2 +-
 board/pm856/pm856.c                            |    2 +-
 board/sbc8349/sbc8349.c                        |    2 +-
 board/sbc8548/sbc8548.c                        |   20 +---
 board/sbc8560/sbc8560.c                        |    6 +-
 board/sheldon/simpc8313/sdram.c                |    2 +-
 board/sheldon/simpc8313/simpc8313.c            |    2 +-
 board/socrates/socrates.c                      |   31 +++---
 board/tqc/tqm834x/tqm834x.c                    |    8 +-
 board/tqc/tqm85xx/nand.c                       |   12 +-
 board/tqc/tqm85xx/tqm85xx.c                    |   35 +++---
 board/xes/xpedite5170/xpedite5170.c            |   10 +-
 board/xes/xpedite5200/xpedite5200.c            |   11 +-
 board/xes/xpedite5370/xpedite5370.c            |    9 +-
 common/cmd_reginfo.c                           |    5 +
 drivers/misc/fsl_law.c                         |  131 ++++++++++--------------
 drivers/mtd/nand/fsl_elbc_nand.c               |   18 ++--
 drivers/usb/host/ohci-hcd.c                    |   11 --
 drivers/usb/host/ohci.h                        |   13 +++
 include/configs/MPC8313ERDB.h                  |    1 +
 include/configs/MPC8315ERDB.h                  |    1 +
 include/configs/MPC837XEMDS.h                  |    1 +
 include/configs/MPC8536DS.h                    |    1 +
 include/configs/MPC8540EVAL.h                  |    1 +
 include/configs/MPC8541CDS.h                   |    1 +
 include/configs/MPC8544DS.h                    |    1 +
 include/configs/MPC8548CDS.h                   |    1 +
 include/configs/MPC8555CDS.h                   |    1 +
 include/configs/MPC8560ADS.h                   |    1 +
 include/configs/MPC8568MDS.h                   |    1 +
 include/configs/MPC8569MDS.h                   |    1 +
 include/configs/MPC8572DS.h                    |    1 +
 include/configs/P1_P2_RDB.h                    |    1 +
 include/configs/P2020DS.h                      |    1 +
 include/configs/PM854.h                        |    1 +
 include/configs/PM856.h                        |    1 +
 include/configs/SBC8540.h                      |    1 +
 include/configs/SIMPC8313.h                    |    1 +
 include/configs/TQM85xx.h                      |    1 +
 include/configs/XPEDITE5200.h                  |    1 +
 include/configs/XPEDITE5370.h                  |    2 +
 include/configs/sbc8548.h                      |    1 +
 include/configs/sbc8560.h                      |    1 +
 include/configs/socrates.h                     |    1 +
 include/configs/stxgp3.h                       |    1 +
 include/configs/stxssa.h                       |    1 +
 include/mpc85xx.h                              |    2 -
 nand_spl/board/freescale/mpc8536ds/nand_boot.c |    5 +-
 nand_spl/nand_boot_fsl_elbc.c                  |    4 +-

Becky Bruce

author

2010-06-02 18:12 UTC #1 lore raw

PATCH v2 1/10 powerpc: Update configs to properly set FSL_ELBC

Some parts that have an Enhanced Local Bus Controller weren't setting CONFIG_FSL_ELBC. Fix this so we can use this define properly going forward (currently it's only used if PHYS_64BIT is set, which meant not all platforms needed to have it set correctly).

Signed-off-by Becky Bruce <[email protected]>

---
 include/configs/MPC8313ERDB.h |    1 +
 include/configs/MPC8315ERDB.h |    1 +
 include/configs/MPC837XEMDS.h |    1 +
 include/configs/SIMPC8313.h   |    1 +
 include/configs/XPEDITE5370.h |    1 +
 5 files changed, 5 insertions(+), 0 deletions(-)

include/configs/MPC8313ERDB.h +1 -0

index 94695fc..7858e1f 100644
@@ -36,6 +36,7 @@
 #define CONFIG_MPC8313ERDB	1
 
 #define CONFIG_PCI
+#define CONFIG_FSL_ELBC 1
 
 #define CONFIG_MISC_INIT_R

include/configs/MPC8315ERDB.h +1 -0

index 6972fe8..f1b110b 100644
@@ -197,6 +197,7 @@
 #define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
 #define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
 #define CONFIG_SYS_LBC_LBCR		0x00040000
+#define CONFIG_FSL_ELBC		1
 
 /*
  * FLASH on the Local Bus

include/configs/MPC837XEMDS.h +1 -0

index b30d0e3..9092755 100644
@@ -223,6 +223,7 @@
 #define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
 #define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8
 #define CONFIG_SYS_LBC_LBCR		0x00000000
+#define CONFIG_FSL_ELBC		1
 
 /*
  * FLASH on the Local Bus

include/configs/SIMPC8313.h +1 -0

index 9104f1a..7a6def4 100644
@@ -37,6 +37,7 @@
 #define CONFIG_MPC8313			1
 
 #define CONFIG_PCI
+#define CONFIG_FSL_ELBC			1
 
 #define CONFIG_MISC_INIT_R

include/configs/XPEDITE5370.h +1 -0

index 7fd3668..20a6753 100644
@@ -47,6 +47,7 @@
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+#define CONFIG_FSL_ELBC		1
 
 /*
  * Multicore config

Signature · 1 line

1.6.0.6

Becky Bruce

author

2010-06-02 18:12 UTC #2 lore raw

PATCH v2 2/10 drivers/usb/host/ohci-hcd: undef readl/writel before redefining

This avoids a build warning that you see if anyone in the header chain has included io.h (which is coming shortly). I also move this to the "ohci.h" header file in the same dir, which is cleaner.

Signed-off-by Becky Bruce <[email protected]>

---
 drivers/usb/host/ohci-hcd.c |   11 -----------
 drivers/usb/host/ohci.h     |   13 +++++++++++++
 2 files changed, 13 insertions(+), 11 deletions(-)

drivers/usb/host/ohci-hcd.c +0 ~~-11~~

index b03a600..3ffdc9d 100644
@@ -83,17 +83,6 @@
 #define OHCI_CONTROL_INIT \
 	(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
 
-/*
- * e.g. PCI controllers need this
- */
-#ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS
-# define readl(a) __swap_32(*((volatile u32 *)(a)))
-# define writel(a, b) (*((volatile u32 *)(b)) = __swap_32((volatile u32)a))
-#else
-# define readl(a) (*((volatile u32 *)(a)))
-# define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
-#endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */
-
 #define min_t(type, x, y) \
 		    ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })

drivers/usb/host/ohci.h +13 -0

index 79aa79d..fa4ecc8 100644
@@ -7,6 +7,19 @@
  * usb-ohci.h
  */
 
+/*
+ * e.g. PCI controllers need this
+ */
+#undef readl
+#undef writel
+#ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+# define readl(a) __swap_32(*((volatile u32 *)(a)))
+# define writel(a, b) (*((volatile u32 *)(b)) = __swap_32((volatile u32)a))
+#else
+# define readl(a) (*((volatile u32 *)(a)))
+# define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
+#endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */
+
 /* functions for doing board or CPU specific setup/cleanup */
 extern int usb_board_init(void);
 extern int usb_board_stop(void);

Signature · 1 line

1.6.0.6

Becky Bruce

author

2010-06-02 18:12 UTC #3 lore raw

PATCH v2 3/10 83xx/85xx/86xx: LBC register cleanup

Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot.

To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former.

In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play.

I have done a successful ppc build all and tested a board or two from each processor family.

---
 Makefile                                       |    1 +
 arch/powerpc/cpu/mpc83xx/cpu.c                 |   12 ++--
 arch/powerpc/cpu/mpc83xx/cpu_init.c            |   53 ++----------
 arch/powerpc/cpu/mpc83xx/nand_init.c           |    4 +-
 arch/powerpc/cpu/mpc83xx/speed.c               |    2 +-
 arch/powerpc/cpu/mpc85xx/cpu.c                 |   12 +--
 arch/powerpc/cpu/mpc85xx/cpu_init.c            |   58 +------------
 arch/powerpc/cpu/mpc85xx/cpu_init_nand.c       |    6 +-
 arch/powerpc/cpu/mpc85xx/speed.c               |    5 +-
 arch/powerpc/cpu/mpc86xx/cpu.c                 |   15 +---
 arch/powerpc/cpu/mpc86xx/cpu_init.c            |   55 +------------
 arch/powerpc/cpu/mpc86xx/speed.c               |    5 +-
 arch/powerpc/cpu/mpc8xxx/Makefile              |    3 +
 arch/powerpc/cpu/mpc8xxx/fsl_lbc.c             |   84 ++++++++++++++++++
 arch/powerpc/include/asm/config.h              |    6 ++
 arch/powerpc/include/asm/fsl_lbc.h             |  109 ++++++++++++++----------
 arch/powerpc/include/asm/immap_83xx.h          |   13 ++--
 arch/powerpc/include/asm/immap_85xx.h          |   46 +----------
 arch/powerpc/include/asm/immap_86xx.h          |   49 +----------
 board/atum8548/atum8548.c                      |    2 +-
 board/esd/vme8349/vme8349.c                    |    2 +-
 board/freescale/mpc8313erdb/sdram.c            |    2 +-
 board/freescale/mpc8349emds/mpc8349emds.c      |    2 +-
 board/freescale/mpc8349itx/mpc8349itx.c        |    7 +-
 board/freescale/mpc8360emds/mpc8360emds.c      |    6 +-
 board/freescale/mpc8360erdk/nand.c             |    6 +-
 board/freescale/mpc8540ads/mpc8540ads.c        |    8 +-
 board/freescale/mpc8541cds/mpc8541cds.c        |   13 +--
 board/freescale/mpc8544ds/mpc8544ds.c          |    2 +-
 board/freescale/mpc8548cds/mpc8548cds.c        |   13 +--
 board/freescale/mpc8555cds/mpc8555cds.c        |   12 +--
 board/freescale/mpc8560ads/mpc8560ads.c        |    8 +-
 board/freescale/mpc8568mds/mpc8568mds.c        |   11 +--
 board/freescale/mpc8569mds/mpc8569mds.c        |    2 +-
 board/mpc8540eval/mpc8540eval.c                |    6 +-
 board/pm854/pm854.c                            |    2 +-
 board/pm856/pm856.c                            |    2 +-
 board/sbc8349/sbc8349.c                        |    2 +-
 board/sbc8548/sbc8548.c                        |   20 ++---
 board/sbc8560/sbc8560.c                        |    6 +-
 board/sheldon/simpc8313/sdram.c                |    2 +-
 board/sheldon/simpc8313/simpc8313.c            |    2 +-
 board/socrates/socrates.c                      |   31 +++----
 board/tqc/tqm834x/tqm834x.c                    |    8 +-
 board/tqc/tqm85xx/nand.c                       |   12 ++--
 board/tqc/tqm85xx/tqm85xx.c                    |   35 ++++----
 board/xes/xpedite5170/xpedite5170.c            |   10 +--
 board/xes/xpedite5200/xpedite5200.c            |   11 +--
 board/xes/xpedite5370/xpedite5370.c            |    9 +-
 drivers/mtd/nand/fsl_elbc_nand.c               |   18 ++---
 include/mpc85xx.h                              |    2 -
 nand_spl/board/freescale/mpc8536ds/nand_boot.c |    5 +-
 nand_spl/nand_boot_fsl_elbc.c                  |    4 +-
 53 files changed, 321 insertions(+), 500 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc8xxx/fsl_lbc.c

Makefile +1 -0

index c26e491..2d4327a 100644
@@ -220,6 +220,7 @@ LIBS += drivers/power/libpower.a
 LIBS += drivers/spi/libspi.a
 ifeq ($(CPU),mpc83xx)
 LIBS += drivers/qe/qe.a
+LIBS += arch/powerpc/cpu/mpc8xxx/lib8xxx.a
 endif
 ifeq ($(CPU),mpc85xx)
 LIBS += drivers/qe/qe.a

arch/powerpc/cpu/mpc83xx/cpu.c +6 -6

index d3be909..24193ce 100644
@@ -156,16 +156,16 @@ int checkcpu(void)
 void upmconfig (uint upm, uint *table, uint size)
 {
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile fsl_lbus_t *lbus = &immap->lbus;
+	volatile fsl_lbc_t *lbc = &immap->im_lbc;
 	volatile uchar *dummy = NULL;
 	const u32 msel = (upm + 4) << BR_MSEL_SHIFT;	/* What the MSEL field in BRn should be */
-	volatile u32 *mxmr = &lbus->mamr + upm;	/* Pointer to mamr, mbmr, or mcmr */
+	volatile u32 *mxmr = &lbc->mamr + upm;	/* ptr to mamr, mbmr, or mcmr */
 	uint i;
 
-	/* Scan all the banks to determine the base address of the device */
+	/* Find the address for the dummy write transaction */
 	for (i = 0; i < 8; i++) {
-		if ((lbus->bank[i].br & BR_MSEL) == msel) {
-			dummy = (uchar *) (lbus->bank[i].br & BR_BA);
+		if ((get_lbc_br(i) & BR_MSEL) == msel) {
+			dummy = (uchar *) (get_lbc_br(i) & BR_BA);
 			break;
 		}
 	}

@@ -179,7 +179,7 @@ void upmconfig (uint upm, uint *table, uint size)
 	*mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
 
 	for (i = 0; i < size; i++) {
-		lbus->mdr = table[i];
+		lbc->mdr = table[i];
 		__asm__ __volatile__ ("sync");
 		*dummy = 0;	/* Write the value to memory and increment MAD */
 		__asm__ __volatile__ ("sync");

arch/powerpc/cpu/mpc83xx/cpu_init.c +7 ~~-46~~

95 lines not on this page · raw message

arch/powerpc/cpu/mpc83xx/nand_init.c +2 -2

index 38e141a..d1648b7 100644
@@ -88,8 +88,8 @@ void cpu_init_f (volatile immap_t * im)
 	&& defined(CONFIG_SYS_NAND_OR_PRELIM) \
 	&& defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
 	&& defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
-	im->lbus.bank[0].br = CONFIG_SYS_NAND_BR_PRELIM;
-	im->lbus.bank[0].or = CONFIG_SYS_NAND_OR_PRELIM;
+	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
 	im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
 	im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
 #else

arch/powerpc/cpu/mpc83xx/speed.c +1 -1

index 500eef1..a42c495 100644
@@ -388,7 +388,7 @@ int get_clocks(void)
 
 	lbiu_clk = csb_clk *
 	           (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
-	lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
+	lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
 	switch (lcrr) {
 	case 2:
 	case 4:

arch/powerpc/cpu/mpc85xx/cpu.c +4 -8

index fddeb2f..4160b60 100644
@@ -257,8 +257,7 @@ void upmconfig (uint upm, uint * table, uint size)
 {
 	int i, mdr, mad, old_mad = 0;
 	volatile u32 *mxmr;
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
-	volatile u32 *brp,*orp;
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	volatile u8* dummy = NULL;
 	int upmmask;

@@ -281,12 +280,9 @@ void upmconfig (uint upm, uint * table, uint size)
 	}
 
 	/* Find the address for the dummy write transaction */
-	for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
-		 i++, brp += 2, orp += 2) {
-
-		/* Look for a valid BR with selected UPM */
-		if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
-			dummy = (volatile u8*)(in_be32(brp) & BR_BA);
+	for (i = 0; i < 8; i++) {
+		if ((get_lbc_br(i) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
+			dummy = (volatile u8 *)(get_lbc_br(i) & BR_BA);
 			break;
 		}
 	}

arch/powerpc/cpu/mpc85xx/cpu_init.c +2 ~~-56~~

76 lines not on this page · raw message

arch/powerpc/cpu/mpc85xx/cpu_init_nand.c +3 -3

index 184cca4..8fb27ab 100644
@@ -25,7 +25,7 @@
 
 void cpu_init_f(void)
 {
-	ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	/*
 	 * LCRR - Clock Ratio Register - set up local bus timing

@@ -34,8 +34,8 @@ void cpu_init_f(void)
 	out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
 
 #if defined(CONFIG_NAND_BR_PRELIM) && defined(CONFIG_NAND_OR_PRELIM)
-	out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM);
-	out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM);
+	set_lbc_br(0, CONFIG_NAND_BR_PRELIM);
+	set_lbc_or(0, CONFIG_NAND_OR_PRELIM);
 #else
 #error  CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined
 #endif

arch/powerpc/cpu/mpc85xx/speed.c +1 -4

index 8132115..dd4c6b3 100644
@@ -172,10 +172,7 @@ void get_sys_info (sys_info_t * sysInfo)
 	/* We will program LCRR to this value later */
 	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
 #else
-	{
-	    volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
-	    lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
-	}
+	lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
 #endif
 	if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
 #if defined(CONFIG_FSL_CORENET)

arch/powerpc/cpu/mpc86xx/cpu.c +1 ~~-14~~

index 1887575..0fe94a0 100644
@@ -180,22 +180,9 @@ watchdog_reset(void)
  */
 void mpc86xx_reginfo(void)
 {
-	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	ccsr_lbc_t *lbc = &immap->im_lbc;
-
 	print_bats();
 	print_laws();
-
-	printf ("Local Bus Controller Registers\n"
-		"\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0));
-	printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1));
-	printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2));
-	printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3));
-	printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4));
-	printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5));
-	printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6));
-	printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7));
-
+	print_lbc_regs();
 }
 
 /*

arch/powerpc/cpu/mpc86xx/cpu_init.c +1 ~~-54~~

68 lines not on this page · raw message

arch/powerpc/cpu/mpc86xx/speed.c +1 -4

index 64a3479..a2d0a8a 100644
@@ -97,10 +97,7 @@ void get_sys_info(sys_info_t *sysInfo)
 	/* We will program LCRR to this value later */
 	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
 #else
-	{
-		volatile ccsr_lbc_t *lbc = &immap->im_lbc;
-		lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
-	}
+	lcrr_div = in_be32(&immap->im_lbc.lcrr) & LCRR_CLKDIV;
 #endif
 	if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
 		sysInfo->freqLocalBus = sysInfo->freqSystemBus / (lcrr_div * 2);

arch/powerpc/cpu/mpc8xxx/Makefile +3 -0

index 481f9e5..34a5198 100644
@@ -10,9 +10,12 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib8xxx.a
 
+ifeq ($(CPU), $(filter $(CPU), mpc85xx mpc86xx))
 COBJS-y	+= cpu.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
 COBJS-$(CONFIG_PCI)	+= pci_cfg.o
+endif
+COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))

arch/powerpc/cpu/mpc8xxx/fsl_lbc.c new file +84 -0

84 lines not on this page · raw message

arch/powerpc/include/asm/config.h +6 -0

index fc3facb..01036f3 100644
@@ -76,4 +76,10 @@
 /* Relocation to SDRAM works on all PPC boards */
 #define CONFIG_RELOC_FIXUP_WORKS
 
+/* Most PPC SOCs have a LBC so define this here */
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
+	defined(CONFIG_MPC83xx)
+#define CONFIG_FSL_LBC
+#endif
+
 #endif /* _ASM_CONFIG_H_ */

arch/powerpc/include/asm/fsl_lbc.h +65 ~~-44~~

120 lines not on this page · raw message

arch/powerpc/include/asm/immap_83xx.h +7 -6

index 6b42a73..9353dc0 100644
@@ -635,7 +635,7 @@ typedef struct immap {
 	u8			res2[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res3[0x900];
-	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
 	u8			res4[0x1000];
 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
 	dma83xx_t		dma;		/* DMA */

@@ -675,7 +675,7 @@ typedef struct immap {
 	u8			res1[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res2[0x900];
-	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
 	u8			res3[0x1000];
 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
 	dma83xx_t		dma;		/* DMA */

@@ -710,7 +710,7 @@ typedef struct immap {
 	u8			res1[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res2[0x900];
-	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
 	u8			res3[0x1000];
 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
 	dma83xx_t		dma;		/* DMA */

@@ -755,7 +755,7 @@ typedef struct immap {
 	u8			res1[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res2[0x900];
-	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
 	u8			res3[0x1000];
 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
 	dma83xx_t		dma;		/* DMA */

@@ -805,7 +805,7 @@ typedef struct immap {
 	u8			res4[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res5[0x900];
-	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
 	u8			res6[0x2000];
 	dma83xx_t		dma;		/* DMA */
 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */

@@ -844,7 +844,7 @@ typedef struct immap {
 	u8			res3[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res4[0x900];
-	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
 	u8			res5[0x2000];
 	dma83xx_t		dma;		/* DMA */
 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */

@@ -868,6 +868,7 @@ typedef struct immap {
 #endif
 #define CONFIG_SYS_MPC83xx_USB_ADDR \
 			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
+#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
 
 #define CONFIG_SYS_TSEC1_OFFSET		0x24000
 #define CONFIG_SYS_MDIO1_OFFSET		0x24000

arch/powerpc/include/asm/immap_85xx.h +1 ~~-45~~

58 lines not on this page · raw message

arch/powerpc/include/asm/immap_86xx.h +3 ~~-46~~

73 lines not on this page · raw message

board/atum8548/atum8548.c +1 -1

index c11a5c3..4f7d935 100644
@@ -47,7 +47,7 @@ int board_early_init_f (void)
 int checkboard (void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 
 	if ((uint)&gur->porpllsr != 0xe00e0000) {

board/esd/vme8349/vme8349.c +1 -1

index b0ebad7..96698e7 100644
@@ -105,7 +105,7 @@ int misc_init_r()
 {
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 
-	clrsetbits_be32(&im->lbus.lcrr, LBCR_LDIS, 0);
+	clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0);
 
 	return 0;
 }

board/freescale/mpc8313erdb/sdram.c +1 -1

index 0c4fd68..7aede13 100644
@@ -110,7 +110,7 @@ static long fixed_sdram(void)
 phys_size_t initdram(int board_type)
 {
 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile fsl_lbus_t *lbc = &im->lbus;
+	volatile fsl_lbc_t *lbc = &im->im_lbc;
 	u32 msize;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)

board/freescale/mpc8349emds/mpc8349emds.c +1 -1

index 61d1249..365ac37 100644
@@ -192,7 +192,7 @@ int checkboard (void)
 void sdram_init(void)
 {
 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile fsl_lbus_t *lbc = &immap->lbus;
+	volatile fsl_lbc_t *lbc = &immap->im_lbc;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 
 	/*

board/freescale/mpc8349itx/mpc8349itx.c +3 -4

index 7da39f1..5647579 100644
@@ -221,15 +221,14 @@ int misc_init_f(void)
 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
 	};
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile fsl_lbus_t *lbus = &immap->lbus;
 
-	lbus->bank[3].br = CONFIG_SYS_BR3_PRELIM;
-	lbus->bank[3].or = CONFIG_SYS_OR3_PRELIM;
+	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
+	set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
 
 	/* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
 	   GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
 	 */
-	lbus->mamr = 0x08404440;
+	immap->im_lbc.mamr = 0x08404440;
 
 	upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));

board/freescale/mpc8360emds/mpc8360emds.c +3 -3

index 4f55732..59ada9c 100644
@@ -280,7 +280,7 @@ int checkboard(void)
 static int sdram_init(unsigned int base)
 {
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile fsl_lbus_t *lbc = &immap->lbus;
+	fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
 	int rem = base % sdram_size;
 	uint *sdram_addr;

@@ -293,8 +293,8 @@ static int sdram_init(unsigned int base)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	immap->lbus.bank[2].br = base | CONFIG_SYS_BR2;
-	immap->lbus.bank[2].or = CONFIG_SYS_OR2;
+	set_lbc_br(2, base | CONFIG_SYS_BR2);
+	set_lbc_or(2, CONFIG_SYS_OR2);
 	immap->sysconf.lblaw[2].bar = base;
 	immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;

board/freescale/mpc8360erdk/nand.c +3 -3

index 9ffffb4..92d56a3 100644
@@ -82,9 +82,9 @@ static struct fsl_upm_nand fun = {
 
 int board_nand_init(struct nand_chip *nand)
 {
-	fun.upm.mxmr = &im->lbus.mamr;
-	fun.upm.mdr = &im->lbus.mdr;
-	fun.upm.mar = &im->lbus.mar;
+	fun.upm.mxmr = &im->im_lbc.mamr;
+	fun.upm.mdr = &im->im_lbc.mdr;
+	fun.upm.mar = &im->im_lbc.mar;
 
 	upm_setup(&fun.upm);

board/freescale/mpc8540ads/mpc8540ads.c +4 -4

index 9e3f677..f9ff827 100644
@@ -117,7 +117,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

@@ -176,7 +176,7 @@ local_bus_init(void)
 void
 sdram_init(void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 
 	puts("    SDRAM: ");

@@ -185,8 +185,8 @@ sdram_init(void)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
-	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	asm("msync");

board/freescale/mpc8541cds/mpc8541cds.c +4 -9

index c30d966..0580fe7 100644
@@ -291,7 +291,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

@@ -340,7 +340,7 @@ sdram_init(void)
 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 
 	uint idx;
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 	uint cpu_board_rev;
 	uint lsdmr_common;

@@ -352,16 +352,11 @@ sdram_init(void)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
-	asm("msync");
-
-	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
-	asm("msync");
-
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	asm("msync");
 
-
 	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 	asm("msync");

board/freescale/mpc8544ds/mpc8544ds.c +1 -1

index 0be2d89..581d5f2 100644
@@ -40,7 +40,7 @@
 int checkboard (void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 	u8 vboot;
 	u8 *pixis_base = (u8 *)PIXIS_BASE;

board/freescale/mpc8548cds/mpc8548cds.c +4 -9

index aa3f32b..f016995 100644
@@ -118,7 +118,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

@@ -154,7 +154,7 @@ sdram_init(void)
 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 
 	uint idx;
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 	uint cpu_board_rev;
 	uint lsdmr_common;

@@ -166,16 +166,11 @@ sdram_init(void)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
-	asm("msync");
-
-	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
-	asm("msync");
-
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	asm("msync");
 
-
 	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 	asm("msync");

board/freescale/mpc8555cds/mpc8555cds.c +4 -8

index ecddd0d..b7e0e0c 100644
@@ -291,7 +291,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

@@ -340,7 +340,7 @@ sdram_init(void)
 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 
 	uint idx;
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 	uint cpu_board_rev;
 	uint lsdmr_common;

@@ -352,12 +352,8 @@ sdram_init(void)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
-	asm("msync");
-
-	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
-	asm("msync");
-
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	asm("msync");

board/freescale/mpc8560ads/mpc8560ads.c +4 -4

index 2bca0f2..489f90b 100644
@@ -322,7 +322,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

@@ -381,7 +381,7 @@ local_bus_init(void)
 void
 sdram_init(void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 
 	puts("    SDRAM: ");

@@ -390,8 +390,8 @@ sdram_init(void)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
-	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	asm("msync");

board/freescale/mpc8568mds/mpc8568mds.c +4 -7

index 4ec13a9..036bf95 100644
@@ -181,7 +181,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

@@ -214,7 +214,7 @@ sdram_init(void)
 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 
 	uint idx;
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 	uint lsdmr_common;

@@ -225,16 +225,13 @@ sdram_init(void)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
-	asm("msync");
-
-	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	asm("msync");
 
 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	asm("msync");
 
-
 	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 	asm("msync");

board/freescale/mpc8569mds/mpc8569mds.c +1 -1

index 1eddeef..81e8ff5 100644
@@ -308,7 +308,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

board/mpc8540eval/mpc8540eval.c +3 -3

index 7c27233..054d644 100644
@@ -69,7 +69,7 @@ phys_size_t initdram (int board_type)
 	long dram_size = 0;
 
 #if !defined(CONFIG_RAM_AS_FLASH)
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	sys_info_t sysinfo;
 	uint temp_lbcdll = 0;
 #endif

@@ -110,8 +110,8 @@ phys_size_t initdram (int board_type)
 		gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
 		asm("sync;isync;msync");
 	}
-	lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
-	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
 	asm("sync");

board/pm854/pm854.c +1 -1

index 5353d73..a302b91 100644
@@ -134,7 +134,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

board/pm856/pm856.c +1 -1

index b14a3d3..f9d92d9 100644
@@ -290,7 +290,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

board/sbc8349/sbc8349.c +1 -1

index 34861d4..50fae7c 100644
@@ -160,7 +160,7 @@ int checkboard (void)
 void sdram_init(void)
 {
 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile fsl_lbus_t *lbc = &immap->lbus;
+	volatile fsl_lbc_t *lbc = &immap->im_lbc;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 
 	puts("\n   SDRAM on Local Bus: ");

board/sbc8548/sbc8548.c +6 ~~-14~~

index 194f6ab..d62cfd1 100644
@@ -116,7 +116,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

@@ -152,7 +152,7 @@ sdram_init(void)
 #if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
 
 	uint idx;
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 	uint lsdmr_common;

@@ -163,22 +163,14 @@ sdram_init(void)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
-	asm("msync");
-
-	out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
-	asm("msync");
-
-	out_be32(&lbc->or4, CONFIG_SYS_OR4_PRELIM);
-	asm("msync");
-
-	out_be32(&lbc->br4, CONFIG_SYS_BR4_PRELIM);
-	asm("msync");
+	set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
+	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
+	set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
+	set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
 
 	out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
 	asm("msync");
 
-
 	out_be32(&lbc->lsrt,  CONFIG_SYS_LBC_LSRT);
 	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
 	asm("msync");

board/sbc8560/sbc8560.c +3 -3

index c40b5e3..10ba62f 100644
@@ -269,7 +269,7 @@ phys_size_t initdram (int board_type)
 
 #if 0
 #if !defined(CONFIG_RAM_AS_FLASH)
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	sys_info_t sysinfo;
 	uint temp_lbcdll = 0;
 #endif

@@ -310,8 +310,8 @@ phys_size_t initdram (int board_type)
 		gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
 		asm("sync;isync;msync");
 	}
-	lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
-	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
 	asm("sync");

board/sheldon/simpc8313/sdram.c +1 -1

index ebb70a2..ba59943 100644
@@ -129,7 +129,7 @@ void si_read_i2c(u32 lbyte, int count, u8 *buffer)
 phys_size_t initdram(int board_type)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile fsl_lbus_t *lbc= &im->lbus;
+	volatile fsl_lbc_t *lbc = &im->im_lbc;
 	u32 msize;
 
 	if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im)

board/sheldon/simpc8313/simpc8313.c +1 -1

index cb30b48..c2164c9 100644
@@ -93,7 +93,7 @@ int misc_init_r(void)
 {
 	int rc = 0;
 	immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	fsl_lbus_t *lbus = &immap->lbus;
+	fsl_lbc_t *lbus = &immap->im_lbc;
 	u32 *mxmr = &lbus->mamr;	/* Pointer to mamr */
 
 	/* UPM Table Configuration Code */

board/socrates/socrates.c +15 ~~-16~~

index 9183c15..72e7401 100644
@@ -87,8 +87,6 @@ int checkboard (void)
 
 int misc_init_r (void)
 {
-	volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
-
 	/*
 	 * Adjust flash start and offset to detected values
 	 */

@@ -99,8 +97,10 @@ int misc_init_r (void)
 	 * Check if boot FLASH isn't max size
 	 */
 	if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
-		memctl->or0 = gd->bd->bi_flashstart | (CONFIG_SYS_OR0_PRELIM & 0x00007fff);
-		memctl->br0 = gd->bd->bi_flashstart | (CONFIG_SYS_BR0_PRELIM & 0x00007fff);
+		set_lbc_or(0, gd->bd->bi_flashstart |
+			   (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
+		set_lbc_br(0, gd->bd->bi_flashstart |
+			   (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
 
 		/*
 		 * Re-check to get correct base address

@@ -112,8 +112,8 @@ int misc_init_r (void)
 	 * Check if only one FLASH bank is available
 	 */
 	if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
-		memctl->or1 = 0;
-		memctl->br1 = 0;
+		set_lbc_or(1, 0);
+		set_lbc_br(1, 0);
 
 		/*
 		 * Re-do flash protection upon new addresses

@@ -148,7 +148,7 @@ int misc_init_r (void)
  */
 void local_bus_init (void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 	sys_info_t sysinfo;
 	uint clkdiv;

@@ -299,26 +299,25 @@ const gdc_regs *board_get_regs (void)
 
 int lime_probe(void)
 {
-	volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 	uint cfg_br2;
 	uint cfg_or2;
 	int type;
 
-	cfg_br2 = memctl->br2;
-	cfg_or2 = memctl->or2;
+	cfg_br2 = get_lbc_br(2);
+	cfg_or2 = get_lbc_or(2);
 
 	/* Configure GPCM for CS2 */
-	memctl->br2 = 0;
-	memctl->or2 = 0xfc000410;
-	memctl->br2 = (CONFIG_SYS_LIME_BASE) | 0x00001901;
+	set_lbc_br(2, 0);
+	set_lbc_or(2, 0xfc000410);
+	set_lbc_br(2, (CONFIG_SYS_LIME_BASE) | 0x00001901);
 
 	/* Get controller type */
 	type = mb862xx_probe(CONFIG_SYS_LIME_BASE);
 
 	/* Restore previous CS2 configuration */
-	memctl->br2 = 0;
-	memctl->or2 = cfg_or2;
-	memctl->br2 = cfg_br2;
+	set_lbc_br(2, 0);
+	set_lbc_or(2, cfg_or2);
+	set_lbc_br(2, cfg_br2);
 
 	return (type == MB862XX_TYPE_LIME) ? 1 : 0;
 }

board/tqc/tqm834x/tqm834x.c +4 -4

index e564879..8d046f4 100644
@@ -253,10 +253,10 @@ static int detect_num_flash_banks(void)
 	debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks);
 
 	/* set OR0 and BR0 */
-	im->lbus.bank[0].or = CONFIG_SYS_OR_TIMING_FLASH |
-		(-(total_size) & OR_GPCM_AM);
-	im->lbus.bank[0].br = (CONFIG_SYS_FLASH_BASE & BR_BA) |
-		(BR_MS_GPCM | BR_PS_32 | BR_V);
+	set_lbc_or(0, CONFIG_SYS_OR_TIMING_FLASH |
+		   (-(total_size) & OR_GPCM_AM));
+	set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) |
+		   (BR_MS_GPCM | BR_PS_32 | BR_V));
 
 	return (0);
 }

board/tqc/tqm85xx/nand.c +6 -6

index 3da689a..4b16c31 100644
@@ -377,7 +377,7 @@ volatile const u32 *nand_upm_patt;
  */
 static void upmb_write (u_char addr, ulong val)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	out_be32 (&lbc->mdr, val);

@@ -393,14 +393,14 @@ static void upmb_write (u_char addr, ulong val)
 /*
  * Initialize UPM for NAND flash access.
  */
-static void nand_upm_setup (volatile ccsr_lbc_t *lbc)
+static void nand_upm_setup (volatile fsl_lbc_t *lbc)
 {
 	uint i, j;
 	uint or3 = CONFIG_SYS_OR3_PRELIM;
 	uint clock = get_lbc_clock ();
 
-	out_be32 (&lbc->br3, 0);	/* disable bank and reset all bits */
-	out_be32 (&lbc->br3, CONFIG_SYS_BR3_PRELIM);
+	set_lbc_br(3, 0);	/* disable bank and reset all bits */
+	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
 
 	/*
 	 * Search appropriate UPM table for bus clock.

@@ -424,7 +424,7 @@ static void nand_upm_setup (volatile ccsr_lbc_t *lbc)
 		/* EAD must be set due to TQM8548 timing specification */
 		or3 |= OR_UPM_EAD;
 
-	out_be32 (&lbc->or3, or3);
+	set_lbc_or(3, or3);
 
 	/* Assign address of table */
 	nand_upm_patt = upm_freq_table[i].upm_patt;

@@ -458,7 +458,7 @@ void board_nand_select_device (struct nand_chip *nand, int chip)
 
 int board_nand_init (struct nand_chip *nand)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	if (!nand_upm_patt)
 		nand_upm_setup (lbc);

board/tqc/tqm85xx/tqm85xx.c +17 ~~-18~~

index 8c9d586..fc2a6cb 100644
@@ -269,8 +269,6 @@ int checkboard (void)
 
 int misc_init_r (void)
 {
-	volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
-
 	/*
 	 * Adjust flash start and offset to detected values
 	 */

@@ -281,26 +279,27 @@ int misc_init_r (void)
 	 * Recalculate CS configuration if second FLASH bank is available
 	 */
 	if (flash_info[0].size > 0) {
-		memctl->or1 = ((-flash_info[0].size) & 0xffff8000) |
-			(CONFIG_SYS_OR1_PRELIM & 0x00007fff);
-		memctl->br1 = gd->bd->bi_flashstart |
-			(CONFIG_SYS_BR1_PRELIM & 0x00007fff);
+		set_lbc_or(1, ((-flash_info[0].size) & 0xffff8000) |
+			   (CONFIG_SYS_OR1_PRELIM & 0x00007fff));
+		set_lbc_br(1, gd->bd->bi_flashstart |
+			   (CONFIG_SYS_BR1_PRELIM & 0x00007fff));
 		/*
 		 * Re-check to get correct base address for bank 1
 		 */
 		flash_get_size (gd->bd->bi_flashstart, 0);
 	} else {
-		memctl->or1 = 0;
-		memctl->br1 = 0;
+		set_lbc_or(1, 0);
+		set_lbc_br(1, 0);
 	}
 
 	/*
 	 *  If bank 1 is equipped, bank 0 is mapped after bank 1
 	 */
-	memctl->or0 = ((-flash_info[1].size) & 0xffff8000) |
-		(CONFIG_SYS_OR0_PRELIM & 0x00007fff);
-	memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) |
-		(CONFIG_SYS_BR0_PRELIM & 0x00007fff);
+	set_lbc_or(0, ((-flash_info[1].size) & 0xffff8000) |
+		   (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
+	set_lbc_br(0, gd->bd->bi_flashstart |
+		   (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
+
 	/*
 	 * Re-check to get correct base address for bank 0
 	 */

@@ -341,7 +340,7 @@ int misc_init_r (void)
  */
 static void upmc_write (u_char addr, uint val)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	out_be32 (&lbc->mdr, val);

@@ -358,7 +357,7 @@ static void upmc_write (u_char addr, uint val)
 
 uint get_lbc_clock (void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	sys_info_t sys_info;
 	ulong clkdiv = lbc->lcrr & LCRR_CLKDIV;

@@ -386,7 +385,7 @@ uint get_lbc_clock (void)
 void local_bus_init (void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint lbc_mhz = get_lbc_clock ()  / 1000000;
 
 #ifdef CONFIG_MPC8548

@@ -502,10 +501,10 @@ void local_bus_init (void)
 	 * set if Local Bus Clock is > 83 MHz.
 	 */
 	if (lbc_mhz > 83)
-		out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
+		set_lbc_or(2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
 	else
-		out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN);
-	out_be32 (&lbc->br2, CONFIG_SYS_BR2_CAN);
+		set_lbc_or(2, CONFIG_SYS_OR2_CAN);
+	set_lbc_br(2, CONFIG_SYS_BR2_CAN);
 
 	/* LGPL4 is UPWAIT */
 	out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);

board/xes/xpedite5170/xpedite5170.c +4 -6

index f4231a9..5822941 100644
@@ -56,8 +56,6 @@ int checkboard(void)
  */
 static void flash_cs_fixup(void)
 {
-	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	ccsr_lbc_t *lbc = &immap->im_lbc;
 	int flash_sel;
 
 	/*

@@ -70,11 +68,11 @@ static void flash_cs_fixup(void)
 	printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
 
 	if (flash_sel) {
-		out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM);
-		out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM);
+		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
 
-		out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM);
-		out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM);
+		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
 	}
 }

board/xes/xpedite5200/xpedite5200.c +5 -6

index 7109771..a2627f8 100644
@@ -38,7 +38,7 @@ extern void ft_board_pci_setup(void *blob, bd_t *bd);
 
 int checkboard(void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 	char *s;

@@ -65,7 +65,6 @@ int checkboard(void)
 
 static void flash_cs_fixup(void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 	int flash_sel;
 
 	/*

@@ -78,11 +77,11 @@ static void flash_cs_fixup(void)
 	printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
 
 	if (flash_sel) {
-		out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM);
-		out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM);
+		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
 
-		out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM);
-		out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM);
+		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
 	}
 }

board/xes/xpedite5370/xpedite5370.c +4 -5

index 48d9fc8..2a060c2 100644
@@ -58,7 +58,6 @@ int checkboard(void)
 
 static void flash_cs_fixup(void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 	int flash_sel;
 
 	/*

@@ -71,11 +70,11 @@ static void flash_cs_fixup(void)
 	printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
 
 	if (flash_sel) {
-		out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM);
-		out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM);
+		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
 
-		out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM);
-		out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM);
+		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
 	}
 }

drivers/mtd/nand/fsl_elbc_nand.c +7 ~~-11~~

index 146e9bf..acdb431 100644
@@ -75,7 +75,7 @@ struct fsl_elbc_ctrl {
 	struct fsl_elbc_mtd *chips[MAX_BANKS];
 
 	/* device info */
-	fsl_lbus_t *regs;
+	fsl_lbc_t *regs;
 	u8 __iomem *addr;        /* Address of assigned FCM buffer        */
 	unsigned int page;       /* Last page written to / read from      */
 	unsigned int read_bytes; /* Number of bytes read during command   */

@@ -171,7 +171,7 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	fsl_lbus_t *lbc = ctrl->regs;
+	fsl_lbc_t *lbc = ctrl->regs;
 	int buf_num;
 
 	ctrl->page = page_addr;

@@ -211,7 +211,7 @@ static int fsl_elbc_run_command(struct mtd_info *mtd)
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	fsl_lbus_t *lbc = ctrl->regs;
+	fsl_lbc_t *lbc = ctrl->regs;
 	long long end_tick;
 	u32 ltesr;

@@ -261,7 +261,7 @@ static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 {
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	fsl_lbus_t *lbc = ctrl->regs;
+	fsl_lbc_t *lbc = ctrl->regs;
 
 	if (priv->page_size) {
 		out_be32(&lbc->fir,

@@ -295,7 +295,7 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	fsl_lbus_t *lbc = ctrl->regs;
+	fsl_lbc_t *lbc = ctrl->regs;
 
 	ctrl->use_mdr = 0;

@@ -633,7 +633,7 @@ static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 {
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	fsl_lbus_t *lbc = ctrl->regs;
+	fsl_lbc_t *lbc = ctrl->regs;
 
 	if (ctrl->status != LTESR_CC)
 		return NAND_STATUS_FAIL;

@@ -697,11 +697,7 @@ static void fsl_elbc_ctrl_init(void)
 	if (!elbc_ctrl)
 		return;
 
-#ifdef CONFIG_MPC85xx
-	elbc_ctrl->regs = (void *)CONFIG_SYS_MPC85xx_LBC_ADDR;
-#else
-	elbc_ctrl->regs = &((immap_t *)CONFIG_SYS_IMMR)->lbus;
-#endif
+	elbc_ctrl->regs = LBC_BASE_ADDR;
 
 	/* clear event registers */
 	out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);

include/mpc85xx.h +0 -2

index a4d4d65..2495b99 100644
@@ -6,8 +6,6 @@
 #ifndef	__MPC85xx_H__
 #define __MPC85xx_H__
 
-#include <asm/fsl_lbc.h>
-
 /* define for common ppc_asm.tmpl */
 #define EXC_OFF_SYS_RESET	0x100	/* System reset */
 #define _START_OFFSET		0

nand_spl/board/freescale/mpc8536ds/nand_boot.c +2 -3

index af29dc2..5a0a0c7 100644
@@ -34,12 +34,11 @@ void board_init_f(ulong bootflag)
 	int px_spd;
 	u32 plat_ratio, bus_clk, sys_clk;
 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-	ccsr_lbc_t *lbc = (void *)CONFIG_SYS_MPC85xx_LBC_ADDR;
 
 #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
 	/* for FPGA */
-	out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
-	out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
+	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
+	set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
 #else
 #error CONFIG_SYS_BR3_PRELIM, CONFIG_SYS_OR3_PRELIM must be defined
 #endif

nand_spl/nand_boot_fsl_elbc.c +2 -2

index ff47d55..9547d44 100644
@@ -32,7 +32,7 @@
 
 static void nand_wait(void)
 {
-	fsl_lbus_t *regs = (fsl_lbus_t *)(CONFIG_SYS_IMMR + 0x5000);
+	fsl_lbc_t *regs = LBC_BASE_ADDR;
 
 	for (;;) {
 		uint32_t status = in_be32(&regs->ltesr);

@@ -49,7 +49,7 @@ static void nand_wait(void)
 
 static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
 {
-	fsl_lbus_t *regs = (fsl_lbus_t *)(CONFIG_SYS_IMMR + 0x5000);
+	fsl_lbc_t *regs = LBC_BASE_ADDR;
 	uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
 	int large = in_be32(&regs->bank[0].or) & OR_FCM_PGS;
 	int block_shift = large ? 17 : 14;

Signature · 1 line

1.6.0.6

Becky Bruce

author

2010-06-02 18:12 UTC #4 lore raw

PATCH v2 4/10 mpc85xx: tlb.c cleanups

Extract the operation to read a tlb into a function - we will need this later to print out the tlbs, and there's no point in duplicating the code. Create a TSIZE_TO_BYTES macro to deal with the conversion from the MAS field to an actual size instead of duplicating this in code. There are a few misc other minor cleanups.

Signed-off-by Becky Bruce <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/tlb.c |   50 +++++++++++++++++++--------------------
 arch/powerpc/include/asm/mmu.h |    1 +
 2 files changed, 25 insertions(+), 26 deletions(-)

arch/powerpc/cpu/mpc85xx/tlb.c +24 ~~-26~~

index b3037ac..eebb6ae 100644
@@ -55,6 +55,24 @@ void init_tlbs(void)
 	return ;
 }
 
+void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
+		       phys_addr_t *rpn)
+{
+	u32 _mas1;
+
+	mtspr(MAS0, FSL_BOOKE_MAS0(1, idx, 0));
+	asm volatile("tlbre;isync");
+	_mas1 = mfspr(MAS1);
+
+	*valid = (_mas1 & MAS1_VALID);
+	*tsize = (_mas1 >> 8) & 0xf;
+	*epn = mfspr(MAS2) & MAS2_EPN;
+	*rpn = mfspr(MAS3) & MAS3_RPN;
+#ifdef CONFIG_ENABLE_36BIT_PHYS
+	*rpn |= ((u64)mfspr(MAS7)) << 32;
+#endif
+}
+
 #ifndef CONFIG_NAND_SPL
 static inline void use_tlb_cam(u8 idx)
 {

@@ -82,15 +100,9 @@ void init_used_tlb_cams(void)
 
 	/* walk all the entries */
 	for (i = 0; i < num_cam; i++) {
-		u32 _mas1;
-
 		mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0));
-
 		asm volatile("tlbre;isync");
-		_mas1 = mfspr(MAS1);
-
-		/* if the entry isn't valid skip it */
-		if ((_mas1 & MAS1_VALID))
+		if (mfspr(MAS1) & MAS1_VALID)
 			use_tlb_cam(i);
 	}
 }

@@ -134,7 +146,7 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn,
 
 #ifdef CONFIG_ADDR_MAP
 	if ((tlb == 1) && (gd->flags & GD_FLG_RELOC))
-		addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), esel);
+		addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), esel);
 #endif
 }

@@ -201,26 +213,12 @@ void init_addr_map(void)
 	/* walk all the entries */
 	for (i = 0; i < num_cam; i++) {
 		unsigned long epn;
-		u32 tsize, _mas1;
+		u32 tsize, valid;
 		phys_addr_t rpn;
 
-		mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0));
-
-		asm volatile("tlbre;isync");
-		_mas1 = mfspr(MAS1);
-
-		/* if the entry isn't valid skip it */
-		if (!(_mas1 & MAS1_VALID))
-			continue;
-
-		tsize = (_mas1 >> 8) & 0xf;
-		epn = mfspr(MAS2) & MAS2_EPN;
-		rpn = mfspr(MAS3) & MAS3_RPN;
-#ifdef CONFIG_ENABLE_36BIT_PHYS
-		rpn |= ((phys_addr_t)mfspr(MAS7)) << 32;
-#endif
-
-		addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), i);
+		read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn);
+		if (valid & MAS1_VALID)
+			addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), i);
 	}
 
 	return ;

arch/powerpc/include/asm/mmu.h +1 -0

index 5166507..d4c7b75 100644
@@ -402,6 +402,7 @@ extern void print_bats(void);
 #define MAS1_TID(x)	((x << 16) & 0x3FFF0000)
 #define MAS1_TS		0x00001000
 #define MAS1_TSIZE(x)	((x << 8) & 0x00000F00)
+#define TSIZE_TO_BYTES(x) ((phys_addr_t)(1UL << ((tsize * 2) + 10)))
 
 #define MAS2_EPN	0xFFFFF000
 #define MAS2_X0		0x00000040

Signature · 1 line

1.6.0.6

Becky Bruce

author

2010-06-02 18:12 UTC #5 lore raw

PATCH v2 5/10 mpc85xx: Add print_tlbcam() function

This dumps out the contents of TLB1 on 85xx-based systems.

Signed-off-by Becky Bruce <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/tlb.c |   20 ++++++++++++++++++++
 arch/powerpc/include/asm/mmu.h |    1 +
 2 files changed, 21 insertions(+), 0 deletions(-)

arch/powerpc/cpu/mpc85xx/tlb.c +20 -0

index eebb6ae..f2833a5 100644
@@ -74,6 +74,26 @@ void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
 }
 
 #ifndef CONFIG_NAND_SPL
+void print_tlbcam(void)
+{
+	int i;
+	unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
+
+	/* walk all the entries */
+	printf("TLBCAM entries\n");
+	for (i = 0; i < num_cam; i++) {
+		unsigned long epn;
+		u32 tsize, valid;
+		phys_addr_t rpn;
+
+		read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn);
+		printf("entry %02d: V: %d EPN 0x%08x RPN 0x%08llx size:",
+			i, (valid == 0) ? 0 : 1, (unsigned int)epn,
+			(unsigned long long)rpn);
+		print_size(TSIZE_TO_BYTES(tsize), "\n");
+	}
+}
+
 static inline void use_tlb_cam(u8 idx)
 {
 	int i = idx / 32;

arch/powerpc/include/asm/mmu.h +1 -0

index d4c7b75..c01c85f 100644
@@ -486,6 +486,7 @@ extern void init_tlbs(void);
 extern int find_tlb_idx(void *addr, u8 tlbsel);
 extern void init_used_tlb_cams(void);
 extern int find_free_tlbcam(void);
+extern void print_tlbcam(void);
 
 extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);

Signature · 1 line

1.6.0.6

Becky Bruce

author

2010-06-02 18:12 UTC #6 lore raw

PATCH v2 6/10 drivers/misc/fsl_law.c: Rearrange code to avoid duplication

The current code redefines functions based on FSL_CORENET_ vs not - create macros/inlines instead that hide the differences.

Signed-off-by Becky Bruce <[email protected]>

---
 arch/powerpc/include/asm/fsl_law.h |    1 +
 drivers/misc/fsl_law.c             |  125 ++++++++++++++----------------------
 2 files changed, 49 insertions(+), 77 deletions(-)

arch/powerpc/include/asm/fsl_law.h +1 -0

index 34c56a2..12ba1a6 100644
@@ -47,6 +47,7 @@ enum law_size {
 };
 
 #define law_size_bits(sz)	(__ilog2_u64(sz) - 1)
+#define lawar_size(x)	(1ULL << ((x & 0x3f) + 1))
 
 #ifdef CONFIG_FSL_CORENET
 enum law_trgt_if {

drivers/misc/fsl_law.c +48 ~~-77~~

175 lines not on this page · raw message

Signature · 1 line

1.6.0.6

Becky Bruce

author

2010-06-02 18:12 UTC #7 lore raw

PATCH v2 7/10 fsl_law.c: Add print_laws() for FSL_CORENET platforms.

Add printing of LAWBARH/LAWBARL for FSL_CORENET platforms.

Signed-off-by Becky Bruce <[email protected]>

---
 drivers/misc/fsl_law.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

drivers/misc/fsl_law.c +6 -0

index 9688888..628bd59 100644
@@ -193,7 +193,13 @@ void print_laws(void)
 	printf("\nLocal Access Window Configuration\n");
 	for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
 		lawar = in_be32(LAWAR_ADDR(i));
+#ifdef CONFIG_FSL_CORENET
+		printf("LAWBARH%02d: 0x%08x LAWBARL%02d: 0x%08x",
+		       i, in_be32(LAWBARH_ADDR(i)),
+		       i, in_be32(LAWBARL_ADDR(i)));
+#else
 		printf("LAWBAR%02d: 0x%08x", i, in_be32(LAWBAR_ADDR(i)));
+#endif
 		printf(" LAWAR0x%02d: 0x%08x\n", i, lawar);
 		printf("\t(EN: %d TGT: 0x%02x SIZE: ",
 		       (lawar & LAW_EN) ? 1 : 0, (lawar >> 20) & 0xff);

Signature · 1 line

1.6.0.6

Becky Bruce

author

2010-06-02 18:12 UTC #8 lore raw

PATCH v2 8/10 mpc85xx: Add reginfo command

The new command dumps the TLBCAM, the LAWs, and the BR/OR regs. Add CONFIG_CMD_REGINFO to the config for all MPC85xx parts.

Signed-off-by Becky Bruce <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/cpu.c |   13 +++++++++++++
 common/cmd_reginfo.c           |    5 +++++
 include/configs/MPC8536DS.h    |    1 +
 include/configs/MPC8540EVAL.h  |    1 +
 include/configs/MPC8541CDS.h   |    1 +
 include/configs/MPC8544DS.h    |    1 +
 include/configs/MPC8548CDS.h   |    1 +
 include/configs/MPC8555CDS.h   |    1 +
 include/configs/MPC8560ADS.h   |    1 +
 include/configs/MPC8568MDS.h   |    1 +
 include/configs/MPC8569MDS.h   |    1 +
 include/configs/MPC8572DS.h    |    1 +
 include/configs/P1_P2_RDB.h    |    1 +
 include/configs/P2020DS.h      |    1 +
 include/configs/PM854.h        |    1 +
 include/configs/PM856.h        |    1 +
 include/configs/SBC8540.h      |    1 +
 include/configs/TQM85xx.h      |    1 +
 include/configs/XPEDITE5200.h  |    1 +
 include/configs/XPEDITE5370.h  |    1 +
 include/configs/sbc8548.h      |    1 +
 include/configs/sbc8560.h      |    1 +
 include/configs/socrates.h     |    1 +
 include/configs/stxgp3.h       |    1 +
 include/configs/stxssa.h       |    1 +
 25 files changed, 41 insertions(+), 0 deletions(-)

arch/powerpc/cpu/mpc85xx/cpu.c +13 -0

index 4160b60..7ab4a2a 100644
@@ -32,6 +32,8 @@
 #include <fsl_esdhc.h>
 #include <asm/cache.h>
 #include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/fsl_law.h>
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -322,3 +324,14 @@ int cpu_mmc_init(bd_t *bis)
 	return 0;
 #endif
 }
+
+/*
+ * Print out the state of various machine registers.
+ * Currently prints out LAWs, BR0/OR0, and TLBs
+ */
+void mpc85xx_reginfo(void)
+{
+	print_tlbcam();
+	print_laws();
+	print_lbc_regs();
+}

common/cmd_reginfo.c +5 -0

index 89fd9ec..0fbe0b2 100644
@@ -33,6 +33,8 @@ extern void ppc4xx_reginfo(void);
 #include <mpc5xxx.h>
 #elif defined (CONFIG_MPC86xx)
 extern void mpc86xx_reginfo(void);
+#elif defined(CONFIG_MPC85xx)
+extern void mpc85xx_reginfo(void);
 #endif
 
 int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])

@@ -183,6 +185,9 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #elif defined(CONFIG_MPC86xx)
 	mpc86xx_reginfo();
 
+#elif defined(CONFIG_MPC85xx)
+	mpc85xx_reginfo();
+
 #elif defined(CONFIG_BLACKFIN)
 	puts("\nSystem Configuration registers\n");

include/configs/MPC8536DS.h +1 -0

index da4313a..9c46d3e 100644
@@ -669,6 +669,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI

include/configs/MPC8540EVAL.h +1 -0

index 95ea275..7daf934 100644
@@ -294,6 +294,7 @@
 
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_I2C
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

include/configs/MPC8541CDS.h +1 -0

index e945da2..ae4fba8 100644
@@ -403,6 +403,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

include/configs/MPC8544DS.h +1 -0

index 799d946..faba353 100644
@@ -420,6 +420,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

include/configs/MPC8548CDS.h +1 -0

index 3eb0049..fdd3597 100644
@@ -462,6 +462,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

include/configs/MPC8555CDS.h +1 -0

index 07a8e61..5011e5a 100644
@@ -401,6 +401,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

include/configs/MPC8560ADS.h +1 -0

index 4a4a9ed..98677e5 100644
@@ -416,6 +416,7 @@
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

include/configs/MPC8568MDS.h +1 -0

index 6973538..0cc2d47 100644
@@ -421,6 +421,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

include/configs/MPC8569MDS.h +1 -0

index 0c43b2b..bb7bb47 100644
@@ -539,6 +539,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

include/configs/MPC8572DS.h +1 -0

index 78b7369..6038de1 100644
@@ -574,6 +574,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI

include/configs/P1_P2_RDB.h +1 -0

index a9b4004..926c774 100644
@@ -466,6 +466,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_NET

include/configs/P2020DS.h +1 -0

index 66be725..9bed161 100644
@@ -553,6 +553,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI

include/configs/PM854.h +1 -0

index 4b9bcca..7426bca 100644
@@ -326,6 +326,7 @@
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

include/configs/PM856.h +1 -0

index 1db20bc..0bd28fc 100644
@@ -325,6 +325,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

include/configs/SBC8540.h +1 -0

index 1989e5a..5d424dd 100644
@@ -380,6 +380,7 @@
 
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_I2C
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

include/configs/TQM85xx.h +1 -0

index d44fb07..90abe14 100644
@@ -593,6 +593,7 @@
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_MII
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI

include/configs/XPEDITE5200.h +1 -0

index 1a56c60..df5ef78 100644
@@ -338,6 +338,7 @@
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SNTP
+#define CONFIG_CMD_REGINFO
 
 /*
  * Miscellaneous configurable options

include/configs/XPEDITE5370.h +1 -0

index 20a6753..1d6091c 100644
@@ -397,6 +397,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_SNTP
+#define CONFIG_CMD_REGINFO
 
 /*
  * Miscellaneous configurable options

include/configs/sbc8548.h +1 -0

index aeac2de..3f4056e 100644
@@ -487,6 +487,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_ELF
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

include/configs/sbc8560.h +1 -0

index dab4f80..53d06ed 100644
@@ -382,6 +382,7 @@
 
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_I2C
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

include/configs/socrates.h +1 -0

index 89f7cc4..ad70109 100644
@@ -355,6 +355,7 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SNTP
 #define CONFIG_CMD_USB
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

include/configs/stxgp3.h +1 -0

index 86b231c..891d2bf 100644
@@ -321,6 +321,7 @@
 
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_I2C
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_SYS_RAMBOOT)
     #undef CONFIG_CMD_SAVEENV

include/configs/stxssa.h +1 -0

index 2783f9e..363f7b4 100644
@@ -353,6 +353,7 @@
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SNTP
+#define CONFIG_CMD_REGINFO
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI

Signature · 1 line

1.6.0.6

Becky Bruce

author

2010-06-02 18:12 UTC #9 lore raw

PATCH v2 9/10 powerpc 83xx/85xx: Merge lbc upmconfig code

Each platform had its own version of the upmconfig, despite the init process being identical. Now that we have a spot for common lbc code, create a common upmconfig() there.

Signed-off-by Becky Bruce <[email protected]>

---
 arch/powerpc/cpu/mpc83xx/cpu.c     |   66 ------------------------------------
 arch/powerpc/cpu/mpc85xx/cpu.c     |   61 ---------------------------------
 arch/powerpc/cpu/mpc8xxx/fsl_lbc.c |   51 +++++++++++++++++++++++++++
 arch/powerpc/include/asm/fsl_lbc.h |    3 ++
 4 files changed, 54 insertions(+), 127 deletions(-)

arch/powerpc/cpu/mpc83xx/cpu.c +0 ~~-66~~

index 24193ce..d37fc80 100644
@@ -125,72 +125,6 @@ int checkcpu(void)
 	return 0;
 }
 
-
-/*
- * Program a UPM with the code supplied in the table.
- *
- * The 'dummy' variable is used to increment the MAD. 'dummy' is
- * supposed to be a pointer to the memory of the device being
- * programmed by the UPM.  The data in the MDR is written into
- * memory and the MAD is incremented every time there's a write
- * to 'dummy'. Unfortunately, the current prototype for this
- * function doesn't allow for passing the address of this
- * device, and changing the prototype will break a number lots
- * of other code, so we need to use a round-about way of finding
- * the value for 'dummy'.
- *
- * The value can be extracted from the base address bits of the
- * Base Register (BR) associated with the specific UPM.  To find
- * that BR, we need to scan all 8 BRs until we find the one that
- * has its MSEL bits matching the UPM we want.  Once we know the
- * right BR, we can extract the base address bits from it.
- *
- * The MxMR and the BR and OR of the chosen bank should all be
- * configured before calling this function.
- *
- * Parameters:
- * upm: 0=UPMA, 1=UPMB, 2=UPMC
- * table: Pointer to an array of values to program
- * size: Number of elements in the array.  Must be 64 or less.
- */
-void upmconfig (uint upm, uint *table, uint size)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile fsl_lbc_t *lbc = &immap->im_lbc;
-	volatile uchar *dummy = NULL;
-	const u32 msel = (upm + 4) << BR_MSEL_SHIFT;	/* What the MSEL field in BRn should be */
-	volatile u32 *mxmr = &lbc->mamr + upm;	/* ptr to mamr, mbmr, or mcmr */
-	uint i;
-
-	/* Find the address for the dummy write transaction */
-	for (i = 0; i < 8; i++) {
-		if ((get_lbc_br(i) & BR_MSEL) == msel) {
-			dummy = (uchar *) (get_lbc_br(i) & BR_BA);
-			break;
-		}
-	}
-
-	if (!dummy) {
-		printf("Error: %s() could not find matching BR\n", __FUNCTION__);
-		hang();
-	}
-
-	/* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
-	*mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
-
-	for (i = 0; i < size; i++) {
-		lbc->mdr = table[i];
-		__asm__ __volatile__ ("sync");
-		*dummy = 0;	/* Write the value to memory and increment MAD */
-		__asm__ __volatile__ ("sync");
-		while(((*mxmr & 0x3f) != ((i + 1) & 0x3f)));
-	}
-
-	/* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
-	*mxmr &= 0xCFFFFFC0;
-}
-
-
 int
 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {

arch/powerpc/cpu/mpc85xx/cpu.c +0 ~~-61~~

67 lines not on this page · raw message

arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +51 -0

54 lines not on this page · raw message

arch/powerpc/include/asm/fsl_lbc.h +3 -0

index 33e6dd9..82d24ab 100644
@@ -62,6 +62,8 @@
 #define BR_V				0x00000001
 #define BR_V_SHIFT			0
 
+#define BR_UPMx_TO_MSEL(x)		((x + 4) << BR_MSEL_SHIFT)
+
 #define UPMA			0
 #define UPMB			1
 #define UPMC			2

@@ -458,6 +460,7 @@
 
 extern void print_lbc_regs(void);
 extern void init_early_memctl_regs(void);
+extern void upmconfig(uint upm, uint *table, uint size);
 
 #define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR)
 #define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br))

Signature · 1 line

1.6.0.6

Becky Bruce

author

2010-06-02 18:12 UTC #10 lore raw

PATCH v2 10/10 MAKEALL: Add missing powerpc 36-bit targets

We were missing 8641HPCN_36BIT and MPC8536DS_36BIT.

Signed-off-by Becky Bruce <[email protected]>

---
 MAKEALL |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

MAKEALL +2 -0

index 2527352..a82c93c 100755
@@ -393,6 +393,7 @@ LIST_85xx="		\
 	MPC8536DS_NAND	\
 	MPC8536DS_SDCARD	\
 	MPC8536DS_SPIFLASH	\
+	MPC8536DS_36BIT	\
 	MPC8540ADS	\
 	MPC8540EVAL	\
 	MPC8541CDS	\

@@ -453,6 +454,7 @@ LIST_85xx="		\
 
 LIST_86xx="		\
 	MPC8610HPCD	\
+	MPC8641HPCN_36BIT \
 	MPC8641HPCN	\
 	sbc8641d	\
 	XPEDITE5170	\

Signature · 1 line

1.6.0.6

Scott Wood

2010-06-02 19:21 UTC #11 lore raw

PATCH v2 10/10 MAKEALL: Add missing powerpc 36-bit targets

Quoted 12 lines · Becky Bruce

We were missing 8641HPCN_36BIT and MPC8536DS_36BIT.
Signed-off-by Becky Bruce<[email protected]>
---
  MAKEALL |    2 ++
  1 files changed, 2 insertions(+), 0 deletions(-)
MAKEALL +0 -0
index 2527352..a82c93c 100755

MAKEALL LIST_85xx=" \ · line 399

Quoted 7 lines

MAKEALL +1 -0

@@ -393,6 +393,7 @@ LIST_85xx="		\
  	MPC8536DS_NAND	\
  	MPC8536DS_SDCARD	\
  	MPC8536DS_SPIFLASH	\
+	MPC8536DS_36BIT	\
  	MPC8540ADS	\
  	MPC8540EVAL	\
  	MPC8541CDS	\

What about 36-bit NAND, etc?

Is there a general policy about which targets to include in MAKEALL once they start exploding with combinations?

-Scott

Becky Bruce

author

2010-06-02 19:25 UTC #12 lore raw

PATCH v2 10/10 MAKEALL: Add missing powerpc 36-bit targets

Quoted 23 lines · Scott Wood

Quoted 12 lines · Becky Bruce
We were missing 8641HPCN_36BIT and MPC8536DS_36BIT.
Signed-off-by Becky Bruce<[email protected]>
---
 MAKEALL |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)
MAKEALL +0 -0
index 2527352..a82c93c 100755
MAKEALL LIST_85xx=" \ · line 399
Quoted 7 lines
MAKEALL +1 -0
@@ -393,6 +393,7 @@ LIST_85xx="		\
 	MPC8536DS_NAND	\
 	MPC8536DS_SDCARD	\
 	MPC8536DS_SPIFLASH	\
+	MPC8536DS_36BIT	\
 	MPC8540ADS	\
 	MPC8540EVAL	\
 	MPC8541CDS	\
What about 36-bit NAND, etc?

Quoted 2 lines

Is there a general policy about which targets to include in MAKEALL once they start exploding with combinations?

I don't know what the policy is, but it seemed like the 36-bit ones certainly needed to be in here. You're welcome to add whatever you want (and WD has made some changes to the build lately, so maybe that will clarify this).

-B

Wolfgang Denk

2010-06-02 20:08 UTC #13 lore raw

PATCH v2 10/10 MAKEALL: Add missing powerpc 36-bit targets

Dear Becky,

Quoted 2 lines · in message <[email protected]> you wrote:

I don't know what the policy is, but it seemed like the 36-bit ones

When I started with the MAKEALL script my idea was to have (at least) all "typical" configurations represented to cover as many as possible of the feature set. By now the number of features and possible combinations of these have reached a complexity that we eventually should build just all targets: 10 or 20 more or less - who cares?

Quoted 3 lines

certainly needed to be in here. You're welcome to add whatever you want (and WD has made some changes to the build lately, so maybe that will clarify this).

One of the ideas I have in mind with my Makefile rework is to make board configurations completely table driven, with one line entry per board configuration. The MAKEALL script would then pick the relevant boards from this database - all of them (that match certain selection criteria, like CPU type, or more, if possible).

Best regards,

Wolfgang Denk

Signature · 6 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"If you'll excuse me a minute, I'm going to have a cup of coffee."
- broadcast from Apollo 11's LEM, "Eagle", to Johnson  Space  Center,
Houston July 20, 1969, 7:27 P.M.

Scott Wood

2010-06-02 19:16 UTC #14 lore raw

PATCH v2 3/10 83xx/85xx/86xx: LBC register cleanup

In reply to Becky Bruce

arch/powerpc/include/asm/fsl_lbc.h line 518

Quoted 12 lines · Becky Bruce

arch/powerpc/include/asm/fsl_lbc.h +12 -0

+#ifdef CONFIG_NAND_FSL_ELBC
+	u8	res9[0x8];
+	u32     fmr;            /* Flash Mode Register */
+	u32     fir;            /* Flash Instruction Register */
+	u32     fcr;            /* Flash Command Register */
+	u32     fbar;           /* Flash Block Addr Register */
+	u32     fpar;           /* Flash Page Addr Register */
+	u32     fbcr;           /* Flash Byte Count Register */
+	u8      res10[0xF08];
+#else
+	u8      res9[0xF28];
+#endif

Shouldn't this be CONFIG_FSL_ELBC (or really, CONFIG_SYS_FSL_ELBC, as it describes the hardware and not user config)? The existence of these fields isn't dependent on whether we're enabling the NAND driver (who knows, some board code might want to do something directly with it, or someone could just want the NAND SPL for some strange reason, or...).

-Scott

Becky Bruce

author

2010-06-02 19:32 UTC #15 lore raw

PATCH v2 3/10 83xx/85xx/86xx: LBC register cleanup

Quoted 12 lines · Scott Wood

Quoted 11 lines · Becky Bruce

arch/powerpc/include/asm/fsl_lbc.h +11 -0

+#ifdef CONFIG_NAND_FSL_ELBC
+	u8	res9[0x8];
+	u32     fmr;            /* Flash Mode Register */
+	u32     fir;            /* Flash Instruction Register */
+	u32     fcr;            /* Flash Command Register */
+	u32     fbar;           /* Flash Block Addr Register */
+	u32     fpar;           /* Flash Page Addr Register */
+	u32     fbcr;           /* Flash Byte Count Register */
+	u8      res10[0xF08];
+#else
+	u8      res9[0xF28];

Quoted 8 lines

Quoted 1 line
+#endif
Shouldn't this be CONFIG_FSL_ELBC (or really, CONFIG_SYS_FSL_ELBC, as it describes the hardware and not user config)? The existence of these fields isn't dependent on whether we're enabling the NAND driver (who knows, some board code might want to do something directly with it, or someone could just want the NAND SPL for some strange reason, or...).

I don't think these fields exist on every ELBC, but I could be wrong....... I remember digging through a pile of docs but, unfortunately, I'm WFH today and my nice handy printouts are on my desk at the office, so I'll have to peek at it tomorrow.

-Becky

Becky Bruce

author

2010-06-02 20:55 UTC #16 lore raw

PATCH v3 3/10 83xx/85xx/86xx: LBC register cleanup

In reply to Becky Bruce

Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot.

In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play.

I have done a successful ppc build all and tested a board or two from each processor family.

Signed-off-by Becky Bruce <[email protected]>

---
 Makefile                                       |    1 +
 arch/powerpc/cpu/mpc83xx/cpu.c                 |   12 ++--
 arch/powerpc/cpu/mpc83xx/cpu_init.c            |   53 ++----------
 arch/powerpc/cpu/mpc83xx/nand_init.c           |    4 +-
 arch/powerpc/cpu/mpc83xx/speed.c               |    2 +-
 arch/powerpc/cpu/mpc85xx/cpu.c                 |   12 +--
 arch/powerpc/cpu/mpc85xx/cpu_init.c            |   58 +------------
 arch/powerpc/cpu/mpc85xx/cpu_init_nand.c       |    6 +-
 arch/powerpc/cpu/mpc85xx/speed.c               |    5 +-
 arch/powerpc/cpu/mpc86xx/cpu.c                 |   15 +---
 arch/powerpc/cpu/mpc86xx/cpu_init.c            |   55 +------------
 arch/powerpc/cpu/mpc86xx/speed.c               |    5 +-
 arch/powerpc/cpu/mpc8xxx/Makefile              |    3 +
 arch/powerpc/cpu/mpc8xxx/fsl_lbc.c             |   84 ++++++++++++++++++
 arch/powerpc/include/asm/config.h              |    6 ++
 arch/powerpc/include/asm/fsl_lbc.h             |  109 ++++++++++++++----------
 arch/powerpc/include/asm/immap_83xx.h          |   13 ++--
 arch/powerpc/include/asm/immap_85xx.h          |   46 +----------
 arch/powerpc/include/asm/immap_86xx.h          |   49 +----------
 board/atum8548/atum8548.c                      |    2 +-
 board/esd/vme8349/vme8349.c                    |    2 +-
 board/freescale/mpc8313erdb/sdram.c            |    2 +-
 board/freescale/mpc8349emds/mpc8349emds.c      |    2 +-
 board/freescale/mpc8349itx/mpc8349itx.c        |    7 +-
 board/freescale/mpc8360emds/mpc8360emds.c      |    6 +-
 board/freescale/mpc8360erdk/nand.c             |    6 +-
 board/freescale/mpc8540ads/mpc8540ads.c        |    8 +-
 board/freescale/mpc8541cds/mpc8541cds.c        |   13 +--
 board/freescale/mpc8544ds/mpc8544ds.c          |    2 +-
 board/freescale/mpc8548cds/mpc8548cds.c        |   13 +--
 board/freescale/mpc8555cds/mpc8555cds.c        |   12 +--
 board/freescale/mpc8560ads/mpc8560ads.c        |    8 +-
 board/freescale/mpc8568mds/mpc8568mds.c        |   11 +--
 board/freescale/mpc8569mds/mpc8569mds.c        |    2 +-
 board/mpc8540eval/mpc8540eval.c                |    6 +-
 board/pm854/pm854.c                            |    2 +-
 board/pm856/pm856.c                            |    2 +-
 board/sbc8349/sbc8349.c                        |    2 +-
 board/sbc8548/sbc8548.c                        |   20 ++---
 board/sbc8560/sbc8560.c                        |    6 +-
 board/sheldon/simpc8313/sdram.c                |    2 +-
 board/sheldon/simpc8313/simpc8313.c            |    2 +-
 board/socrates/socrates.c                      |   31 +++----
 board/tqc/tqm834x/tqm834x.c                    |    8 +-
 board/tqc/tqm85xx/nand.c                       |   12 ++--
 board/tqc/tqm85xx/tqm85xx.c                    |   35 ++++----
 board/xes/xpedite5170/xpedite5170.c            |   10 +--
 board/xes/xpedite5200/xpedite5200.c            |   11 +--
 board/xes/xpedite5370/xpedite5370.c            |    9 +-
 drivers/mtd/nand/fsl_elbc_nand.c               |   18 ++---
 include/mpc85xx.h                              |    2 -
 nand_spl/board/freescale/mpc8536ds/nand_boot.c |    5 +-
 nand_spl/nand_boot_fsl_elbc.c                  |    4 +-
 53 files changed, 321 insertions(+), 500 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc8xxx/fsl_lbc.c

Makefile +1 -0

index c26e491..2d4327a 100644
@@ -220,6 +220,7 @@ LIBS += drivers/power/libpower.a
 LIBS += drivers/spi/libspi.a
 ifeq ($(CPU),mpc83xx)
 LIBS += drivers/qe/qe.a
+LIBS += arch/powerpc/cpu/mpc8xxx/lib8xxx.a
 endif
 ifeq ($(CPU),mpc85xx)
 LIBS += drivers/qe/qe.a

arch/powerpc/cpu/mpc83xx/cpu.c +6 -6

index d3be909..24193ce 100644
@@ -156,16 +156,16 @@ int checkcpu(void)
 void upmconfig (uint upm, uint *table, uint size)
 {
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile fsl_lbus_t *lbus = &immap->lbus;
+	volatile fsl_lbc_t *lbc = &immap->im_lbc;
 	volatile uchar *dummy = NULL;
 	const u32 msel = (upm + 4) << BR_MSEL_SHIFT;	/* What the MSEL field in BRn should be */
-	volatile u32 *mxmr = &lbus->mamr + upm;	/* Pointer to mamr, mbmr, or mcmr */
+	volatile u32 *mxmr = &lbc->mamr + upm;	/* ptr to mamr, mbmr, or mcmr */
 	uint i;
 
-	/* Scan all the banks to determine the base address of the device */
+	/* Find the address for the dummy write transaction */
 	for (i = 0; i < 8; i++) {
-		if ((lbus->bank[i].br & BR_MSEL) == msel) {
-			dummy = (uchar *) (lbus->bank[i].br & BR_BA);
+		if ((get_lbc_br(i) & BR_MSEL) == msel) {
+			dummy = (uchar *) (get_lbc_br(i) & BR_BA);
 			break;
 		}
 	}

@@ -179,7 +179,7 @@ void upmconfig (uint upm, uint *table, uint size)
 	*mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
 
 	for (i = 0; i < size; i++) {
-		lbus->mdr = table[i];
+		lbc->mdr = table[i];
 		__asm__ __volatile__ ("sync");
 		*dummy = 0;	/* Write the value to memory and increment MAD */
 		__asm__ __volatile__ ("sync");

arch/powerpc/cpu/mpc83xx/cpu_init.c +7 ~~-46~~

95 lines not on this page · raw message

arch/powerpc/cpu/mpc83xx/nand_init.c +2 -2

index 38e141a..d1648b7 100644
@@ -88,8 +88,8 @@ void cpu_init_f (volatile immap_t * im)
 	&& defined(CONFIG_SYS_NAND_OR_PRELIM) \
 	&& defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
 	&& defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
-	im->lbus.bank[0].br = CONFIG_SYS_NAND_BR_PRELIM;
-	im->lbus.bank[0].or = CONFIG_SYS_NAND_OR_PRELIM;
+	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
 	im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
 	im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
 #else

arch/powerpc/cpu/mpc83xx/speed.c +1 -1

index 500eef1..a42c495 100644
@@ -388,7 +388,7 @@ int get_clocks(void)
 
 	lbiu_clk = csb_clk *
 	           (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
-	lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
+	lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
 	switch (lcrr) {
 	case 2:
 	case 4:

arch/powerpc/cpu/mpc85xx/cpu.c +4 -8

index fddeb2f..4160b60 100644
@@ -257,8 +257,7 @@ void upmconfig (uint upm, uint * table, uint size)
 {
 	int i, mdr, mad, old_mad = 0;
 	volatile u32 *mxmr;
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
-	volatile u32 *brp,*orp;
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	volatile u8* dummy = NULL;
 	int upmmask;

@@ -281,12 +280,9 @@ void upmconfig (uint upm, uint * table, uint size)
 	}
 
 	/* Find the address for the dummy write transaction */
-	for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
-		 i++, brp += 2, orp += 2) {
-
-		/* Look for a valid BR with selected UPM */
-		if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
-			dummy = (volatile u8*)(in_be32(brp) & BR_BA);
+	for (i = 0; i < 8; i++) {
+		if ((get_lbc_br(i) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
+			dummy = (volatile u8 *)(get_lbc_br(i) & BR_BA);
 			break;
 		}
 	}

arch/powerpc/cpu/mpc85xx/cpu_init.c +2 ~~-56~~

76 lines not on this page · raw message

arch/powerpc/cpu/mpc85xx/cpu_init_nand.c +3 -3

index 184cca4..8fb27ab 100644
@@ -25,7 +25,7 @@
 
 void cpu_init_f(void)
 {
-	ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	/*
 	 * LCRR - Clock Ratio Register - set up local bus timing

@@ -34,8 +34,8 @@ void cpu_init_f(void)
 	out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
 
 #if defined(CONFIG_NAND_BR_PRELIM) && defined(CONFIG_NAND_OR_PRELIM)
-	out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM);
-	out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM);
+	set_lbc_br(0, CONFIG_NAND_BR_PRELIM);
+	set_lbc_or(0, CONFIG_NAND_OR_PRELIM);
 #else
 #error  CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined
 #endif

arch/powerpc/cpu/mpc85xx/speed.c +1 -4

index 8132115..dd4c6b3 100644
@@ -172,10 +172,7 @@ void get_sys_info (sys_info_t * sysInfo)
 	/* We will program LCRR to this value later */
 	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
 #else
-	{
-	    volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
-	    lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
-	}
+	lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
 #endif
 	if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
 #if defined(CONFIG_FSL_CORENET)

arch/powerpc/cpu/mpc86xx/cpu.c +1 ~~-14~~

index 1887575..0fe94a0 100644
@@ -180,22 +180,9 @@ watchdog_reset(void)
  */
 void mpc86xx_reginfo(void)
 {
-	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	ccsr_lbc_t *lbc = &immap->im_lbc;
-
 	print_bats();
 	print_laws();
-
-	printf ("Local Bus Controller Registers\n"
-		"\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0));
-	printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1));
-	printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2));
-	printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3));
-	printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4));
-	printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5));
-	printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6));
-	printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7));
-
+	print_lbc_regs();
 }
 
 /*

arch/powerpc/cpu/mpc86xx/cpu_init.c +1 ~~-54~~

68 lines not on this page · raw message

arch/powerpc/cpu/mpc86xx/speed.c +1 -4

index 64a3479..a2d0a8a 100644
@@ -97,10 +97,7 @@ void get_sys_info(sys_info_t *sysInfo)
 	/* We will program LCRR to this value later */
 	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
 #else
-	{
-		volatile ccsr_lbc_t *lbc = &immap->im_lbc;
-		lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
-	}
+	lcrr_div = in_be32(&immap->im_lbc.lcrr) & LCRR_CLKDIV;
 #endif
 	if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
 		sysInfo->freqLocalBus = sysInfo->freqSystemBus / (lcrr_div * 2);

arch/powerpc/cpu/mpc8xxx/Makefile +3 -0

index 481f9e5..34a5198 100644
@@ -10,9 +10,12 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib8xxx.a
 
+ifeq ($(CPU), $(filter $(CPU), mpc85xx mpc86xx))
 COBJS-y	+= cpu.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
 COBJS-$(CONFIG_PCI)	+= pci_cfg.o
+endif
+COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))

arch/powerpc/cpu/mpc8xxx/fsl_lbc.c new file +84 -0

84 lines not on this page · raw message

arch/powerpc/include/asm/config.h +6 -0

index fc3facb..01036f3 100644
@@ -76,4 +76,10 @@
 /* Relocation to SDRAM works on all PPC boards */
 #define CONFIG_RELOC_FIXUP_WORKS
 
+/* Most PPC SOCs have a LBC so define this here */
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
+	defined(CONFIG_MPC83xx)
+#define CONFIG_FSL_LBC
+#endif
+
 #endif /* _ASM_CONFIG_H_ */

arch/powerpc/include/asm/fsl_lbc.h +65 ~~-44~~

120 lines not on this page · raw message

arch/powerpc/include/asm/immap_83xx.h +7 -6

index 6b42a73..9353dc0 100644
@@ -635,7 +635,7 @@ typedef struct immap {
 	u8			res2[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res3[0x900];
-	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
 	u8			res4[0x1000];
 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
 	dma83xx_t		dma;		/* DMA */

@@ -675,7 +675,7 @@ typedef struct immap {
 	u8			res1[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res2[0x900];
-	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
 	u8			res3[0x1000];
 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
 	dma83xx_t		dma;		/* DMA */

@@ -710,7 +710,7 @@ typedef struct immap {
 	u8			res1[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res2[0x900];
-	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
 	u8			res3[0x1000];
 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
 	dma83xx_t		dma;		/* DMA */

@@ -755,7 +755,7 @@ typedef struct immap {
 	u8			res1[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res2[0x900];
-	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
 	u8			res3[0x1000];
 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
 	dma83xx_t		dma;		/* DMA */

@@ -805,7 +805,7 @@ typedef struct immap {
 	u8			res4[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res5[0x900];
-	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
 	u8			res6[0x2000];
 	dma83xx_t		dma;		/* DMA */
 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */

@@ -844,7 +844,7 @@ typedef struct immap {
 	u8			res3[0x1300];
 	duart83xx_t		duart[2];	/* DUART */
 	u8			res4[0x900];
-	fsl_lbus_t		lbus;	/* Local Bus Controller Registers */
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
 	u8			res5[0x2000];
 	dma83xx_t		dma;		/* DMA */
 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */

@@ -868,6 +868,7 @@ typedef struct immap {
 #endif
 #define CONFIG_SYS_MPC83xx_USB_ADDR \
 			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
+#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
 
 #define CONFIG_SYS_TSEC1_OFFSET		0x24000
 #define CONFIG_SYS_MDIO1_OFFSET		0x24000

arch/powerpc/include/asm/immap_85xx.h +1 ~~-45~~

58 lines not on this page · raw message

arch/powerpc/include/asm/immap_86xx.h +3 ~~-46~~

73 lines not on this page · raw message

board/atum8548/atum8548.c +1 -1

index c11a5c3..4f7d935 100644
@@ -47,7 +47,7 @@ int board_early_init_f (void)
 int checkboard (void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 
 	if ((uint)&gur->porpllsr != 0xe00e0000) {

board/esd/vme8349/vme8349.c +1 -1

index b0ebad7..96698e7 100644
@@ -105,7 +105,7 @@ int misc_init_r()
 {
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 
-	clrsetbits_be32(&im->lbus.lcrr, LBCR_LDIS, 0);
+	clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0);
 
 	return 0;
 }

board/freescale/mpc8313erdb/sdram.c +1 -1

index 0c4fd68..7aede13 100644
@@ -110,7 +110,7 @@ static long fixed_sdram(void)
 phys_size_t initdram(int board_type)
 {
 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile fsl_lbus_t *lbc = &im->lbus;
+	volatile fsl_lbc_t *lbc = &im->im_lbc;
 	u32 msize;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)

board/freescale/mpc8349emds/mpc8349emds.c +1 -1

index 61d1249..365ac37 100644
@@ -192,7 +192,7 @@ int checkboard (void)
 void sdram_init(void)
 {
 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile fsl_lbus_t *lbc = &immap->lbus;
+	volatile fsl_lbc_t *lbc = &immap->im_lbc;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 
 	/*

board/freescale/mpc8349itx/mpc8349itx.c +3 -4

index 7da39f1..5647579 100644
@@ -221,15 +221,14 @@ int misc_init_f(void)
 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
 	};
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile fsl_lbus_t *lbus = &immap->lbus;
 
-	lbus->bank[3].br = CONFIG_SYS_BR3_PRELIM;
-	lbus->bank[3].or = CONFIG_SYS_OR3_PRELIM;
+	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
+	set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
 
 	/* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
 	   GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
 	 */
-	lbus->mamr = 0x08404440;
+	immap->im_lbc.mamr = 0x08404440;
 
 	upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));

board/freescale/mpc8360emds/mpc8360emds.c +3 -3

index 4f55732..59ada9c 100644
@@ -280,7 +280,7 @@ int checkboard(void)
 static int sdram_init(unsigned int base)
 {
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile fsl_lbus_t *lbc = &immap->lbus;
+	fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
 	int rem = base % sdram_size;
 	uint *sdram_addr;

@@ -293,8 +293,8 @@ static int sdram_init(unsigned int base)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	immap->lbus.bank[2].br = base | CONFIG_SYS_BR2;
-	immap->lbus.bank[2].or = CONFIG_SYS_OR2;
+	set_lbc_br(2, base | CONFIG_SYS_BR2);
+	set_lbc_or(2, CONFIG_SYS_OR2);
 	immap->sysconf.lblaw[2].bar = base;
 	immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;

board/freescale/mpc8360erdk/nand.c +3 -3

index 9ffffb4..92d56a3 100644
@@ -82,9 +82,9 @@ static struct fsl_upm_nand fun = {
 
 int board_nand_init(struct nand_chip *nand)
 {
-	fun.upm.mxmr = &im->lbus.mamr;
-	fun.upm.mdr = &im->lbus.mdr;
-	fun.upm.mar = &im->lbus.mar;
+	fun.upm.mxmr = &im->im_lbc.mamr;
+	fun.upm.mdr = &im->im_lbc.mdr;
+	fun.upm.mar = &im->im_lbc.mar;
 
 	upm_setup(&fun.upm);

board/freescale/mpc8540ads/mpc8540ads.c +4 -4

index 9e3f677..f9ff827 100644
@@ -117,7 +117,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

@@ -176,7 +176,7 @@ local_bus_init(void)
 void
 sdram_init(void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 
 	puts("    SDRAM: ");

@@ -185,8 +185,8 @@ sdram_init(void)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
-	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	asm("msync");

board/freescale/mpc8541cds/mpc8541cds.c +4 -9

index c30d966..0580fe7 100644
@@ -291,7 +291,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

@@ -340,7 +340,7 @@ sdram_init(void)
 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 
 	uint idx;
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 	uint cpu_board_rev;
 	uint lsdmr_common;

@@ -352,16 +352,11 @@ sdram_init(void)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
-	asm("msync");
-
-	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
-	asm("msync");
-
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	asm("msync");
 
-
 	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 	asm("msync");

board/freescale/mpc8544ds/mpc8544ds.c +1 -1

index 0be2d89..581d5f2 100644
@@ -40,7 +40,7 @@
 int checkboard (void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 	u8 vboot;
 	u8 *pixis_base = (u8 *)PIXIS_BASE;

board/freescale/mpc8548cds/mpc8548cds.c +4 -9

index aa3f32b..f016995 100644
@@ -118,7 +118,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

@@ -154,7 +154,7 @@ sdram_init(void)
 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 
 	uint idx;
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 	uint cpu_board_rev;
 	uint lsdmr_common;

@@ -166,16 +166,11 @@ sdram_init(void)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
-	asm("msync");
-
-	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
-	asm("msync");
-
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	asm("msync");
 
-
 	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 	asm("msync");

board/freescale/mpc8555cds/mpc8555cds.c +4 -8

index ecddd0d..b7e0e0c 100644
@@ -291,7 +291,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

@@ -340,7 +340,7 @@ sdram_init(void)
 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 
 	uint idx;
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 	uint cpu_board_rev;
 	uint lsdmr_common;

@@ -352,12 +352,8 @@ sdram_init(void)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
-	asm("msync");
-
-	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
-	asm("msync");
-
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	asm("msync");

board/freescale/mpc8560ads/mpc8560ads.c +4 -4

index 2bca0f2..489f90b 100644
@@ -322,7 +322,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

@@ -381,7 +381,7 @@ local_bus_init(void)
 void
 sdram_init(void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 
 	puts("    SDRAM: ");

@@ -390,8 +390,8 @@ sdram_init(void)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
-	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	asm("msync");

board/freescale/mpc8568mds/mpc8568mds.c +4 -7

index 4ec13a9..036bf95 100644
@@ -181,7 +181,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

@@ -214,7 +214,7 @@ sdram_init(void)
 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 
 	uint idx;
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 	uint lsdmr_common;

@@ -225,16 +225,13 @@ sdram_init(void)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
-	asm("msync");
-
-	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	asm("msync");
 
 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	asm("msync");
 
-
 	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 	asm("msync");

board/freescale/mpc8569mds/mpc8569mds.c +1 -1

index 1eddeef..81e8ff5 100644
@@ -308,7 +308,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

board/mpc8540eval/mpc8540eval.c +3 -3

index 7c27233..054d644 100644
@@ -69,7 +69,7 @@ phys_size_t initdram (int board_type)
 	long dram_size = 0;
 
 #if !defined(CONFIG_RAM_AS_FLASH)
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	sys_info_t sysinfo;
 	uint temp_lbcdll = 0;
 #endif

@@ -110,8 +110,8 @@ phys_size_t initdram (int board_type)
 		gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
 		asm("sync;isync;msync");
 	}
-	lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
-	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
 	asm("sync");

board/pm854/pm854.c +1 -1

index 5353d73..a302b91 100644
@@ -134,7 +134,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

board/pm856/pm856.c +1 -1

index b14a3d3..f9d92d9 100644
@@ -290,7 +290,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

board/sbc8349/sbc8349.c +1 -1

index 34861d4..50fae7c 100644
@@ -160,7 +160,7 @@ int checkboard (void)
 void sdram_init(void)
 {
 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile fsl_lbus_t *lbc = &immap->lbus;
+	volatile fsl_lbc_t *lbc = &immap->im_lbc;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 
 	puts("\n   SDRAM on Local Bus: ");

board/sbc8548/sbc8548.c +6 ~~-14~~

index 194f6ab..d62cfd1 100644
@@ -116,7 +116,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;

@@ -152,7 +152,7 @@ sdram_init(void)
 #if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
 
 	uint idx;
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 	uint lsdmr_common;

@@ -163,22 +163,14 @@ sdram_init(void)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
-	asm("msync");
-
-	out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
-	asm("msync");
-
-	out_be32(&lbc->or4, CONFIG_SYS_OR4_PRELIM);
-	asm("msync");
-
-	out_be32(&lbc->br4, CONFIG_SYS_BR4_PRELIM);
-	asm("msync");
+	set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
+	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
+	set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
+	set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
 
 	out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
 	asm("msync");
 
-
 	out_be32(&lbc->lsrt,  CONFIG_SYS_LBC_LSRT);
 	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
 	asm("msync");

board/sbc8560/sbc8560.c +3 -3

index c40b5e3..10ba62f 100644
@@ -269,7 +269,7 @@ phys_size_t initdram (int board_type)
 
 #if 0
 #if !defined(CONFIG_RAM_AS_FLASH)
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	sys_info_t sysinfo;
 	uint temp_lbcdll = 0;
 #endif

@@ -310,8 +310,8 @@ phys_size_t initdram (int board_type)
 		gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
 		asm("sync;isync;msync");
 	}
-	lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
-	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
 	asm("sync");

board/sheldon/simpc8313/sdram.c +1 -1

index ebb70a2..ba59943 100644
@@ -129,7 +129,7 @@ void si_read_i2c(u32 lbyte, int count, u8 *buffer)
 phys_size_t initdram(int board_type)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile fsl_lbus_t *lbc= &im->lbus;
+	volatile fsl_lbc_t *lbc = &im->im_lbc;
 	u32 msize;
 
 	if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im)

board/sheldon/simpc8313/simpc8313.c +1 -1

index cb30b48..c2164c9 100644
@@ -93,7 +93,7 @@ int misc_init_r(void)
 {
 	int rc = 0;
 	immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	fsl_lbus_t *lbus = &immap->lbus;
+	fsl_lbc_t *lbus = &immap->im_lbc;
 	u32 *mxmr = &lbus->mamr;	/* Pointer to mamr */
 
 	/* UPM Table Configuration Code */

board/socrates/socrates.c +15 ~~-16~~

index 9183c15..72e7401 100644
@@ -87,8 +87,6 @@ int checkboard (void)
 
 int misc_init_r (void)
 {
-	volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
-
 	/*
 	 * Adjust flash start and offset to detected values
 	 */

@@ -99,8 +97,10 @@ int misc_init_r (void)
 	 * Check if boot FLASH isn't max size
 	 */
 	if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
-		memctl->or0 = gd->bd->bi_flashstart | (CONFIG_SYS_OR0_PRELIM & 0x00007fff);
-		memctl->br0 = gd->bd->bi_flashstart | (CONFIG_SYS_BR0_PRELIM & 0x00007fff);
+		set_lbc_or(0, gd->bd->bi_flashstart |
+			   (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
+		set_lbc_br(0, gd->bd->bi_flashstart |
+			   (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
 
 		/*
 		 * Re-check to get correct base address

@@ -112,8 +112,8 @@ int misc_init_r (void)
 	 * Check if only one FLASH bank is available
 	 */
 	if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
-		memctl->or1 = 0;
-		memctl->br1 = 0;
+		set_lbc_or(1, 0);
+		set_lbc_br(1, 0);
 
 		/*
 		 * Re-do flash protection upon new addresses

@@ -148,7 +148,7 @@ int misc_init_r (void)
  */
 void local_bus_init (void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 	sys_info_t sysinfo;
 	uint clkdiv;

@@ -299,26 +299,25 @@ const gdc_regs *board_get_regs (void)
 
 int lime_probe(void)
 {
-	volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 	uint cfg_br2;
 	uint cfg_or2;
 	int type;
 
-	cfg_br2 = memctl->br2;
-	cfg_or2 = memctl->or2;
+	cfg_br2 = get_lbc_br(2);
+	cfg_or2 = get_lbc_or(2);
 
 	/* Configure GPCM for CS2 */
-	memctl->br2 = 0;
-	memctl->or2 = 0xfc000410;
-	memctl->br2 = (CONFIG_SYS_LIME_BASE) | 0x00001901;
+	set_lbc_br(2, 0);
+	set_lbc_or(2, 0xfc000410);
+	set_lbc_br(2, (CONFIG_SYS_LIME_BASE) | 0x00001901);
 
 	/* Get controller type */
 	type = mb862xx_probe(CONFIG_SYS_LIME_BASE);
 
 	/* Restore previous CS2 configuration */
-	memctl->br2 = 0;
-	memctl->or2 = cfg_or2;
-	memctl->br2 = cfg_br2;
+	set_lbc_br(2, 0);
+	set_lbc_or(2, cfg_or2);
+	set_lbc_br(2, cfg_br2);
 
 	return (type == MB862XX_TYPE_LIME) ? 1 : 0;
 }

board/tqc/tqm834x/tqm834x.c +4 -4

index e564879..8d046f4 100644
@@ -253,10 +253,10 @@ static int detect_num_flash_banks(void)
 	debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks);
 
 	/* set OR0 and BR0 */
-	im->lbus.bank[0].or = CONFIG_SYS_OR_TIMING_FLASH |
-		(-(total_size) & OR_GPCM_AM);
-	im->lbus.bank[0].br = (CONFIG_SYS_FLASH_BASE & BR_BA) |
-		(BR_MS_GPCM | BR_PS_32 | BR_V);
+	set_lbc_or(0, CONFIG_SYS_OR_TIMING_FLASH |
+		   (-(total_size) & OR_GPCM_AM));
+	set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) |
+		   (BR_MS_GPCM | BR_PS_32 | BR_V));
 
 	return (0);
 }

board/tqc/tqm85xx/nand.c +6 -6

index 3da689a..4b16c31 100644
@@ -377,7 +377,7 @@ volatile const u32 *nand_upm_patt;
  */
 static void upmb_write (u_char addr, ulong val)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	out_be32 (&lbc->mdr, val);

@@ -393,14 +393,14 @@ static void upmb_write (u_char addr, ulong val)
 /*
  * Initialize UPM for NAND flash access.
  */
-static void nand_upm_setup (volatile ccsr_lbc_t *lbc)
+static void nand_upm_setup (volatile fsl_lbc_t *lbc)
 {
 	uint i, j;
 	uint or3 = CONFIG_SYS_OR3_PRELIM;
 	uint clock = get_lbc_clock ();
 
-	out_be32 (&lbc->br3, 0);	/* disable bank and reset all bits */
-	out_be32 (&lbc->br3, CONFIG_SYS_BR3_PRELIM);
+	set_lbc_br(3, 0);	/* disable bank and reset all bits */
+	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
 
 	/*
 	 * Search appropriate UPM table for bus clock.

@@ -424,7 +424,7 @@ static void nand_upm_setup (volatile ccsr_lbc_t *lbc)
 		/* EAD must be set due to TQM8548 timing specification */
 		or3 |= OR_UPM_EAD;
 
-	out_be32 (&lbc->or3, or3);
+	set_lbc_or(3, or3);
 
 	/* Assign address of table */
 	nand_upm_patt = upm_freq_table[i].upm_patt;

@@ -458,7 +458,7 @@ void board_nand_select_device (struct nand_chip *nand, int chip)
 
 int board_nand_init (struct nand_chip *nand)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	if (!nand_upm_patt)
 		nand_upm_setup (lbc);

board/tqc/tqm85xx/tqm85xx.c +17 ~~-18~~

index 8c9d586..fc2a6cb 100644
@@ -269,8 +269,6 @@ int checkboard (void)
 
 int misc_init_r (void)
 {
-	volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
-
 	/*
 	 * Adjust flash start and offset to detected values
 	 */

@@ -281,26 +279,27 @@ int misc_init_r (void)
 	 * Recalculate CS configuration if second FLASH bank is available
 	 */
 	if (flash_info[0].size > 0) {
-		memctl->or1 = ((-flash_info[0].size) & 0xffff8000) |
-			(CONFIG_SYS_OR1_PRELIM & 0x00007fff);
-		memctl->br1 = gd->bd->bi_flashstart |
-			(CONFIG_SYS_BR1_PRELIM & 0x00007fff);
+		set_lbc_or(1, ((-flash_info[0].size) & 0xffff8000) |
+			   (CONFIG_SYS_OR1_PRELIM & 0x00007fff));
+		set_lbc_br(1, gd->bd->bi_flashstart |
+			   (CONFIG_SYS_BR1_PRELIM & 0x00007fff));
 		/*
 		 * Re-check to get correct base address for bank 1
 		 */
 		flash_get_size (gd->bd->bi_flashstart, 0);
 	} else {
-		memctl->or1 = 0;
-		memctl->br1 = 0;
+		set_lbc_or(1, 0);
+		set_lbc_br(1, 0);
 	}
 
 	/*
 	 *  If bank 1 is equipped, bank 0 is mapped after bank 1
 	 */
-	memctl->or0 = ((-flash_info[1].size) & 0xffff8000) |
-		(CONFIG_SYS_OR0_PRELIM & 0x00007fff);
-	memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) |
-		(CONFIG_SYS_BR0_PRELIM & 0x00007fff);
+	set_lbc_or(0, ((-flash_info[1].size) & 0xffff8000) |
+		   (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
+	set_lbc_br(0, gd->bd->bi_flashstart |
+		   (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
+
 	/*
 	 * Re-check to get correct base address for bank 0
 	 */

@@ -341,7 +340,7 @@ int misc_init_r (void)
  */
 static void upmc_write (u_char addr, uint val)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	out_be32 (&lbc->mdr, val);

@@ -358,7 +357,7 @@ static void upmc_write (u_char addr, uint val)
 
 uint get_lbc_clock (void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	sys_info_t sys_info;
 	ulong clkdiv = lbc->lcrr & LCRR_CLKDIV;

@@ -386,7 +385,7 @@ uint get_lbc_clock (void)
 void local_bus_init (void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint lbc_mhz = get_lbc_clock ()  / 1000000;
 
 #ifdef CONFIG_MPC8548

@@ -502,10 +501,10 @@ void local_bus_init (void)
 	 * set if Local Bus Clock is > 83 MHz.
 	 */
 	if (lbc_mhz > 83)
-		out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
+		set_lbc_or(2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
 	else
-		out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN);
-	out_be32 (&lbc->br2, CONFIG_SYS_BR2_CAN);
+		set_lbc_or(2, CONFIG_SYS_OR2_CAN);
+	set_lbc_br(2, CONFIG_SYS_BR2_CAN);
 
 	/* LGPL4 is UPWAIT */
 	out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);

board/xes/xpedite5170/xpedite5170.c +4 -6

index f4231a9..5822941 100644
@@ -56,8 +56,6 @@ int checkboard(void)
  */
 static void flash_cs_fixup(void)
 {
-	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	ccsr_lbc_t *lbc = &immap->im_lbc;
 	int flash_sel;
 
 	/*

@@ -70,11 +68,11 @@ static void flash_cs_fixup(void)
 	printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
 
 	if (flash_sel) {
-		out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM);
-		out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM);
+		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
 
-		out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM);
-		out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM);
+		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
 	}
 }

board/xes/xpedite5200/xpedite5200.c +5 -6

index 7109771..a2627f8 100644
@@ -38,7 +38,7 @@ extern void ft_board_pci_setup(void *blob, bd_t *bd);
 
 int checkboard(void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 	char *s;

@@ -65,7 +65,6 @@ int checkboard(void)
 
 static void flash_cs_fixup(void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 	int flash_sel;
 
 	/*

@@ -78,11 +77,11 @@ static void flash_cs_fixup(void)
 	printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
 
 	if (flash_sel) {
-		out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM);
-		out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM);
+		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
 
-		out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM);
-		out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM);
+		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
 	}
 }

board/xes/xpedite5370/xpedite5370.c +4 -5

index 48d9fc8..2a060c2 100644
@@ -58,7 +58,6 @@ int checkboard(void)
 
 static void flash_cs_fixup(void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 	int flash_sel;
 
 	/*

@@ -71,11 +70,11 @@ static void flash_cs_fixup(void)
 	printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
 
 	if (flash_sel) {
-		out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM);
-		out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM);
+		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
 
-		out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM);
-		out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM);
+		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
 	}
 }

drivers/mtd/nand/fsl_elbc_nand.c +7 ~~-11~~

index 146e9bf..acdb431 100644
@@ -75,7 +75,7 @@ struct fsl_elbc_ctrl {
 	struct fsl_elbc_mtd *chips[MAX_BANKS];
 
 	/* device info */
-	fsl_lbus_t *regs;
+	fsl_lbc_t *regs;
 	u8 __iomem *addr;        /* Address of assigned FCM buffer        */
 	unsigned int page;       /* Last page written to / read from      */
 	unsigned int read_bytes; /* Number of bytes read during command   */

@@ -171,7 +171,7 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	fsl_lbus_t *lbc = ctrl->regs;
+	fsl_lbc_t *lbc = ctrl->regs;
 	int buf_num;
 
 	ctrl->page = page_addr;

@@ -211,7 +211,7 @@ static int fsl_elbc_run_command(struct mtd_info *mtd)
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	fsl_lbus_t *lbc = ctrl->regs;
+	fsl_lbc_t *lbc = ctrl->regs;
 	long long end_tick;
 	u32 ltesr;

@@ -261,7 +261,7 @@ static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 {
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	fsl_lbus_t *lbc = ctrl->regs;
+	fsl_lbc_t *lbc = ctrl->regs;
 
 	if (priv->page_size) {
 		out_be32(&lbc->fir,

@@ -295,7 +295,7 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	fsl_lbus_t *lbc = ctrl->regs;
+	fsl_lbc_t *lbc = ctrl->regs;
 
 	ctrl->use_mdr = 0;

@@ -633,7 +633,7 @@ static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 {
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	fsl_lbus_t *lbc = ctrl->regs;
+	fsl_lbc_t *lbc = ctrl->regs;
 
 	if (ctrl->status != LTESR_CC)
 		return NAND_STATUS_FAIL;

@@ -697,11 +697,7 @@ static void fsl_elbc_ctrl_init(void)
 	if (!elbc_ctrl)
 		return;
 
-#ifdef CONFIG_MPC85xx
-	elbc_ctrl->regs = (void *)CONFIG_SYS_MPC85xx_LBC_ADDR;
-#else
-	elbc_ctrl->regs = &((immap_t *)CONFIG_SYS_IMMR)->lbus;
-#endif
+	elbc_ctrl->regs = LBC_BASE_ADDR;
 
 	/* clear event registers */
 	out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);

include/mpc85xx.h +0 -2

index a4d4d65..2495b99 100644
@@ -6,8 +6,6 @@
 #ifndef	__MPC85xx_H__
 #define __MPC85xx_H__
 
-#include <asm/fsl_lbc.h>
-
 /* define for common ppc_asm.tmpl */
 #define EXC_OFF_SYS_RESET	0x100	/* System reset */
 #define _START_OFFSET		0

nand_spl/board/freescale/mpc8536ds/nand_boot.c +2 -3

index af29dc2..5a0a0c7 100644
@@ -34,12 +34,11 @@ void board_init_f(ulong bootflag)
 	int px_spd;
 	u32 plat_ratio, bus_clk, sys_clk;
 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-	ccsr_lbc_t *lbc = (void *)CONFIG_SYS_MPC85xx_LBC_ADDR;
 
 #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
 	/* for FPGA */
-	out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
-	out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
+	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
+	set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
 #else
 #error CONFIG_SYS_BR3_PRELIM, CONFIG_SYS_OR3_PRELIM must be defined
 #endif

nand_spl/nand_boot_fsl_elbc.c +2 -2

index ff47d55..9547d44 100644
@@ -32,7 +32,7 @@
 
 static void nand_wait(void)
 {
-	fsl_lbus_t *regs = (fsl_lbus_t *)(CONFIG_SYS_IMMR + 0x5000);
+	fsl_lbc_t *regs = LBC_BASE_ADDR;
 
 	for (;;) {
 		uint32_t status = in_be32(&regs->ltesr);

@@ -49,7 +49,7 @@ static void nand_wait(void)
 
 static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
 {
-	fsl_lbus_t *regs = (fsl_lbus_t *)(CONFIG_SYS_IMMR + 0x5000);
+	fsl_lbc_t *regs = LBC_BASE_ADDR;
 	uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
 	int large = in_be32(&regs->bank[0].or) & OR_FCM_PGS;
 	int block_shift = large ? 17 : 14;

Signature · 1 line

1.6.0.6

Becky Bruce

author

2010-06-02 20:57 UTC #17 lore raw

PATCH v3 3/10 83xx/85xx/86xx: LBC register cleanup

Note: I resubmitted this one, as the signed-off-by line had somehow gone into the great big bit-bucket in the sky.

-Becky

Kim Phillips

2010-06-04 00:37 UTC #18 lore raw

PATCH v2 3/10 83xx/85xx/86xx: LBC register cleanup

In reply to Becky Bruce

arch/powerpc/include/asm/config.h line 82

Quoted 12 lines · On Wed, 2 Jun 2010 13:12:02 -0500 Becky Bruce <[email protected]>…

arch/powerpc/include/asm/config.h +4 -0

index fc3facb..01036f3 100644
@@ -76,4 +76,10 @@
 /* Relocation to SDRAM works on all PPC boards */
 #define CONFIG_RELOC_FIXUP_WORKS
 
+/* Most PPC SOCs have a LBC so define this here */
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
+	defined(CONFIG_MPC83xx)
+#define CONFIG_FSL_LBC

Instead of in the configs (such as what patch 1 in this series continues to do), can we do ELBC determination here, based on finer-grained configs such as 831x, 837x, etc?

arch/powerpc/include/asm/config.h line 83

Quoted 1 line

arch/powerpc/include/asm/config.h +1 -0
+#endif

Thanks,

Kim

Scott Wood

2010-06-04 20:22 UTC #19 lore raw

PATCH v2 3/10 83xx/85xx/86xx: LBC register cleanup

Quoted 11 lines · Kim Phillips

Quoted 8 lines · On Wed, 2 Jun 2010 13:12:02 -0500 Becky Bruce <[email protected]>…
arch/powerpc/include/asm/config.h +0 -0
index fc3facb..01036f3 100644
@@ -76,4 +76,10 @@
 /* Relocation to SDRAM works on all PPC boards */
 #define CONFIG_RELOC_FIXUP_WORKS
 

Quoted 1 line

arch/powerpc/include/asm/config.h line 79
Quoted 1 line
arch/powerpc/include/asm/config.h +1 -0
+/* Most PPC SOCs have a LBC so define this here */

Even non-Freescale ones?

Quoted 3 lines

arch/powerpc/include/asm/config.h line 82
Quoted 3 lines
arch/powerpc/include/asm/config.h +3 -0
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
+	defined(CONFIG_MPC83xx)
+#define CONFIG_FSL_LBC

What about PQ2?

Quoted 3 lines

Instead of in the configs (such as what patch 1 in this series continues to do), can we do ELBC determination here, based on finer-grained configs such as 831x, 837x, etc?

Let's not introduce more huge ifdef lists, please.

If you don't want to specify it on a per-board basis, have a header file per soc that the board config file includes.

-Scott

Becky Bruce

author

2010-06-08 16:15 UTC #20 lore raw

PATCH v2 3/10 83xx/85xx/86xx: LBC register cleanup

In reply to Kim Phillips

This isn't *ELBC*, it's the existence of any sort of LBC. ELBC is determined per-board in the fine grained configs. There are 2 configs.

-B

Quoted 26 lines · Kim Phillips

arch/powerpc/include/asm/config.h line 82
Quoted 13 lines · On Wed, 2 Jun 2010 13:12:02 -0500 Becky Bruce <[email protected]>…
arch/powerpc/ renamed from arch/powerpc/include/asm/config.h +0 -0
include/asm/config.h
index fc3facb..01036f3 100644
arch/powerpc/include/asm/config.h +4 -0
@@ -76,4 +76,10 @@
 /* Relocation to SDRAM works on all PPC boards */
 #define CONFIG_RELOC_FIXUP_WORKS
 
+/* Most PPC SOCs have a LBC so define this here */
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
+	defined(CONFIG_MPC83xx)
+#define CONFIG_FSL_LBC
Instead of in the configs (such as what patch 1 in this series continues to do), can we do ELBC determination here, based on finer-grained configs such as 831x, 837x, etc?
arch/powerpc/include/asm/config.h line 83
Quoted 1 line
arch/powerpc/include/asm/config.h +1 -0
+#endif
Thanks,
Kim

Kim Phillips

2010-06-08 17:09 UTC #21 lore raw

PATCH v2 3/10 83xx/85xx/86xx: LBC register cleanup

Quoted 2 lines · On Tue, 8 Jun 2010 11:15:07 -0500 Becky Bruce <[email protected]>…

This isn't *ELBC*, it's the existence of any sort of LBC. ELBC is determined per-board in the fine grained configs. There are 2 configs.

that's what I was suggesting to change; to group and centralize the definition of the two seemingly related configs - also because the ELBC should be done at the SoC level.

See Scott's response though - I don't know how long the ELBC ifdef list is, but introducing a header file per soc sounds like a bit out of scope for this patchseries - it already cleans up a bunch of stuff.

Quoted 1 line

-B

Kim

p.s. please don't top-post :).

Quoted 30 lines · Kim Phillips

Quoted 27 lines
arch/powerpc/include/asm/config.h line 82
Quoted 13 lines · On Wed, 2 Jun 2010 13:12:02 -0500 Becky Bruce <[email protected]>…
arch/powerpc/ renamed from arch/powerpc/include/asm/config.h +0 -0
include/asm/config.h
index fc3facb..01036f3 100644
arch/powerpc/include/asm/config.h +4 -0
@@ -76,4 +76,10 @@
 /* Relocation to SDRAM works on all PPC boards */
 #define CONFIG_RELOC_FIXUP_WORKS
 
+/* Most PPC SOCs have a LBC so define this here */
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
+	defined(CONFIG_MPC83xx)
+#define CONFIG_FSL_LBC
Instead of in the configs (such as what patch 1 in this series continues to do), can we do ELBC determination here, based on finer-grained configs such as 831x, 837x, etc?
arch/powerpc/include/asm/config.h line 83
Quoted 1 line
arch/powerpc/include/asm/config.h +1 -0
+#endif
Thanks,
Kim

Becky Bruce

author

2010-06-08 17:28 UTC #22 lore raw

PATCH v2 3/10 83xx/85xx/86xx: LBC register cleanup

Quoted 12 lines · Kim Phillips

Quoted 3 lines · On Tue, 8 Jun 2010 11:15:07 -0500 Becky Bruce <[email protected]>…
This isn't *ELBC*, it's the existence of any sort of LBC. ELBC is determined per-board in the fine grained configs. There are 2 configs.
that's what I was suggesting to change; to group and centralize the definition of the two seemingly related configs - also because the ELBC
should be done at the SoC level.

Quoted 4 lines

See Scott's response though - I don't know how long the ELBC ifdef list
is, but introducing a header file per soc sounds like a bit out of scope for this patchseries - it already cleans up a bunch of stuff.

I think it is out of scope here - I think this is fine the way it is, at least for now. I'd like to get these cleanups in as soon as possible before someone else replicates more code.

We can post a followon later to change how we deal with ELBC/LBC; and there are also more cleanups to be done - for example, there's still code that accesses lbc space not using IO accessors. I've cleaned up the BR/OR cases, but I want to eventually fix it all. Unfortunately, I'm out of time at this point. This patch series is a significant step forward, but there's still more work to be done.

Cheers,
Becky

Quoted 37 lines

Quoted 2 lines
-B
Kim
p.s. please don't top-post :).
Quoted 30 lines · Kim Phillips
Quoted 27 lines
arch/powerpc/include/asm/config.h line 82
Quoted 13 lines · On Wed, 2 Jun 2010 13:12:02 -0500 Becky Bruce <[email protected]>…
arch/powerpc/ renamed from arch/powerpc/include/asm/config.h +0 -0
include/asm/config.h
index fc3facb..01036f3 100644
arch/powerpc/include/asm/config.h +4 -0
@@ -76,4 +76,10 @@
 /* Relocation to SDRAM works on all PPC boards */
 #define CONFIG_RELOC_FIXUP_WORKS
 
+/* Most PPC SOCs have a LBC so define this here */
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
+	defined(CONFIG_MPC83xx)
+#define CONFIG_FSL_LBC
Instead of in the configs (such as what patch 1 in this series continues to do), can we do ELBC determination here, based on finer-grained configs such as 831x, 837x, etc?
arch/powerpc/include/asm/config.h line 83
Quoted 1 line
arch/powerpc/include/asm/config.h +1 -0
+#endif
Thanks,
Kim

Kim Phillips

2010-06-08 18:43 UTC #23 lore raw

PATCH v2 3/10 83xx/85xx/86xx: LBC register cleanup

Quoted 24 lines · On Tue, 8 Jun 2010 12:28:48 -0500 Becky Bruce <[email protected]>…

Quoted 12 lines · Kim Phillips
Quoted 3 lines · On Tue, 8 Jun 2010 11:15:07 -0500 Becky Bruce <[email protected]>…
This isn't *ELBC*, it's the existence of any sort of LBC. ELBC is determined per-board in the fine grained configs. There are 2 configs.
that's what I was suggesting to change; to group and centralize the definition of the two seemingly related configs - also because the ELBC
should be done at the SoC level.
Quoted 4 lines
See Scott's response though - I don't know how long the ELBC ifdef list
is, but introducing a header file per soc sounds like a bit out of scope for this patchseries - it already cleans up a bunch of stuff.
I think it is out of scope here - I think this is fine the way it is, at least for now. I'd like to get these cleanups in as soon as possible before someone else replicates more code.

Quoted 6 lines

We can post a followon later to change how we deal with ELBC/LBC; and there are also more cleanups to be done - for example, there's still code that accesses lbc space not using IO accessors. I've cleaned up the BR/OR cases, but I want to eventually fix it all. Unfortunately, I'm out of time at this point. This patch series is a significant step forward, but there's still more work to be done.

ok but e.g., patch 1 in this series omits the MPC837XERDB, which needs to be fixed.

I was curious so I compiled the ELBC CONFIG_ list, in case you want to change patch 1 in the series to _delete_ the entries in the board configs and add them as pointed out in this patch:

MPC831x
MPC837x
MPC8536
MPC8569
MPC8572

and, of course, the Pxxxx's.

Quoted 2 lines

Cheers,
Becky

Kim

Quoted 40 lines

Quoted 38 lines
Quoted 3 lines
-B
Kim
p.s. please don't top-post :).
Quoted 30 lines · Kim Phillips
Quoted 27 lines
arch/powerpc/include/asm/config.h line 82
Quoted 13 lines · On Wed, 2 Jun 2010 13:12:02 -0500 Becky Bruce <[email protected]>…
arch/powerpc/ renamed from arch/powerpc/include/asm/config.h +0 -0
include/asm/config.h
index fc3facb..01036f3 100644
arch/powerpc/include/asm/config.h +4 -0
@@ -76,4 +76,10 @@
 /* Relocation to SDRAM works on all PPC boards */
 #define CONFIG_RELOC_FIXUP_WORKS
 
+/* Most PPC SOCs have a LBC so define this here */
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
+	defined(CONFIG_MPC83xx)
+#define CONFIG_FSL_LBC
Instead of in the configs (such as what patch 1 in this series continues to do), can we do ELBC determination here, based on finer-grained configs such as 831x, 837x, etc?
arch/powerpc/include/asm/config.h line 83
Quoted 1 line
arch/powerpc/include/asm/config.h +1 -0
+#endif
Thanks,
Kim

Becky Bruce

author

2010-06-08 18:49 UTC #24 lore raw

PATCH v2 3/10 83xx/85xx/86xx: LBC register cleanup

Quoted 42 lines · Kim Phillips

Quoted 24 lines · On Tue, 8 Jun 2010 12:28:48 -0500 Becky Bruce <[email protected]>…
Quoted 12 lines · Kim Phillips
Quoted 3 lines · On Tue, 8 Jun 2010 11:15:07 -0500 Becky Bruce <[email protected]>…
This isn't *ELBC*, it's the existence of any sort of LBC. ELBC is determined per-board in the fine grained configs. There are 2 configs.
that's what I was suggesting to change; to group and centralize the definition of the two seemingly related configs - also because the ELBC
should be done at the SoC level.
Quoted 4 lines
See Scott's response though - I don't know how long the ELBC ifdef list
is, but introducing a header file per soc sounds like a bit out of scope for this patchseries - it already cleans up a bunch of stuff.
I think it is out of scope here - I think this is fine the way it is, at least for now. I'd like to get these cleanups in as soon as possible before someone else replicates more code.
Quoted 7 lines
We can post a followon later to change how we deal with ELBC/LBC; and
there are also more cleanups to be done - for example, there's still code that accesses lbc space not using IO accessors. I've cleaned up the BR/OR cases, but I want to eventually fix it all. Unfortunately, I'm out of time at this point. This patch series is a significant step forward, but there's still more work to be done.
ok but e.g., patch 1 in this series omits the MPC837XERDB, which needs to be fixed.
I was curious so I compiled the ELBC CONFIG_ list, in case you want to change patch 1 in the series to _delete_ the entries in the board configs and add them as pointed out in this patch:

Quoted 7 lines

MPC831x
MPC837x
MPC8536
MPC8569
MPC8572
and, of course, the Pxxxx's.

OK, thanks, I'll try to look at it probably tonight.

-Becky

Quoted 46 lines

Quoted 3 lines
Cheers,
Becky
Kim
Quoted 40 lines
Quoted 38 lines
Quoted 3 lines
-B
Kim
p.s. please don't top-post :).
Quoted 30 lines · Kim Phillips
Quoted 27 lines
arch/powerpc/include/asm/config.h line 82
Quoted 13 lines · On Wed, 2 Jun 2010 13:12:02 -0500 Becky Bruce <[email protected]>…
arch/powerpc/ renamed from arch/powerpc/include/asm/config.h +0 -0
include/asm/config.h
index fc3facb..01036f3 100644
arch/powerpc/include/asm/config.h +4 -0
@@ -76,4 +76,10 @@
 /* Relocation to SDRAM works on all PPC boards */
 #define CONFIG_RELOC_FIXUP_WORKS
 
+/* Most PPC SOCs have a LBC so define this here */
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
+	defined(CONFIG_MPC83xx)
+#define CONFIG_FSL_LBC
Instead of in the configs (such as what patch 1 in this series continues to do), can we do ELBC determination here, based on finer-grained configs such as 831x, 837x, etc?
arch/powerpc/include/asm/config.h line 83
Quoted 1 line
arch/powerpc/include/asm/config.h +1 -0
+#endif
Thanks,
Kim