ARM: S5PC100: Move external interrupt defines

index 71ae1f5..29a8a12 100644
@@ -146,13 +146,6 @@ enum s5p_gpio_number {
 /* define the number of gpios we need to the one after the MP04() range */
 #define ARCH_NR_GPIOS		(S5PC100_GPIO_END + 1)
 
-#define EINT_MODE		S3C_GPIO_SFN(0x2)
-
-#define EINT_GPIO_0(x)		S5PC100_GPH0(x)
-#define EINT_GPIO_1(x)		S5PC100_GPH1(x)
-#define EINT_GPIO_2(x)		S5PC100_GPH2(x)
-#define EINT_GPIO_3(x)		S5PC100_GPH3(x)
-
 #include <asm-generic/gpio.h>
 
 #endif /* __ASM_ARCH_GPIO_H */

index dd6295e..6abe481 100644
@@ -71,5 +71,12 @@
 #define S5P_EXTINT_RISEEDGE		(0x03)
 #define S5P_EXTINT_BOTHEDGE		(0x04)
 
+#define EINT_MODE		S3C_GPIO_SFN(0x2)
+
+#define EINT_GPIO_0(x)		S5PC100_GPH0(x)
+#define EINT_GPIO_1(x)		S5PC100_GPH1(x)
+#define EINT_GPIO_2(x)		S5PC100_GPH2(x)
+#define EINT_GPIO_3(x)		S5PC100_GPH3(x)
+
 #endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */
 

new file mode 100644
index 0000000..0c27a9d
@@ -0,0 +1,35 @@
+/*
+ * linux/arch/arm/plat-s5p/gpiolib.c
+ *
+ * Copyright (C) 2010 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <[email protected]>
+ *
+ * S5P - GPIOlib support
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/gpio.h>
+#include <mach/irqs.h>
+#include <mach/regs-gpio.h>
+
+/* be called from gpio_to_irq() for external interrupts */
+int s5p_gpiolib_eint_to_irq(struct gpio_chip *chip, unsigned int offset)
+{
+	switch (chip->base) {
+	case EINT_GPIO_0(0):
+		return IRQ_EINT(offset);
+	case EINT_GPIO_1(0):
+		return IRQ_EINT(8 + offset);
+	case EINT_GPIO_2(0):
+		return IRQ_EINT(16 + offset);
+	case EINT_GPIO_3(0):
+		return IRQ_EINT(24 + offset);
+	default:
+		return -EINVAL;
+	}
+}

index e358c7d..f6c5151 100644
@@ -121,6 +121,8 @@ extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
 /* exported for core SoC support to change */
 extern struct s3c_gpio_cfg s3c24xx_gpiocfg_default;
 
+extern int s5p_gpiolib_eint_to_irq(struct gpio_chip *chip, unsigned int offset);
+
 #ifdef CONFIG_S3C_GPIO_TRACK
 extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
 

index 9ea8972..5b73c3e 100644
@@ -213,6 +213,7 @@ static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
 			.base	= S5PV210_GPH0(0),
 			.ngpio	= S5PV210_GPIO_H0_NR,
 			.label	= "GPH0",
+			.to_irq = s5p_gpiolib_eint_to_irq,
 		},
 	}, {
 		.base	= (S5P_VA_GPIO + 0xC20),

@@ -221,6 +222,7 @@ static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
 			.base	= S5PV210_GPH1(0),
 			.ngpio	= S5PV210_GPIO_H1_NR,
 			.label	= "GPH1",
+			.to_irq = s5p_gpiolib_eint_to_irq,
 		},
 	}, {
 		.base	= (S5P_VA_GPIO + 0xC40),

@@ -229,6 +231,7 @@ static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
 			.base	= S5PV210_GPH2(0),
 			.ngpio	= S5PV210_GPIO_H2_NR,
 			.label	= "GPH2",
+			.to_irq = s5p_gpiolib_eint_to_irq,
 		},
 	}, {
 		.base	= (S5P_VA_GPIO + 0xC60),

@@ -237,6 +240,7 @@ static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
 			.base	= S5PV210_GPH3(0),
 			.ngpio	= S5PV210_GPIO_H3_NR,
 			.label	= "GPH3",
+			.to_irq = s5p_gpiolib_eint_to_irq,
 		},
 	},
 };

index 0fab7f2..60704ef 100644
@@ -66,25 +66,6 @@ static int s5pc100_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
 	return S3C_IRQ_GPIO(chip->base + offset);
 }
 
-static int s5pc100_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
-{
-	int base;
-
-	base = chip->base - S5PC100_GPH0(0);
-	if (base == 0)
-		return IRQ_EINT(offset);
-	base = chip->base - S5PC100_GPH1(0);
-	if (base == 0)
-		return IRQ_EINT(8 + offset);
-	base = chip->base - S5PC100_GPH2(0);
-	if (base == 0)
-		return IRQ_EINT(16 + offset);
-	base = chip->base - S5PC100_GPH3(0);
-	if (base == 0)
-		return IRQ_EINT(24 + offset);
-	return -EINVAL;
-}
-
 static struct s3c_gpio_cfg gpio_cfg = {
 	.set_config	= s3c_gpio_setcfg_s3c64xx_4bit,
 	.set_pull	= s3c_gpio_setpull_updown,

@@ -232,6 +213,7 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
 			.base	= S5PC100_GPH0(0),
 			.ngpio	= S5PC100_GPIO_H0_NR,
 			.label	= "GPH0",
+			.to_irq = s5p_gpiolib_eint_to_irq,
 		},
 	}, {
 		.base	= S5PC100_GPH1_BASE,

@@ -240,6 +222,7 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
 			.base	= S5PC100_GPH1(0),
 			.ngpio	= S5PC100_GPIO_H1_NR,
 			.label	= "GPH1",
+			.to_irq = s5p_gpiolib_eint_to_irq,
 		},
 	}, {
 		.base	= S5PC100_GPH2_BASE,

@@ -248,6 +231,7 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
 			.base	= S5PC100_GPH2(0),
 			.ngpio	= S5PC100_GPIO_H2_NR,
 			.label	= "GPH2",
+			.to_irq = s5p_gpiolib_eint_to_irq,
 		},
 	}, {
 		.base	= S5PC100_GPH3_BASE,

@@ -256,6 +240,7 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
 			.base	= S5PC100_GPH3(0),
 			.ngpio	= S5PC100_GPIO_H3_NR,
 			.label	= "GPH3",
+			.to_irq = s5p_gpiolib_eint_to_irq,
 		},
 	}, {
 		.base	= S5PC100_GPI_BASE,

@@ -399,8 +384,6 @@ static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip)
 			set_irq_handler(irq, handle_level_irq);
 			set_irq_flags(irq, IRQF_VALID);
 		}
-	} else if (chip->config == &gpio_cfg_eint) {
-		chip->chip.to_irq = s5pc100_gpiolib_to_eint;
 	}
 }
 

index 5b73c3e..166725f 100644
@@ -150,6 +150,7 @@ static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
 			.label	= "GPG3",
 		},
 	}, {
+		.config	= &gpio_cfg_noint,
 		.chip	= {
 			.base	= S5PV210_GPI(0),
 			.ngpio	= S5PV210_GPIO_I_NR,

@@ -249,11 +250,16 @@ static __init int s5pv210_gpiolib_init(void)
 {
 	struct s3c_gpio_chip *chip = s5pv210_gpio_4bit;
 	int nr_chips = ARRAY_SIZE(s5pv210_gpio_4bit);
+	int gpioint_group = 0;
 	int i = 0;
 
 	for (i = 0; i < nr_chips; i++, chip++) {
-		if (chip->config == NULL)
+		if (chip->config == NULL) {
 			chip->config = &gpio_cfg;
+
+			/* gpio interrupts */
+			s5p_gpioint_add(chip, gpioint_group++);
+		}
 		if (chip->base == NULL)
 			chip->base = S5PV210_BANK_BASE(i);
 	}

index 9689537..43baacc 100644
@@ -121,8 +121,22 @@
 #define S5P_EINT_BASE1		(S5P_IRQ_VIC0(0))
 #define S5P_EINT_BASE2		(IRQ_VIC_END + 1)
 
+/* GPIO interrupt */
+#define S5P_GPIOINT_GROUP_NR	22
+#define S5P_GPIOINT_BASE	(IRQ_EINT(31) + 1)
+#define S5P_IRQ_GPIOINT(x)	(S5P_GPIOINT_BASE + (x))
+
 /* Set the default NR_IRQS */
-#define NR_IRQS			(IRQ_EINT(31) + 1)
+
+/*
+ * GPIO groups is 27. Each GPIO group can have max 8 GPIO interrupts.
+ *
+ * We should include gpios of all gpio groups from GPIO_A0 until GPIO_J4 to
+ * NR_IRQS because 22 gpio groups having gpio interrupts aren't in order and
+ * are mixed with no interrupt gpio groups, then it can give simple irq
+ * computation of gpio interrupts.
+ */
+#define NR_IRQS			(S5P_IRQ_GPIOINT(27 * 8) + 1)
 
 /* Compatibility */
 #define IRQ_LCD_FIFO		IRQ_LCD0

208 lines not on this page · raw message

index f6c5151..a6b844c 100644
@@ -123,6 +123,8 @@ extern struct s3c_gpio_cfg s3c24xx_gpiocfg_default;
 
 extern int s5p_gpiolib_eint_to_irq(struct gpio_chip *chip, unsigned int offset);
 
+extern void s5p_gpioint_add(struct s3c_gpio_chip *chip, int group);
+
 #ifdef CONFIG_S3C_GPIO_TRACK
 extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
 

index 60704ef..a34a700 100644
@@ -63,7 +63,7 @@
 
 static int s5pc100_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
 {
-	return S3C_IRQ_GPIO(chip->base + offset);
+	return S5P_IRQ_GPIOINT(chip->base + offset);
 }
 
 static struct s3c_gpio_cfg gpio_cfg = {

@@ -365,45 +365,26 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
 	},
 };
 
-/* FIXME move from irq-gpio.c */
-extern struct irq_chip s5pc100_gpioint;
-extern void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
-
-static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip)
-{
-	/* Interrupt */
-	if (chip->config == &gpio_cfg) {
-		int i, irq;
-
-		chip->chip.to_irq = s5pc100_gpiolib_to_irq;
-
-		for (i = 0;  i < chip->chip.ngpio; i++) {
-			irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i;
-			set_irq_chip(irq, &s5pc100_gpioint);
-			set_irq_data(irq, &chip->chip);
-			set_irq_handler(irq, handle_level_irq);
-			set_irq_flags(irq, IRQF_VALID);
-		}
-	}
-}
-
 static __init int s5pc100_gpiolib_init(void)
 {
 	struct s3c_gpio_chip *chip;
 	int nr_chips;
+	int gpioint_group = 0;
 
 	chip = s5pc100_gpio_chips;
 	nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
 
-	for (; nr_chips > 0; nr_chips--, chip++)
-		s5pc100_gpiolib_link(chip);
+	for (; nr_chips > 0; nr_chips--, chip++) {
+		if (chip->config == &gpio_cfg) {
+			/* gpio interrupts */
+			chip->chip.to_irq = s5pc100_gpiolib_to_irq;
+			s5p_gpioint_add(chip, gpioint_group++);
+		}
+	}
 
 	samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips,
 				       ARRAY_SIZE(s5pc100_gpio_chips));
 
-	/* Interrupt */
-	set_irq_chained_handler(IRQ_GPIOINT, s5pc100_irq_gpioint_handler);
-
 	return 0;
 }
 core_initcall(s5pc100_gpiolib_init);

index 28aa551..8f725bd 100644
@@ -100,11 +100,21 @@
 #define S5P_EINT_BASE1		(S5P_IRQ_VIC0(0))
 #define S5P_EINT_BASE2		(IRQ_VIC_END + 1)
 
-#define S3C_IRQ_GPIO_BASE	(IRQ_EINT(31) + 1)
-#define S3C_IRQ_GPIO(x)		(S3C_IRQ_GPIO_BASE + (x))
+#define S5P_GPIOINT_GROUP_NR	21
+#define S5P_GPIOINT_BASE	(IRQ_EINT(31) + 1)
+#define S5P_IRQ_GPIOINT(x)	(S5P_GPIOINT_BASE + (x))
 
-/* Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs */
-#define NR_IRQS		(S3C_IRQ_GPIO(320) + 1)
+/* Set the default NR_IRQS */
+
+/*
+ * GPIO groups is 25. Each GPIO group can have max 8 GPIO interrupts.
+ *
+ * We should include gpios of all gpio groups from GPIO_A0 until GPIO_J4 to
+ * NR_IRQS because 21 gpio groups having gpio interrupts aren't in order and
+ * are mixed with no interrupt gpio groups, then it can give simple irq
+ * computation of gpio interrupts.
+ */
+#define NR_IRQS			(S5P_IRQ_GPIOINT(25 * 8) + 1)
 
 /* Compatibility */
 #define IRQ_LCD_FIFO		IRQ_LCD0

266 lines not on this page · raw message

index a34a700..2dcb501 100644
@@ -61,11 +61,6 @@
  * L3	8	4Bit	None
  */
 
-static int s5pc100_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
-{
-	return S5P_IRQ_GPIOINT(chip->base + offset);
-}
-
 static struct s3c_gpio_cfg gpio_cfg = {
 	.set_config	= s3c_gpio_setcfg_s3c64xx_4bit,
 	.set_pull	= s3c_gpio_setpull_updown,

@@ -377,7 +372,7 @@ static __init int s5pc100_gpiolib_init(void)
 	for (; nr_chips > 0; nr_chips--, chip++) {
 		if (chip->config == &gpio_cfg) {
 			/* gpio interrupts */
-			chip->chip.to_irq = s5pc100_gpiolib_to_irq;
+			chip->chip.to_irq = s5p_gpiolib_gpioint_to_irq;
 			s5p_gpioint_add(chip, gpioint_group++);
 		}
 	}

index 166725f..f4ac81f 100644
@@ -258,6 +258,7 @@ static __init int s5pv210_gpiolib_init(void)
 			chip->config = &gpio_cfg;
 
 			/* gpio interrupts */
+			chip->chip.to_irq = s5p_gpiolib_gpioint_to_irq;
 			s5p_gpioint_add(chip, gpioint_group++);
 		}
 		if (chip->base == NULL)

index 0c27a9d..dcd1ee4 100644
@@ -33,3 +33,10 @@ int s5p_gpiolib_eint_to_irq(struct gpio_chip *chip, unsigned int offset)
 		return -EINVAL;
 	}
 }
+
+/* be called from gpio_to_irq() for gpio interrupts */
+int s5p_gpiolib_gpioint_to_irq(struct gpio_chip *chip, unsigned int offset)
+{
+	return S5P_IRQ_GPIOINT(chip->base + offset);
+}
+

index a6b844c..d484aaf 100644
@@ -122,6 +122,8 @@ extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
 extern struct s3c_gpio_cfg s3c24xx_gpiocfg_default;
 
 extern int s5p_gpiolib_eint_to_irq(struct gpio_chip *chip, unsigned int offset);
+extern int s5p_gpiolib_gpioint_to_irq(struct gpio_chip *chip,
+		unsigned int offset);
 
 extern void s5p_gpioint_add(struct s3c_gpio_chip *chip, int group);