Support for board Calao USB A9263

index c520e89..73e23cf 100644
@@ -33,8 +33,6 @@ typedef struct at91_spi {
 	at91_pdc_t	pdc;
 } at91_spi_t;
 
-#ifdef CONFIG_AT91_LEGACY
-
 #define AT91_SPI_CR			0x00		/* Control Register */
 #define		AT91_SPI_SPIEN		(1 <<  0)		/* SPI Enable */
 #define		AT91_SPI_SPIDIS		(1 <<  1)		/* SPI Disable */

@@ -121,6 +119,4 @@ typedef struct at91_spi {
 
 #define AT91_SPI_PTSR		0x0124			/* PDC Transfer Status Register */
 
-#endif /* CONFIG_AT91_LEGACY */
-
 #endif

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index 73e23cf..e86212d 100644
@@ -33,90 +33,68 @@ typedef struct at91_spi {
 	at91_pdc_t	pdc;
 } at91_spi_t;
 
-#define AT91_SPI_CR			0x00		/* Control Register */
-#define		AT91_SPI_SPIEN		(1 <<  0)		/* SPI Enable */
-#define		AT91_SPI_SPIDIS		(1 <<  1)		/* SPI Disable */
-#define		AT91_SPI_SWRST		(1 <<  7)		/* SPI Software Reset */
-#define		AT91_SPI_LASTXFER	(1 << 24)		/* Last Transfer [SAM9261 only] */
-
-#define AT91_SPI_MR			0x04		/* Mode Register */
-#define		AT91_SPI_MSTR		(1    <<  0)		/* Master/Slave Mode */
-#define		AT91_SPI_PS		(1    <<  1)		/* Peripheral Select */
-#define			AT91_SPI_PS_FIXED	(0 << 1)
-#define			AT91_SPI_PS_VARIABLE	(1 << 1)
-#define		AT91_SPI_PCSDEC		(1    <<  2)		/* Chip Select Decode */
-#define		AT91_SPI_DIV32		(1    <<  3)		/* Clock Selection [AT91RM9200 only] */
-#define		AT91_SPI_MODFDIS	(1    <<  4)		/* Mode Fault Detection */
-#define		AT91_SPI_LLB		(1    <<  7)		/* Local Loopback Enable */
-#define		AT91_SPI_PCS		(0xf  << 16)		/* Peripheral Chip Select */
-#define		AT91_SPI_DLYBCS		(0xff << 24)		/* Delay Between Chip Selects */
-
-#define AT91_SPI_RDR		0x08			/* Receive Data Register */
-#define		AT91_SPI_RD		(0xffff <<  0)		/* Receive Data */
-#define		AT91_SPI_PCS		(0xf	<< 16)		/* Peripheral Chip Select */
-
-#define AT91_SPI_TDR		0x0c			/* Transmit Data Register */
-#define		AT91_SPI_TD		(0xffff <<  0)		/* Transmit Data */
-#define		AT91_SPI_PCS		(0xf	<< 16)		/* Peripheral Chip Select */
-#define		AT91_SPI_LASTXFER	(1	<< 24)		/* Last Transfer [SAM9261 only] */
-
-#define AT91_SPI_SR		0x10			/* Status Register */
-#define		AT91_SPI_RDRF		(1 <<  0)		/* Receive Data Register Full */
-#define		AT91_SPI_TDRE		(1 <<  1)		/* Transmit Data Register Full */
-#define		AT91_SPI_MODF		(1 <<  2)		/* Mode Fault Error */
-#define		AT91_SPI_OVRES		(1 <<  3)		/* Overrun Error Status */
-#define		AT91_SPI_ENDRX		(1 <<  4)		/* End of RX buffer */
-#define		AT91_SPI_ENDTX		(1 <<  5)		/* End of TX buffer */
-#define		AT91_SPI_RXBUFF		(1 <<  6)		/* RX Buffer Full */
-#define		AT91_SPI_TXBUFE		(1 <<  7)		/* TX Buffer Empty */
-#define		AT91_SPI_NSSR		(1 <<  8)		/* NSS Rising [SAM9261 only] */
-#define		AT91_SPI_TXEMPTY	(1 <<  9)		/* Transmission Register Empty [SAM9261 only] */
-#define		AT91_SPI_SPIENS		(1 << 16)		/* SPI Enable Status */
-
-#define AT91_SPI_IER		0x14			/* Interrupt Enable Register */
-#define AT91_SPI_IDR		0x18			/* Interrupt Disable Register */
-#define AT91_SPI_IMR		0x1c			/* Interrupt Mask Register */
-
-#define AT91_SPI_CSR(n)		(0x30 + ((n) * 4))	/* Chip Select Registers 0-3 */
-#define		AT91_SPI_CPOL		(1    <<  0)		/* Clock Polarity */
-#define		AT91_SPI_NCPHA		(1    <<  1)		/* Clock Phase */
-#define		AT91_SPI_CSAAT		(1    <<  3)		/* Chip Select Active After Transfer [SAM9261 only] */
-#define		AT91_SPI_BITS		(0xf  <<  4)		/* Bits Per Transfer */
-#define			AT91_SPI_BITS_8		(0 << 4)
-#define			AT91_SPI_BITS_9		(1 << 4)
-#define			AT91_SPI_BITS_10	(2 << 4)
-#define			AT91_SPI_BITS_11	(3 << 4)
-#define			AT91_SPI_BITS_12	(4 << 4)
-#define			AT91_SPI_BITS_13	(5 << 4)
-#define			AT91_SPI_BITS_14	(6 << 4)
-#define			AT91_SPI_BITS_15	(7 << 4)
-#define			AT91_SPI_BITS_16	(8 << 4)
-#define		AT91_SPI_SCBR		(0xff <<  8)		/* Serial Clock Baud Rate */
-#define		AT91_SPI_DLYBS		(0xff << 16)		/* Delay before SPCK */
-#define		AT91_SPI_DLYBCT		(0xff << 24)		/* Delay between Consecutive Transfers */
-
-#define AT91_SPI_RPR		0x0100			/* Receive Pointer Register */
-
-#define AT91_SPI_RCR		0x0104			/* Receive Counter Register */
-
-#define AT91_SPI_TPR		0x0108			/* Transmit Pointer Register */
-
-#define AT91_SPI_TCR		0x010c			/* Transmit Counter Register */
-
-#define AT91_SPI_RNPR		0x0110			/* Receive Next Pointer Register */
-
-#define AT91_SPI_RNCR		0x0114			/* Receive Next Counter Register */
-
-#define AT91_SPI_TNPR		0x0118			/* Transmit Next Pointer Register */
-
-#define AT91_SPI_TNCR		0x011c			/* Transmit Next Counter Register */
-
-#define AT91_SPI_PTCR		0x0120			/* PDC Transfer Control Register */
-#define		AT91_SPI_RXTEN		(0x1 << 0)		/* Receiver Transfer Enable */
-#define		AT91_SPI_RXTDIS		(0x1 << 1)		/* Receiver Transfer Disable */
-#define		AT91_SPI_TXTEN		(0x1 << 8)		/* Transmitter Transfer Enable */
-#define		AT91_SPI_TXTDIS		(0x1 << 9)		/* Transmitter Transfer Disable */
-
-#define AT91_SPI_PTSR		0x0124			/* PDC Transfer Status Register */
+/* Control Register bits */
+#define AT91_SPI_SPIEN        (1 <<  0)      /* SPI Enable */
+#define AT91_SPI_SPIDIS       (1 <<  1)      /* SPI Disable */
+#define AT91_SPI_SWRST        (1 <<  7)      /* SPI Software Reset */
+#define AT91_SPI_LASTXFER     (1 << 24)      /* Last Transfer [SAM9261 only] */
+
+/* Mode Register bits */
+#define AT91_SPI_MSTR         (1    <<  0)   /* Master/Slave Mode */
+#define AT91_SPI_PS           (1    <<  1)   /* Peripheral Select */
+#define  AT91_SPI_PS_FIXED        (0 << 1)
+#define  AT91_SPI_PS_VARIABLE     (1 << 1)
+#define AT91_SPI_PCSDEC       (1    <<  2)   /* Chip Select Decode */
+#define AT91_SPI_DIV32        (1    <<  3)   /* Clock Selection [AT91RM9200 only] */
+#define AT91_SPI_MODFDIS      (1    <<  4)   /* Mode Fault Detection */
+#define AT91_SPI_LLB          (1    <<  7)   /* Local Loopback Enable */
+#define AT91_SPI_PCS          (0xf  << 16)   /* Peripheral Chip Select */
+#define AT91_SPI_DLYBCS       (0xff << 24)   /* Delay Between Chip Selects */
+
+/* Receive data register bits */
+#define AT91_SPI_RD           (0xffff <<  0) /* Receive Data */
+#define AT91_SPI_PCS          (0xf    << 16) /* Peripheral Chip Select */
+
+/* Transmit Data Register bits */
+#define AT91_SPI_TD           (0xffff <<  0) /* Transmit Data */
+#define AT91_SPI_PCS          (0xf    << 16) /* Peripheral Chip Select */
+#define AT91_SPI_LASTXFER     (1      << 24) /* Last Transfer [SAM9261 only] */
+
+/* Status Register bits */
+#define AT91_SPI_RDRF         (1 <<  0)      /* Receive Data Register Full */
+#define AT91_SPI_TDRE         (1 <<  1)      /* Transmit Data Register Full */
+#define AT91_SPI_MODF         (1 <<  2)      /* Mode Fault Error */
+#define AT91_SPI_OVRES        (1 <<  3)      /* Overrun Error Status */
+#define AT91_SPI_ENDRX        (1 <<  4)      /* End of RX buffer */
+#define AT91_SPI_ENDTX        (1 <<  5)      /* End of TX buffer */
+#define AT91_SPI_RXBUFF       (1 <<  6)      /* RX Buffer Full */
+#define AT91_SPI_TXBUFE       (1 <<  7)      /* TX Buffer Empty */
+#define AT91_SPI_NSSR         (1 <<  8)      /* NSS Rising [SAM9261 only] */
+#define AT91_SPI_TXEMPTY      (1 <<  9)      /* Transmission Register Empty [SAM9261 only] */
+#define AT91_SPI_SPIENS       (1 << 16)      /* SPI Enable Status */
+
+/* Chip Select Registers bits */
+#define AT91_SPI_CPOL         (1    <<  0)   /* Clock Polarity */
+#define AT91_SPI_NCPHA        (1    <<  1)   /* Clock Phase */
+#define AT91_SPI_CSAAT        (1    <<  3)   /* Chip Select Active After Transfer [SAM9261 only] */
+#define AT91_SPI_BITS         (0xf  <<  4)   /* Bits Per Transfer */
+#define  AT91_SPI_BITS_8          (0 << 4)
+#define  AT91_SPI_BITS_9          (1 << 4)
+#define  AT91_SPI_BITS_10         (2 << 4)
+#define  AT91_SPI_BITS_11         (3 << 4)
+#define  AT91_SPI_BITS_12         (4 << 4)
+#define  AT91_SPI_BITS_13         (5 << 4)
+#define  AT91_SPI_BITS_14         (6 << 4)
+#define  AT91_SPI_BITS_15         (7 << 4)
+#define  AT91_SPI_BITS_16         (8 << 4)
+#define AT91_SPI_SCBR         (0xff <<  8)   /* Serial Clock Baud Rate */
+#define AT91_SPI_DLYBS        (0xff << 16)   /* Delay before SPCK */
+#define AT91_SPI_DLYBCT       (0xff << 24)   /* Delay between Consecutive Transfers */
+
+/* PDC Transfer Control Register bits */
+#define AT91_SPI_RXTEN        (0x1 << 0)     /* Receiver Transfer Enable */
+#define AT91_SPI_RXTDIS       (0x1 << 1)     /* Receiver Transfer Disable */
+#define AT91_SPI_TXTEN        (0x1 << 8)     /* Transmitter Transfer Enable */
+#define AT91_SPI_TXTDIS       (0x1 << 9)     /* Transmitter Transfer Disable */
 
 #endif

index 4ada1ce..d6c8982 100644
@@ -47,6 +47,7 @@
 #define AT91SAM9263_ID_IRQ0	30	/* Advanced Interrupt Controller (IRQ0) */
 #define AT91SAM9263_ID_IRQ1	31	/* Advanced Interrupt Controller (IRQ1) */
 
+#define AT91_SPI0_BASE		0xfffa4000
 #define AT91_EMAC_BASE		0xfffbc000
 #define AT91_ECC0_BASE		0xffffe000
 #define AT91_SDRAMC0_BASE	0xffffe200

new file mode 100644
index 0000000..614ef0d
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2008-2009
+ * Ulf Samuelsson <[email protected]>
+ * Thomas Petazzoni, Free Electrons, <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x00001FFF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00002000, 0x00003FFF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00004000, 0xFFFFFFFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+};

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index c520e89..73e23cf 100644
@@ -33,8 +33,6 @@ typedef struct at91_spi {
 	at91_pdc_t	pdc;
 } at91_spi_t;
 
-#ifdef CONFIG_AT91_LEGACY
-
 #define AT91_SPI_CR			0x00		/* Control Register */
 #define		AT91_SPI_SPIEN		(1 <<  0)		/* SPI Enable */
 #define		AT91_SPI_SPIDIS		(1 <<  1)		/* SPI Disable */

@@ -121,6 +119,4 @@ typedef struct at91_spi {
 
 #define AT91_SPI_PTSR		0x0124			/* PDC Transfer Status Register */
 
-#endif /* CONFIG_AT91_LEGACY */
-
 #endif

185 lines not on this page · raw message

index 73e23cf..0046256 100644
@@ -33,90 +33,73 @@ typedef struct at91_spi {
 	at91_pdc_t	pdc;
 } at91_spi_t;
 
-#define AT91_SPI_CR			0x00		/* Control Register */
-#define		AT91_SPI_SPIEN		(1 <<  0)		/* SPI Enable */
-#define		AT91_SPI_SPIDIS		(1 <<  1)		/* SPI Disable */
-#define		AT91_SPI_SWRST		(1 <<  7)		/* SPI Software Reset */
-#define		AT91_SPI_LASTXFER	(1 << 24)		/* Last Transfer [SAM9261 only] */
-
-#define AT91_SPI_MR			0x04		/* Mode Register */
-#define		AT91_SPI_MSTR		(1    <<  0)		/* Master/Slave Mode */
-#define		AT91_SPI_PS		(1    <<  1)		/* Peripheral Select */
-#define			AT91_SPI_PS_FIXED	(0 << 1)
-#define			AT91_SPI_PS_VARIABLE	(1 << 1)
-#define		AT91_SPI_PCSDEC		(1    <<  2)		/* Chip Select Decode */
-#define		AT91_SPI_DIV32		(1    <<  3)		/* Clock Selection [AT91RM9200 only] */
-#define		AT91_SPI_MODFDIS	(1    <<  4)		/* Mode Fault Detection */
-#define		AT91_SPI_LLB		(1    <<  7)		/* Local Loopback Enable */
-#define		AT91_SPI_PCS		(0xf  << 16)		/* Peripheral Chip Select */
-#define		AT91_SPI_DLYBCS		(0xff << 24)		/* Delay Between Chip Selects */
-
-#define AT91_SPI_RDR		0x08			/* Receive Data Register */
-#define		AT91_SPI_RD		(0xffff <<  0)		/* Receive Data */
-#define		AT91_SPI_PCS		(0xf	<< 16)		/* Peripheral Chip Select */
-
-#define AT91_SPI_TDR		0x0c			/* Transmit Data Register */
-#define		AT91_SPI_TD		(0xffff <<  0)		/* Transmit Data */
-#define		AT91_SPI_PCS		(0xf	<< 16)		/* Peripheral Chip Select */
-#define		AT91_SPI_LASTXFER	(1	<< 24)		/* Last Transfer [SAM9261 only] */
-
-#define AT91_SPI_SR		0x10			/* Status Register */
-#define		AT91_SPI_RDRF		(1 <<  0)		/* Receive Data Register Full */
-#define		AT91_SPI_TDRE		(1 <<  1)		/* Transmit Data Register Full */
-#define		AT91_SPI_MODF		(1 <<  2)		/* Mode Fault Error */
-#define		AT91_SPI_OVRES		(1 <<  3)		/* Overrun Error Status */
-#define		AT91_SPI_ENDRX		(1 <<  4)		/* End of RX buffer */
-#define		AT91_SPI_ENDTX		(1 <<  5)		/* End of TX buffer */
-#define		AT91_SPI_RXBUFF		(1 <<  6)		/* RX Buffer Full */
-#define		AT91_SPI_TXBUFE		(1 <<  7)		/* TX Buffer Empty */
-#define		AT91_SPI_NSSR		(1 <<  8)		/* NSS Rising [SAM9261 only] */
-#define		AT91_SPI_TXEMPTY	(1 <<  9)		/* Transmission Register Empty [SAM9261 only] */
-#define		AT91_SPI_SPIENS		(1 << 16)		/* SPI Enable Status */
-
-#define AT91_SPI_IER		0x14			/* Interrupt Enable Register */
-#define AT91_SPI_IDR		0x18			/* Interrupt Disable Register */
-#define AT91_SPI_IMR		0x1c			/* Interrupt Mask Register */
-
-#define AT91_SPI_CSR(n)		(0x30 + ((n) * 4))	/* Chip Select Registers 0-3 */
-#define		AT91_SPI_CPOL		(1    <<  0)		/* Clock Polarity */
-#define		AT91_SPI_NCPHA		(1    <<  1)		/* Clock Phase */
-#define		AT91_SPI_CSAAT		(1    <<  3)		/* Chip Select Active After Transfer [SAM9261 only] */
-#define		AT91_SPI_BITS		(0xf  <<  4)		/* Bits Per Transfer */
-#define			AT91_SPI_BITS_8		(0 << 4)
-#define			AT91_SPI_BITS_9		(1 << 4)
-#define			AT91_SPI_BITS_10	(2 << 4)
-#define			AT91_SPI_BITS_11	(3 << 4)
-#define			AT91_SPI_BITS_12	(4 << 4)
-#define			AT91_SPI_BITS_13	(5 << 4)
-#define			AT91_SPI_BITS_14	(6 << 4)
-#define			AT91_SPI_BITS_15	(7 << 4)
-#define			AT91_SPI_BITS_16	(8 << 4)
-#define		AT91_SPI_SCBR		(0xff <<  8)		/* Serial Clock Baud Rate */
-#define		AT91_SPI_DLYBS		(0xff << 16)		/* Delay before SPCK */
-#define		AT91_SPI_DLYBCT		(0xff << 24)		/* Delay between Consecutive Transfers */
-
-#define AT91_SPI_RPR		0x0100			/* Receive Pointer Register */
-
-#define AT91_SPI_RCR		0x0104			/* Receive Counter Register */
-
-#define AT91_SPI_TPR		0x0108			/* Transmit Pointer Register */
-
-#define AT91_SPI_TCR		0x010c			/* Transmit Counter Register */
-
-#define AT91_SPI_RNPR		0x0110			/* Receive Next Pointer Register */
-
-#define AT91_SPI_RNCR		0x0114			/* Receive Next Counter Register */
-
-#define AT91_SPI_TNPR		0x0118			/* Transmit Next Pointer Register */
-
-#define AT91_SPI_TNCR		0x011c			/* Transmit Next Counter Register */
-
-#define AT91_SPI_PTCR		0x0120			/* PDC Transfer Control Register */
-#define		AT91_SPI_RXTEN		(0x1 << 0)		/* Receiver Transfer Enable */
-#define		AT91_SPI_RXTDIS		(0x1 << 1)		/* Receiver Transfer Disable */
-#define		AT91_SPI_TXTEN		(0x1 << 8)		/* Transmitter Transfer Enable */
-#define		AT91_SPI_TXTDIS		(0x1 << 9)		/* Transmitter Transfer Disable */
-
-#define AT91_SPI_PTSR		0x0124			/* PDC Transfer Status Register */
+/* Control Register bits */
+#define AT91_SPI_SPIEN        (1 <<  0)      /* SPI Enable */
+#define AT91_SPI_SPIDIS       (1 <<  1)      /* SPI Disable */
+#define AT91_SPI_SWRST        (1 <<  7)      /* SPI Software Reset */
+#define AT91_SPI_LASTXFER     (1 << 24)      /* Last Transfer [SAM9261 only] */
+
+/* Mode Register bits */
+#define AT91_SPI_MSTR         (1    <<  0)   /* Master/Slave Mode */
+#define AT91_SPI_PS           (1    <<  1)   /* Peripheral Select */
+#define  AT91_SPI_PS_FIXED        (0 << 1)
+#define  AT91_SPI_PS_VARIABLE     (1 << 1)
+#define AT91_SPI_PCSDEC       (1    <<  2)   /* Chip Select Decode */
+#define AT91_SPI_DIV32        (1    <<  3)   /* Clock Selection
+						[AT91RM9200 only] */
+#define AT91_SPI_MODFDIS      (1    <<  4)   /* Mode Fault Detection */
+#define AT91_SPI_LLB          (1    <<  7)   /* Local Loopback Enable */
+#define AT91_SPI_PCS          (0xf  << 16)   /* Peripheral Chip Select */
+#define AT91_SPI_DLYBCS       (0xff << 24)   /* Delay Between Chip Selects */
+
+/* Receive data register bits */
+#define AT91_SPI_RD           (0xffff <<  0) /* Receive Data */
+#define AT91_SPI_PCS          (0xf    << 16) /* Peripheral Chip Select */
+
+/* Transmit Data Register bits */
+#define AT91_SPI_TD           (0xffff <<  0) /* Transmit Data */
+#define AT91_SPI_PCS          (0xf    << 16) /* Peripheral Chip Select */
+#define AT91_SPI_LASTXFER     (1      << 24) /* Last Transfer [SAM9261 only] */
+
+/* Status Register bits */
+#define AT91_SPI_RDRF         (1 <<  0)      /* Receive Data Register Full */
+#define AT91_SPI_TDRE         (1 <<  1)      /* Transmit Data Register Full */
+#define AT91_SPI_MODF         (1 <<  2)      /* Mode Fault Error */
+#define AT91_SPI_OVRES        (1 <<  3)      /* Overrun Error Status */
+#define AT91_SPI_ENDRX        (1 <<  4)      /* End of RX buffer */
+#define AT91_SPI_ENDTX        (1 <<  5)      /* End of TX buffer */
+#define AT91_SPI_RXBUFF       (1 <<  6)      /* RX Buffer Full */
+#define AT91_SPI_TXBUFE       (1 <<  7)      /* TX Buffer Empty */
+#define AT91_SPI_NSSR         (1 <<  8)      /* NSS Rising [SAM9261 only] */
+#define AT91_SPI_TXEMPTY      (1 <<  9)      /* Transmission Register
+						Empty [SAM9261 only] */
+#define AT91_SPI_SPIENS       (1 << 16)      /* SPI Enable Status */
+
+/* Chip Select Registers bits */
+#define AT91_SPI_CPOL         (1    <<  0)   /* Clock Polarity */
+#define AT91_SPI_NCPHA        (1    <<  1)   /* Clock Phase */
+#define AT91_SPI_CSAAT        (1    <<  3)   /* Chip Select Active
+						After Transfer
+						[SAM9261 only] */
+#define AT91_SPI_BITS         (0xf  <<  4)   /* Bits Per Transfer */
+#define  AT91_SPI_BITS_8          (0 << 4)
+#define  AT91_SPI_BITS_9          (1 << 4)
+#define  AT91_SPI_BITS_10         (2 << 4)
+#define  AT91_SPI_BITS_11         (3 << 4)
+#define  AT91_SPI_BITS_12         (4 << 4)
+#define  AT91_SPI_BITS_13         (5 << 4)
+#define  AT91_SPI_BITS_14         (6 << 4)
+#define  AT91_SPI_BITS_15         (7 << 4)
+#define  AT91_SPI_BITS_16         (8 << 4)
+#define AT91_SPI_SCBR         (0xff <<  8)   /* Serial Clock Baud Rate */
+#define AT91_SPI_DLYBS        (0xff << 16)   /* Delay before SPCK */
+#define AT91_SPI_DLYBCT       (0xff << 24)   /* Delay between Consecutive
+						Transfers */
+
+/* PDC Transfer Control Register bits */
+#define AT91_SPI_RXTEN        (0x1 << 0)     /* Receiver Transfer Enable */
+#define AT91_SPI_RXTDIS       (0x1 << 1)     /* Receiver Transfer Disable */
+#define AT91_SPI_TXTEN        (0x1 << 8)     /* Transmitter Transfer Enable */
+#define AT91_SPI_TXTDIS       (0x1 << 9)     /* Transmitter Transfer Disable */
 
 #endif

index 5af6fdc..732ee95 100644
@@ -53,6 +53,7 @@
 #define AT91CAP9_ID_IRQ0	30	/* Advanced Interrupt Controller (IRQ0) */
 #define AT91CAP9_ID_IRQ1	31	/* Advanced Interrupt Controller (IRQ1) */
 
+#define AT91_SPI0_BASE	0xfffa4000
 #define AT91_PIO_BASE	0xfffff200
 #define AT91_PMC_BASE	0xfffffc00
 #define AT91_RSTC_BASE	0xfffffd00

index ec04318..fda8e59 100644
@@ -50,6 +50,7 @@
 #define AT91SAM9260_ID_IRQ2	31	/* Advanced Interrupt Controller (IRQ2) */
 
 #define AT91_EMAC_BASE		0xfffc4000
+#define AT91_SPI0_BASE		0xfffc8000
 #define AT91_SDRAMC_BASE	0xffffea00
 #define AT91_SMC_BASE		0xffffec00
 #define AT91_MATRIX_BASE	0xffffee00

index 7ca0283..ef57403 100644
@@ -43,6 +43,7 @@
 #define AT91SAM9261_ID_IRQ1	30	/* Advanced Interrupt Controller (IRQ1) */
 #define AT91SAM9261_ID_IRQ2	31	/* Advanced Interrupt Controller (IRQ2) */
 
+#define AT91_SPI0_BASE		0xfffc8000
 #define AT91_SDRAMC_BASE	0xffffea00
 #define AT91_SMC_BASE		0xffffec00
 #define AT91_MATRIX_BASE	0xffffee00

index 4ada1ce..d6c8982 100644
@@ -47,6 +47,7 @@
 #define AT91SAM9263_ID_IRQ0	30	/* Advanced Interrupt Controller (IRQ0) */
 #define AT91SAM9263_ID_IRQ1	31	/* Advanced Interrupt Controller (IRQ1) */
 
+#define AT91_SPI0_BASE		0xfffa4000
 #define AT91_EMAC_BASE		0xfffbc000
 #define AT91_ECC0_BASE		0xffffe000
 #define AT91_SDRAMC0_BASE	0xffffe200

index 445f4b2..9bf4149 100644
@@ -51,6 +51,7 @@
 #define AT91SAM9G45_ID_VDEC	30	/* Video Decoder */
 #define AT91SAM9G45_ID_IRQ0	31	/* Advanced Interrupt Controller */
 
+#define AT91_SPI0_BASE		0xfffa4000
 #define AT91_EMAC_BASE		0xfffbc000
 #define AT91_SMC_BASE		0xffffe800
 #define AT91_MATRIX_BASE	0xffffea00

index 8eb0d4f..5807cd2 100644
@@ -44,6 +44,7 @@
 #define AT91SAM9RL_ID_AC97C	24	/* AC97 Controller */
 #define AT91SAM9RL_ID_IRQ0	31	/* Advanced Interrupt Controller (IRQ0) */
 
+#define AT91_SPI0_BASE		0xfffcc000
 #define AT91_SDRAMC_BASE	0xffffea00
 #define AT91_SMC_BASE		0xffffec00
 #define AT91_MATRIX_BASE	0xffffee00

new file mode 100644
index 0000000..614ef0d
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2008-2009
+ * Ulf Samuelsson <[email protected]>
+ * Thomas Petazzoni, Free Electrons, <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x00001FFF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00002000, 0x00003FFF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00004000, 0xFFFFFFFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+};

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