Save/restore MISC_ENABLE register

RFC PATCH In review Ondrej Zary 4 participants 11 messages Jun 7, 2010

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Ondrej Zary

author

2010-06-07 16:15 UTC #0 lore raw

RFC PATCH 1/1 Save/restore MISC_ENABLE register

Save/restore MISC_ENABLE register on suspend/resume.
This fixes OOPS (invalid opcode) on resume from STR on Asus P4P800-VM, which wakes up with MWAIT disabled.

Is this a correct thing to do? Is it OK on x86_64?

Signed-off-by Ondrej Zary <[email protected]>

arch/x86/include/asm/suspend_32.h +1 -0

diff -urp linux-2.6.35-rc1-git2-orig/arch/x86/include/asm/suspend_32.h linux-2.6.35-rc1-git2/arch/x86/include/asm/suspend_32.h
@@ -15,6 +15,7 @@ static inline int arch_prepare_suspend(v
 struct saved_context {
 	u16 es, fs, gs, ss;
 	unsigned long cr0, cr2, cr3, cr4;
+	unsigned long misc_enable;
 	struct desc_ptr gdt;
 	struct desc_ptr idt;
 	u16 ldt;

arch/x86/include/asm/suspend_64.h +1 -0

diff -urp linux-2.6.35-rc1-git2-orig/arch/x86/include/asm/suspend_64.h linux-2.6.35-rc1-git2/arch/x86/include/asm/suspend_64.h
@@ -27,6 +27,7 @@ struct saved_context {
 	u16 ds, es, fs, gs, ss;
 	unsigned long gs_base, gs_kernel_base, fs_base;
 	unsigned long cr0, cr2, cr3, cr4, cr8;
+	unsigned long misc_enable;
 	unsigned long efer;
 	u16 gdt_pad;
 	u16 gdt_limit;

arch/x86/power/cpu.c +2 -0

diff -urp linux-2.6.35-rc1-git2-orig/arch/x86/power/cpu.c linux-2.6.35-rc1-git2/arch/x86/power/cpu.c
@@ -105,6 +105,7 @@ static void __save_processor_state(struc
 	ctxt->cr4 = read_cr4();
 	ctxt->cr8 = read_cr8();
 #endif
+	rdmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
 }
 
 /* Needed by apm.c */

@@ -152,6 +153,7 @@ static void fix_processor_context(void)
  */
 static void __restore_processor_state(struct saved_context *ctxt)
 {
+	wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
 	/*
 	 * control registers
 	 */

Signature · 1 line

Ondrej Zary

H. Peter Anvin

reviewer

2010-06-07 17:27 UTC #1 lore raw

Quoted 5 lines · Ondrej Zary

Save/restore MISC_ENABLE register on suspend/resume.
This fixes OOPS (invalid opcode) on resume from STR on Asus P4P800-VM, which wakes up with MWAIT disabled.
Is this a correct thing to do? Is it OK on x86_64?

This MSR isn't available on all processors, and thus cannot be saved and restored unconditionally like this. On the save path, one can use rdmsr_safe(); on the wakeup path it's not clear to me it is safe to do so, so it would be better to save a presence flag on the save path and conditionalize the write.

-hpa

Ondrej Zary

author

2010-06-07 18:51 UTC #2 lore raw

Quoted 5 lines · On Monday 07 June 2010 19:27:23 H. Peter Anvin wrote:

Quoted 4 lines · Ondrej Zary
Save/restore MISC_ENABLE register on suspend/resume.
This fixes OOPS (invalid opcode) on resume from STR on Asus P4P800-VM, which wakes up with MWAIT disabled.

Quoted 7 lines

Quoted 1 line
Is this a correct thing to do? Is it OK on x86_64?
This MSR isn't available on all processors, and thus cannot be saved and restored unconditionally like this. On the save path, one can use rdmsr_safe(); on the wakeup path it's not clear to me it is safe to do so, so it would be better to save a presence flag on the save path and conditionalize the write.

Something like this?

Save/restore MISC_ENABLE register on suspend/resume.
This fixes OOPS (invalid opcode) on resume from STR on Asus P4P800-VM, which wakes up with MWAIT disabled.

Signed-off-by Ondrej Zary <[email protected]>

arch/x86//include/asm/suspend_32.h +2 -0

diff -urp linux-2.6.35-rc1-git2-orig/arch/x86//include/asm/suspend_32.h linux-2.6.35-rc1-git2/arch/x86//include/asm/suspend_32.h
@@ -15,6 +15,8 @@ static inline int arch_prepare_suspend(v
 struct saved_context {
 	u16 es, fs, gs, ss;
 	unsigned long cr0, cr2, cr3, cr4;
+	u64 misc_enable;
+	bool misc_enable_saved;
 	struct desc_ptr gdt;
 	struct desc_ptr idt;
 	u16 ldt;

arch/x86//include/asm/suspend_64.h +2 -0

diff -urp linux-2.6.35-rc1-git2-orig/arch/x86//include/asm/suspend_64.h linux-2.6.35-rc1-git2/arch/x86//include/asm/suspend_64.h
@@ -27,6 +27,8 @@ struct saved_context {
 	u16 ds, es, fs, gs, ss;
 	unsigned long gs_base, gs_kernel_base, fs_base;
 	unsigned long cr0, cr2, cr3, cr4, cr8;
+	u64 misc_enable;
+	bool misc_enable_saved;
 	unsigned long efer;
 	u16 gdt_pad;
 	u16 gdt_limit;

arch/x86//power/cpu.c +4 -0

diff -urp linux-2.6.35-rc1-git2-orig/arch/x86//power/cpu.c linux-2.6.35-rc1-git2/arch/x86//power/cpu.c
@@ -105,6 +105,8 @@ static void __save_processor_state(struc
 	ctxt->cr4 = read_cr4();
 	ctxt->cr8 = read_cr8();
 #endif
+	ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
+					       &ctxt->misc_enable);
 }
 
 /* Needed by apm.c */

@@ -152,6 +154,8 @@ static void fix_processor_context(void)
  */
 static void __restore_processor_state(struct saved_context *ctxt)
 {
+	if (ctxt->misc_enable_saved)
+		wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
 	/*
 	 * control registers
 	 */

Signature · 1 line

Ondrej Zary

H. Peter Anvin

reviewer

2010-06-07 18:53 UTC #3 lore raw

Quoted 9 lines · Ondrej Zary

Something like this?
Save/restore MISC_ENABLE register on suspend/resume.
This fixes OOPS (invalid opcode) on resume from STR on Asus P4P800-VM, which wakes up with MWAIT disabled.
Signed-off-by Ondrej Zary <[email protected]>

Yes, that's a lot better.

I presume you have tested it. Rafael, do you want to take this or should I?

-hpa

Ondrej Zary

author

2010-06-07 19:02 UTC #4 lore raw

Quoted 7 lines · On Monday 07 June 2010 20:53:38 H. Peter Anvin wrote:

Quoted 6 lines · Ondrej Zary
Something like this?
Save/restore MISC_ENABLE register on suspend/resume.
This fixes OOPS (invalid opcode) on resume from STR on Asus P4P800-VM, which wakes up with MWAIT disabled.

Quoted 6 lines

Quoted 1 line
Signed-off-by Ondrej Zary <[email protected]>
Yes, that's a lot better.
I presume you have tested it. Rafael, do you want to take this or should I?

Yes, it works on the P4P800-VM. Don't have any x86_64 machine to test.

Signature · 1 line

Ondrej Zary

Ondrej Zary

author

2010-06-07 19:02 UTC #5 lore raw

In reply to H. Peter Anvin

Quoted 7 lines · On Monday 07 June 2010 20:53:38 H. Peter Anvin wrote:

Quoted 6 lines · Ondrej Zary
Something like this?
Save/restore MISC_ENABLE register on suspend/resume.
This fixes OOPS (invalid opcode) on resume from STR on Asus P4P800-VM, which wakes up with MWAIT disabled.

Quoted 6 lines

Quoted 1 line
Signed-off-by Ondrej Zary <[email protected]>
Yes, that's a lot better.
I presume you have tested it. Rafael, do you want to take this or should I?

Yes, it works on the P4P800-VM. Don't have any x86_64 machine to test.

Signature · 1 line

Ondrej Zary

Rafael J. Wysocki

2010-06-07 21:04 UTC #6 lore raw

In reply to H. Peter Anvin

Quoted 8 lines · H. Peter Anvin

Quoted 7 lines · Ondrej Zary
Something like this?
Save/restore MISC_ENABLE register on suspend/resume.
This fixes OOPS (invalid opcode) on resume from STR on Asus P4P800-VM, which wakes up with MWAIT disabled.

Quoted 6 lines

Quoted 2 lines
Signed-off-by Ondrej Zary <[email protected]>
Yes, that's a lot better.
I presume you have tested it. Rafael, do you want to take this or should I?

I can take it. Is it OK to add your ACK?

Rafael

H. Peter Anvin

reviewer Acked-by

2010-06-07 21:06 UTC #7 lore raw

Quoted 9 lines · Rafael J. Wysocki

Quoted 8 lines · H. Peter Anvin
Quoted 7 lines · Ondrej Zary
Something like this?
Save/restore MISC_ENABLE register on suspend/resume.
This fixes OOPS (invalid opcode) on resume from STR on Asus P4P800-VM, which wakes up with MWAIT disabled.

Quoted 9 lines

Quoted 6 lines
Quoted 2 lines
Signed-off-by Ondrej Zary <[email protected]>
Yes, that's a lot better.
I presume you have tested it. Rafael, do you want to take this or should I?
I can take it. Is it OK to add your ACK?

Yes.

Acked-by H. Peter Anvin <[email protected]>

Alan Stern

2010-06-07 21:09 UTC #8 lore raw

In reply to Rafael J. Wysocki

Quoted 9 lines · Rafael J. Wysocki

Quoted 8 lines · H. Peter Anvin
Quoted 7 lines · Ondrej Zary
Something like this?
Save/restore MISC_ENABLE register on suspend/resume.
This fixes OOPS (invalid opcode) on resume from STR on Asus P4P800-VM, which wakes up with MWAIT disabled.

Quoted 8 lines

Quoted 6 lines
Quoted 2 lines
Signed-off-by Ondrej Zary <[email protected]>
Yes, that's a lot better.
I presume you have tested it. Rafael, do you want to take this or should I?
I can take it. Is it OK to add your ACK?

You might in addition want to note that this patch fixes Bugzilla #15385.

Alan Stern

2010-06-07 21:09 UTC #9 lore raw

In reply to Rafael J. Wysocki

Quoted 9 lines · Rafael J. Wysocki

Quoted 8 lines · H. Peter Anvin
Quoted 7 lines · Ondrej Zary
Something like this?
Save/restore MISC_ENABLE register on suspend/resume.
This fixes OOPS (invalid opcode) on resume from STR on Asus P4P800-VM, which wakes up with MWAIT disabled.

Quoted 8 lines

Quoted 6 lines
Quoted 2 lines
Signed-off-by Ondrej Zary <[email protected]>
Yes, that's a lot better.
I presume you have tested it. Rafael, do you want to take this or should I?
I can take it. Is it OK to add your ACK?

You might in addition want to note that this patch fixes Bugzilla #15385.

Alan Stern

Rafael J. Wysocki

2010-06-07 21:05 UTC #10 lore raw

In reply to H. Peter Anvin

Quoted 8 lines · H. Peter Anvin

Quoted 7 lines · Ondrej Zary
Something like this?
Save/restore MISC_ENABLE register on suspend/resume.
This fixes OOPS (invalid opcode) on resume from STR on Asus P4P800-VM, which wakes up with MWAIT disabled.

Quoted 6 lines

Quoted 2 lines
Signed-off-by Ondrej Zary <[email protected]>
Yes, that's a lot better.
I presume you have tested it. Rafael, do you want to take this or should I?

I can take it. Is it OK to add your ACK?

Rafael