ipr: add writeq definition if needed
Subsystems (2)
A message that is not in the archive (sent off-list or not yet received): [email protected]
PATCH 1/1 ipr: add writeq definition if needed
Compiling the driver will fail on 32 bit powerpc and other architectures where writeq is not defined. This patch adds a definition for writeq.
---
drivers/scsi/ipr.h | 8 ++++++++ 1 file changed, 8 insertions(+)
drivers/scsi/ipr.h +8 -0
@@ -1860,4 +1860,12 @@ static inline int ipr_sdt_is_fmt2(u32 sd return 0; } +#ifndef writeq +static inline void writeq (u64 val,void __iomem *addr) +{ +writel (((u32) (val >>32 )), addr); +writel (((u32) (val)), (addr +4 )); +}#endif + +#endif /* _IPR_H */
Quoted 28 lines · Wayne Boyer
Compiling the driver will fail on 32 bit powerpc and other architectures where writeq is not defined. This patch adds a definition for writeq.
Signed-off-by Wayne Boyer <[email protected]>---
drivers/scsi/ipr.h | 8 ++++++++ 1 file changed, 8 insertions(+)Index:
b/drivers/scsi/ipr.h
===================================================================drivers/scsi/ipr.h +8
-0@@ -1860,4 +1860,12 @@ static inline int ipr_sdt_is_fmt2(u32 sd return 0; } +#ifndef writeq +static inline void writeq (u64 val,void __iomem *addr) +{ +writel (((u32) (val >>32 )), addr); +writel (((u32) (val)), (addr +4 )); +}#endif + +#endif /* _IPR_H */
Signature · 3 lines
Brian King Linux on Power Virtualization IBM Linux Technology Center
Quoted 15 lines · Wayne Boyer
Compiling the driver will fail on 32 bit powerpc and other architectures where writeq is not defined. This patch adds a definition for writeq.
Signed-off-by Wayne Boyer <[email protected]>---
drivers/scsi/ipr.h | 8 ++++++++ 1 file changed, 8 insertions(+)Index:
b/drivers/scsi/ipr.h
===================================================================
drivers/scsi/ipr.h static inline int ipr_sdt_is_fmt2(u32 sd · line 1867
Quoted 8 lines
drivers/scsi/ipr.h +5
-0@@ -1860,4 +1860,12 @@ static inline int ipr_sdt_is_fmt2(u32 sdreturn 0 ; } +#ifndef writeq +static inline void writeq (u64 val,void __iomem *addr) +{ +writel (((u32) (val >>32 )), addr); +writel (((u32) (val)), (addr +4 ));
Are you sure this is what you want? The point about writeq is to do an atomic write of a 64 bit quantity. Doing two writel's loses the atomicity (and can confuse some hardware if not done in the right order). If this code above works correctly, why bother with the writeq?
James
Quoted 19 lines · James Bottomley
Quoted 18 lines · Wayne Boyer
Compiling the driver will fail on 32 bit powerpc and other architectures where writeq is not defined. This patch adds a definition for writeq.
Signed-off-by Wayne Boyer <[email protected]>---
drivers/scsi/ipr.h | 8 ++++++++ 1 file changed, 8 insertions(+)Index:
b/drivers/scsi/ipr.h
===================================================================drivers/scsi/ipr.h +0
-0@@ -1860,4 +1860,12 @@ static inline int ipr_sdt_is_fmt2(u32 sdreturn 0 ; }
Quoted 11 lines
drivers/scsi/ipr.h static inline int ipr_sdt_is_fmt2(u32 sd · line 1867
Quoted 5 lines
drivers/scsi/ipr.h +5
-0+#ifndef writeq +static inline void writeq (u64 val,void __iomem *addr) +{ +writel (((u32) (val >>32 )), addr); +writel (((u32) (val)), (addr +4 ));Are you sure this is what you want? The point about writeq is to do an atomic write of a 64 bit quantity. Doing two writel's loses the atomicity (and can confuse some hardware if not done in the right order). If this code above works correctly, why bother with the writeq?
We do want to issue 8 byte MMIO writes where we can for the new adapters for better performance. We want to use writeq on platforms that support it. I did test the driver using this define with the new hardware and it does work as expected.
Signature · 4 lines
Wayne Boyer IBM - Beaverton, Oregon LTC S/W Development - eServerIO (503) 578-5236, T/L 775-5236
Quoted 32 lines · Wayne Boyer
Quoted 19 lines · James Bottomley
Quoted 18 lines · Wayne Boyer
Compiling the driver will fail on 32 bit powerpc and other architectures where writeq is not defined. This patch adds a definition for writeq.
Signed-off-by Wayne Boyer <[email protected]>---
drivers/scsi/ipr.h | 8 ++++++++ 1 file changed, 8 insertions(+)Index:
b/drivers/scsi/ipr.h
===================================================================drivers/scsi/ipr.h +0
-0@@ -1860,4 +1860,12 @@ static inline int ipr_sdt_is_fmt2(u32 sdreturn 0 ; }Quoted 11 lines
drivers/scsi/ipr.h static inline int ipr_sdt_is_fmt2(u32 sd · line 1867
Quoted 5 lines
drivers/scsi/ipr.h +5
-0+#ifndef writeq +static inline void writeq (u64 val,void __iomem *addr) +{ +writel (((u32) (val >>32 )), addr); +writel (((u32) (val)), (addr +4 ));Are you sure this is what you want? The point about writeq is to do an atomic write of a 64 bit quantity. Doing two writel's loses the atomicity (and can confuse some hardware if not done in the right order). If this code above works correctly, why bother with the writeq?
Quoted 4 lines
We do want to issue 8 byte MMIO writes where we can for the new adapters for better performance. We want to use writeq on platforms that support it. I did test the driver using this define with the new hardware and it does work as expected.
OK, that's fine, just checking.
I suppose we should have some type of writeq_nonatomic() so I don't have to check, but this is the first I've seen of these, so it's likely not very common.
James