MX53: Add initial support for the Freescale MX53
PATCH 1/5 MX53: Add initial support for the Freescale MX53
The patch add initial support for the Freescale i.MX53 processor (family arm cortex_a8).
--- arch/arm/cpu/arm_cortexa8/mx53/Makefile | 48 +++ arch/arm/cpu/arm_cortexa8/mx53/clock.c | 458 ++++++++++++++++++++++++ arch/arm/cpu/arm_cortexa8/mx53/iomux.c | 151 ++++++++ arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S | 220 ++++++++++++ arch/arm/cpu/arm_cortexa8/mx53/soc.c | 93 +++++ arch/arm/cpu/arm_cortexa8/mx53/speed.c | 39 ++ arch/arm/cpu/arm_cortexa8/mx53/timer.c | 189 ++++++++++ arch/arm/cpu/arm_cortexa8/mx53/u-boot.lds | 62 ++++ arch/arm/include/asm/arch-mx53/clock.h | 51 +++ 9 files changed, 1311 insertions(+), 0 deletions(-)
arch/arm/cpu/arm_cortexa8/mx53/Makefile new file +48 -0
@@ -0,0 +1,48 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. +# +# (C) Copyright 2009 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = soc.o clock.o iomux.o timer.o speed.o +SOBJS = lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +#########################################################################
arch/arm/cpu/arm_cortexa8/mx53/clock.c new file +458 -0
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arch/arm/cpu/arm_cortexa8/mx53/iomux.c new file +151 -0
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arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S new file +220 -0
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arch/arm/cpu/arm_cortexa8/mx53/soc.c new file +93 -0
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arch/arm/cpu/arm_cortexa8/mx53/speed.c new file +39 -0
@@ -0,0 +1,39 @@ +/* +* (C) Copyright 2000-2003 +* Wolfgang Denk, DENX Software Engineering, wd at denx.de. +* +* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. +* TsiChung Liew (Tsi-Chung.Liew at freescale.com) +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <common.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> + +int get_clocks (void ) +{ +DECLARE_GLOBAL_DATA_PTR ; + +#ifdef CONFIG_FSL_ESDHC + gd->sdhc_clk =mxc_get_clock (MXC_ESDHC_CLK ); +#endif +return 0 ; +}
arch/arm/cpu/arm_cortexa8/mx53/timer.c new file +189 -0
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arch/arm/cpu/arm_cortexa8/mx53/u-boot.lds new file +62 -0
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arch/arm/include/asm/arch-mx53/clock.h new file +51 -0
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Signature · 1 line
1.7.0.4
PATCH 1/5 MX53: Add initial support for the Freescale MX53
Quoted 4 lines · Jason Liu
The patch add initial support for the Freescale i.MX53 processor (family arm
cortex_a8).Signed-off-by Jason Liu <[email protected]>
Hi Jason,
Quoted 11 lines
--- arch/arm/cpu/arm_cortexa8/mx53/Makefile | 48 +++ arch/arm/cpu/arm_cortexa8/mx53/clock.c | 458 ++++++++++++++++++++++++ arch/arm/cpu/arm_cortexa8/mx53/iomux.c | 151 ++++++++ arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S | 220 ++++++++++++ arch/arm/cpu/arm_cortexa8/mx53/soc.c | 93 +++++ arch/arm/cpu/arm_cortexa8/mx53/speed.c | 39 ++ arch/arm/cpu/arm_cortexa8/mx53/timer.c | 189 ++++++++++ arch/arm/cpu/arm_cortexa8/mx53/u-boot.lds | 62 ++++ arch/arm/include/asm/arch-mx53/clock.h | 51 +++ 9 files changed, 1311 insertions(+), 0 deletions(-)
You duplicated the structure we currently have under mx51 with new files, that sometimes are *identical* or have only slight differences with the original ones. However, we must avoid such kind of duplication and merge the small changes in a single file.
Agree that the name mx51 is confusing when we introduce another cpu of the same family, and probably we should change it from mx51 to mx5, as done in kernel. But again, then cpu/mx5 contains everything related to the cpu family and we do not to have a directory for each single cpu.
arch/arm/cpu/arm_cortexa8/mx53/Makefile
Quoted 6 lines
arch/arm/cpu/arm_cortexa8/mx53/Makefile new file +0
-0
This file is identical to mx51/Makefile. Do not introduce new copies of files.
arch/arm/cpu/arm_cortexa8/mx53/clock.c
Quoted 4 lines
arch/arm/cpu/arm_cortexa8/mx53/Makefile new file +1
-0+#########################################################################arch/arm/cpu/arm_cortexa8/mx53/clock.c new file +0
-0
The file is quite identical to mx51/clock.c, except some small changes. We have to merge them.
arch/arm/cpu/arm_cortexa8/mx53/clock.c line 35
Quoted 5 lines
arch/arm/cpu/arm_cortexa8/mx53/clock.c new file +5
-0+enum pll_clocks { +PLL1_CLOCK =0 , +PLL2_CLOCK , +PLL3_CLOCK , +PLL4_CLOCK ,
As I see, mx53 have an additional PLL (PLL4) source as the MX51. We can use the same structure for both.
arch/arm/cpu/arm_cortexa8/mx53/clock.c line 60
Quoted 13 lines
arch/arm/cpu/arm_cortexa8/mx53/clock.c new file +13
-0+static u32 __decode_pll (struct mxc_pll_reg *pll,u32 infreq) +{ +u32 mfi, mfn, mfd, pd; + + mfn =__raw_readl (&pll->mfn); + mfd =__raw_readl (&pll->mfd) +1 ; + mfi =__raw_readl (&pll->op); + pd = (mfi &0xF ) +1 ; + mfi = (mfi >>4 ) &0xF ; + mfi = (mfi >=5 ) ? mfi :5 ; + +return ((4 * (infreq /1000 ) * (mfi * mfd + mfn)) / (mfd * pd)) *1000 ; +}
This function is identical to the mx51 function.
arch/arm/cpu/arm_cortexa8/mx53/clock.c line 67
Quoted 7 lines
arch/arm/cpu/arm_cortexa8/mx53/clock.c new file +7
-0+ +static u32 __get_mcu_main_clk (void ) +{ +u32 reg, freq; + reg = (__raw_readl (&mxc_ccm->cacrr) &MXC_CCM_CACRR_ARM_PODF_MASK ) >> +MXC_CCM_CACRR_ARM_PODF_OFFSET ; + freq =__decode_pll (mxc_plls[PLL1_CLOCK ],CONFIG_MX53_HCLK_FREQ );
For most functions, the differences is due only to the usage of a different constant. Can we do in another way ? We have already a CONFIG_MX51 switch, and, if we do not find a cleverer solution, we could add some kind of CONFIG_MX53 and put the #ifdef where we define this constants to get a different value.
arch/arm/cpu/arm_cortexa8/mx53/clock.c line 82
Quoted 12 lines
arch/arm/cpu/arm_cortexa8/mx53/clock.c new file +12
-0+static u32 __get_periph_clk (void ) +{ +u32 reg; + reg =__raw_readl (&mxc_ccm->cbcdr); +if (!(reg &MXC_CCM_CBCDR_PERIPH_CLK_SEL )) +return __decode_pll (mxc_plls[PLL2_CLOCK ],CONFIG_MX53_HCLK_FREQ ); + + reg =__raw_readl (&mxc_ccm->cbcmr); +switch ((reg &MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK ) >> +MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET ) { +case 0 : +return __decode_pll (mxc_plls[PLL1_CLOCK ],CONFIG_MX53_HCLK_FREQ );
Ditto
arch/arm/cpu/arm_cortexa8/mx53/clock.c line 101
Quoted 11 lines
arch/arm/cpu/arm_cortexa8/mx53/clock.c new file +11
-0+static u32 __get_ipg_clk (void ) +{ +u32 ahb_podf, ipg_podf; + + ahb_podf =__raw_readl (&mxc_ccm->cbcdr); + ipg_podf = (ahb_podf &MXC_CCM_CBCDR_IPG_PODF_MASK ) >> +MXC_CCM_CBCDR_IPG_PODF_OFFSET ; + ahb_podf = (ahb_podf &MXC_CCM_CBCDR_AHB_PODF_MASK ) >> +MXC_CCM_CBCDR_AHB_PODF_OFFSET ; +return __get_periph_clk () / ((ahb_podf +1 ) * (ipg_podf +1 )); +}
Except for variable names, identical to mx51 function
arch/arm/cpu/arm_cortexa8/mx53/clock.c line 140
Quoted 8 lines
arch/arm/cpu/arm_cortexa8/mx53/clock.c new file +8
-0+static u32 __get_uart_clk (void ) +{ +u32 freq =0 , reg, pred, podf; + reg =__raw_readl (&mxc_ccm->cscmr1); +switch ((reg &MXC_CCM_CSCMR1_UART_CLK_SEL_MASK ) >> +MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET ) { +case 0x0 : + freq =__decode_pll (mxc_plls[PLL1_CLOCK ],CONFIG_MX53_HCLK_FREQ );
Ditto
arch/arm/cpu/arm_cortexa8/mx53/clock.c line 169
Quoted 4 lines
arch/arm/cpu/arm_cortexa8/mx53/clock.c new file +4
-0+ + +static u32 __get_cspi_clk (void ) +{
Again
Quoted 16 lines
arch/arm/cpu/arm_cortexa8/mx53/clock.c new file +16
-0+static u32 __get_axi_a_clk (void ) +{ +u32 cbcdr =__raw_readl (&mxc_ccm->cbcdr); +u32 pdf = (cbcdr &MXC_CCM_CBCDR_AXI_A_PODF_MASK ) \ + >>MXC_CCM_CBCDR_AXI_A_PODF_OFFSET ; + +return __get_periph_clk () / (pdf +1 ); +} + +static u32 __get_axi_b_clk (void ) +{ +u32 cbcdr =__raw_readl (&mxc_ccm->cbcdr); +u32 pdf = (cbcdr &MXC_CCM_CBCDR_AXI_B_PODF_MASK ) \ + >>MXC_CCM_CBCDR_AXI_B_PODF_OFFSET ; + +return __get_periph_clk () / (pdf +1 );
arch/arm/cpu/arm_cortexa8/mx53/clock.c line 229
Quoted 10 lines
arch/arm/cpu/arm_cortexa8/mx53/clock.c new file +10
-0+} + +static u32 __get_ahb_clk (void ) +{ +u32 cbcdr =__raw_readl (&mxc_ccm->cbcdr); +u32 pdf = (cbcdr &MXC_CCM_CBCDR_AHB_PODF_MASK ) \ + >>MXC_CCM_CBCDR_AHB_PODF_OFFSET ; + +return __get_periph_clk () / (pdf +1 ); +}
These new function can be used for MX51 as well. It makes more sense to get a single file for all MX5 family.
arch/arm/cpu/arm_cortexa8/mx53/clock.c line 280
Quoted 9 lines
arch/arm/cpu/arm_cortexa8/mx53/clock.c new file +9
-0+static u32 __get_esdhc1_clk (void ) +{ +u32 ret_val =0 , div, pre_pdf, pdf; +u32 cscmr1 =__raw_readl (&mxc_ccm->cscmr1); +u32 cscdr1 =__raw_readl (&mxc_ccm->cscdr1); +u32 esdh1_clk_sel; + + esdh1_clk_sel = (cscmr1 &MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK ) \ + >>MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET ;
__get_esdhc1_clk(void), __get_esdhc2_clk(void) and _get_esdhc3_clk(void) are the same function, they use only a different constant to access the registers. can we factorize them ?
arch/arm/cpu/arm_cortexa8/mx53/clock.c line 434
Quoted 12 lines
arch/arm/cpu/arm_cortexa8/mx53/clock.c new file +12
-0+/* +* Dump some core clockes. +*/ +int do_mx53_showclocks (cmd_tbl_t *cmdtp,int flag,int argc,char *argv[]) +{ +u32 freq; + freq =__decode_pll (mxc_plls[PLL1_CLOCK ],CONFIG_MX53_HCLK_FREQ ); +printf ("mx53 pll1: %dMHz\n" , freq /1000000 ); + freq =__decode_pll (mxc_plls[PLL2_CLOCK ],CONFIG_MX53_HCLK_FREQ ); +printf ("mx53 pll2: %dMHz\n" , freq /1000000 ); + freq =__decode_pll (mxc_plls[PLL3_CLOCK ],CONFIG_MX53_HCLK_FREQ ); +printf ("mx53 pll3: %dMHz\n" , freq /1000000 );
Again, this function must be merged with do_mx51_showclocks().
arch/arm/cpu/arm_cortexa8/mx53/iomux.c
Quoted 5 lines
arch/arm/cpu/arm_cortexa8/mx53/iomux.c new file +0
-0
This file seems a previous version of iomux.c for MX51. There are only a few differences with the MX51 counterparts, and contains some issue that were reported by ML and solved in the actual version. You should use mx51/iomux.c adding your changes.
arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S
Quoted 5 lines
arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S new file +0
-0
Again, we should use only one for both cpus.
Quoted 15 lines
+.macro
setup_pllpll, freqarch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S new file +14
-0+ ldr r0, =\pll + ldr r1, =0x00001232 + str r1, [r0, #PLL_DP_CTL] + mov r1, #0x2 + str r1, [r0, #PLL_DP_CONFIG] + + ldr r1, W_DP_OP_\freq + str r1, [r0, #PLL_DP_OP] + str r1, [r0, #PLL_DP_HFS_OP] + + ldr r1, W_DP_MFD_\freq + str r1, [r0, #PLL_DP_MFD] + str r1, [r0, #PLL_DP_HFS_MFD] +
arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S line 85
Quoted 10 lines
arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S new file +10
-0+ ldr r1, W_DP_MFN_\freq + str r1, [r0, #PLL_DP_MFN] + str r1, [r0, #PLL_DP_HFS_MFN] + + ldr r1, =0x00001232 + str r1, [r0, #PLL_DP_CTL] +1: ldr r1, [r0, #PLL_DP_CTL] + ands r1, r1, #0x1 + beq 1b +.endm
can we use the same macro for MX51, too ?
Quoted 8 lines
+.section ".text.init", "x"
arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S new file +7
-0+ +.globl lowlevel_init +lowlevel_init: + +#ifdef ENABLE_IMPRECISE_ABORT + mrs r1, spsr /* save old spsr */ + mrs r0, cpsr /* read out the cpsr */
arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S line 186
Quoted 10 lines
arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S new file +10
-0+ bic r0, r0, #0x100 /* clear the A bit */ + msr spsr, r0 /* update spsr */ + add lr, pc, #0x8 /* update lr */ + movs pc, lr /* update cpsr */ + nop + nop + nop + nop + msr spsr, r1 /* restore old spsr */ +#endif
I do not find ENABLE_IMPRECISE_ABORT at all. It is not defined, and this seems dead code. Can you explain why and if this code is needed ? In this case, you have to define ENABLE_IMPRECISE_ABORT somewhere.
arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S line 191
Quoted 4 lines
arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S new file +4
-0+ /* ARM errata ID #468414 */ + mrc 15, 0, r1, c1, c0, 1 + orr r1, r1, #(1 << 5) /* enable L1NEON bit */ + mcr 15, 0, r1, c1, c0, 1
This seems useful for MX51, too. It is a pity to get this correction only for one specifical CPU.
Quoted 1 line
+++
b/arch/arm/cpu/arm_cortexa8/mx53/soc.c
It must be merged with mx51/soc.c
arch/arm/cpu/arm_cortexa8/mx53/speed.c line 37
Quoted 8 lines
arch/arm/cpu/arm_cortexa8/mx53/speed.c +7
-0+int get_clocks (void ) +{ +DECLARE_GLOBAL_DATA_PTR ; + +#ifdef CONFIG_FSL_ESDHC + gd->sdhc_clk =mxc_get_clock (MXC_ESDHC_CLK ); +#endif
Except for the constant, identical to mx51/speed.c. It must be merged.
arch/arm/cpu/arm_cortexa8/mx53/timer.c
Quoted 1 line
arch/arm/cpu/arm_cortexa8/mx53/timer.c +0
-0
Again, it must be merged with mx51/timer.c
arch/arm/cpu/arm_cortexa8/mx53/u-boot.lds line 39
Quoted 3 lines
arch/arm/cpu/arm_cortexa8/mx53/u-boot.lds +2
-0+ { + board/freescale/mx53evk/flash_header.o
During the review of MX51, it was accepted another solution to link the DCD and generally the boot structure to u-boot code. Check the imximage and doc/README.imximage. The current solution is consistent with other architectures, too, such as Kirchwood. Linking the DCD table with flash_header is not accepted.
And u-boot.lds can be the same for MX51 and MX53.
Quoted 13 lines
arch/arm/include/asm/arch-mx53/clock.h new file +8
-0+ +enum mxc_clock { +MXC_ARM_CLK =0 , +MXC_PER_CLK , +MXC_AHB_CLK , +MXC_IPG_CLK , +MXC_IPG_PERCLK , +MXC_UART_CLK ,
arch/arm/include/asm/arch-mx53/clock.h line 43
Quoted 10 lines
arch/arm/include/asm/arch-mx53/clock.h new file +10
-0+MXC_CSPI_CLK , +MXC_AXI_A_CLK , +MXC_AXI_B_CLK , +MXC_EMI_SLOW_CLK , +MXC_DDR_CLK , +MXC_ESDHC_CLK , +MXC_ESDHC2_CLK , +MXC_ESDHC3_CLK , + MXC_ESDHC4_CLK, +};
There are some additional enum as for MX51. Again, we can use only one file for both. And I propose to change arch/arm/include/asm/arch-mx51 to arch/arm/include/asm/arch-mx5.
Best regards,
Stefano babic
Signature · 5 lines
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PATCH 1/5 MX53: Add initial support for the Freescale MX53
Hi, Stefano
Quoted 27 lines
-----Original Message-----
From: Stefano Babic [mailto:sbabic at denx.de]
Sent: 2010?6?18? 17:23
To: Liu Hui-R64343
Cc: wd at denx.de; u-boot at lists.denx.de
Subject: Re: [U-Boot] [U-BOOT][PATCH 1/5] MX53: Add initial support for the Freescale MX53Quoted 4 lines · Jason Liu
The patch add initial support for the Freescale i.MX53 processor (family arm
cortex_a8).Signed-off-by Jason Liu <[email protected]>Hi Jason,
Quoted 11 lines
--- arch/arm/cpu/arm_cortexa8/mx53/Makefile | 48 +++ arch/arm/cpu/arm_cortexa8/mx53/clock.c | 458 ++++++++++++++++++++++++ arch/arm/cpu/arm_cortexa8/mx53/iomux.c | 151 ++++++++ arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S | 220 ++++++++++++ arch/arm/cpu/arm_cortexa8/mx53/soc.c | 93 +++++ arch/arm/cpu/arm_cortexa8/mx53/speed.c | 39 ++ arch/arm/cpu/arm_cortexa8/mx53/timer.c | 189 ++++++++++ arch/arm/cpu/arm_cortexa8/mx53/u-boot.lds | 62 ++++ arch/arm/include/asm/arch-mx53/clock.h | 51 +++ 9 files changed, 1311 insertions(+), 0 deletions(-)
Quoted 6 lines
You duplicated the structure we currently have under mx51 with new files, that sometimes are *identical* or have only slight differences with the original ones. However, we must avoid such kind of duplication and merge the small changes in a single file.
Agree that the name mx51 is confusing when we introduce another cpu of the same family, and probably we should change it from mx51 to mx5, as done in kernel. But again, then cpu/mx5 contains everything related to the cpu family and we do not to have a directory for each single cpu.
Yes, agree. I will do some changes to incorporate mx51/mx53 and later mx5x by changing the mx51 to mx5.
Quoted 11 lines
arch/arm/cpu/arm_cortexa8/mx53/Makefile
Quoted 8 lines
arch/arm/cpu/arm_cortexa8/mx53/Makefile new file +0
-0This file is identical to mx51/Makefile. Do not introduce new copies of files.
Quoted 9 lines
arch/arm/cpu/arm_cortexa8/mx53/clock.c
Quoted 6 lines
arch/arm/cpu/arm_cortexa8/mx53/Makefile new file +2
-0+##################################################################### +####arch/arm/cpu/arm_cortexa8/mx53/clock.c new file +0
-0The file is quite identical to
mx51/clock.c, except some small changes. We have to merge them.
Yes,
Quoted 24 lines
arch/arm/cpu/arm_cortexa8/mx53/clock.c line 35
Quoted 6 lines
arch/arm/cpu/arm_cortexa8/mx53/clock.c new file +5
-0+enum pll_clocks { +PLL1_CLOCK =0 , +PLL2_CLOCK , +PLL3_CLOCK , +PLL4_CLOCK ,As I see, mx53 have an additional PLL (PLL4) source as the MX51. We can use the same structure for both.
arch/arm/cpu/arm_cortexa8/mx53/clock.c
Quoted 12 lines
arch/arm/cpu/arm_cortexa8/mx53/clock.c new file +12
-0+static u32 __decode_pll (struct mxc_pll_reg *pll,u32 infreq) { +u32 mfi, mfn, mfd, pd; + + mfn =__raw_readl (&pll->mfn); + mfd =__raw_readl (&pll->mfd) +1 ; + mfi =__raw_readl (&pll->op); + pd = (mfi &0xF ) +1 ; + mfi = (mfi >>4 ) &0xF ; + mfi = (mfi >=5 ) ? mfi :5 ; + +return ((4 * (infreq /1000 ) * (mfi * mfd + mfn)) / (mfd * pd)) * +1000 ; }This function is identical to the mx51 function.
Quoted 11 lines
arch/arm/cpu/arm_cortexa8/mx53/clock.c line 67
Quoted 7 lines
arch/arm/cpu/arm_cortexa8/mx53/clock.c new file +7
-0+ +static u32 __get_mcu_main_clk (void ) +{ +u32 reg, freq; + reg = (__raw_readl (&mxc_ccm->cacrr) &MXC_CCM_CACRR_ARM_PODF_MASK ) >> +MXC_CCM_CACRR_ARM_PODF_OFFSET ; + freq =__decode_pll (mxc_plls[PLL1_CLOCK ],CONFIG_MX53_HCLK_FREQ );For most functions, the differences is due only to the usage of a different constant. Can we do in another way ? We have already a
CONFIG_MX51switch, and, if we do not find a cleverer solution, we could add some kind ofCONFIG_MX53and put the #ifdef where we define this constants to get a different value.
Yes, agree.
Quoted 65 lines
Quoted 4 lines
arch/arm/cpu/arm_cortexa8/mx53/clock.c new file +2
-0+static u32 __get_periph_clk (void ) +{arch/arm/cpu/arm_cortexa8/mx53/clock.c line 82
Quoted 10 lines
arch/arm/cpu/arm_cortexa8/mx53/clock.c new file +10
-0+u32 reg; + reg =__raw_readl (&mxc_ccm->cbcdr); +if (!(reg &MXC_CCM_CBCDR_PERIPH_CLK_SEL )) +return __decode_pll (mxc_plls[PLL2_CLOCK ],CONFIG_MX53_HCLK_FREQ ); + + reg =__raw_readl (&mxc_ccm->cbcmr); +switch ((reg &MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK ) >> +MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET ) { +case 0 : +return __decode_pll (mxc_plls[PLL1_CLOCK ],CONFIG_MX53_HCLK_FREQ );Ditto
arch/arm/cpu/arm_cortexa8/mx53/clock.c
Quoted 10 lines
arch/arm/cpu/arm_cortexa8/mx53/clock.c new file +10
-0+static u32 __get_ipg_clk (void ) +{ +u32 ahb_podf, ipg_podf; + + ahb_podf =__raw_readl (&mxc_ccm->cbcdr); + ipg_podf = (ahb_podf &MXC_CCM_CBCDR_IPG_PODF_MASK ) >> +MXC_CCM_CBCDR_IPG_PODF_OFFSET ; + ahb_podf = (ahb_podf &MXC_CCM_CBCDR_AHB_PODF_MASK ) >> +MXC_CCM_CBCDR_AHB_PODF_OFFSET ; +return __get_periph_clk () / ((ahb_podf +1 ) * (ipg_podf +1 )); }Except for variable names, identical to mx51 function
arch/arm/cpu/arm_cortexa8/mx53/clock.c line 140
Quoted 8 lines
arch/arm/cpu/arm_cortexa8/mx53/clock.c new file +8
-0+static u32 __get_uart_clk (void ) +{ +u32 freq =0 , reg, pred, podf; + reg =__raw_readl (&mxc_ccm->cscmr1); +switch ((reg &MXC_CCM_CSCMR1_UART_CLK_SEL_MASK ) >> +MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET ) { +case 0x0 : + freq =__decode_pll (mxc_plls[PLL1_CLOCK ],CONFIG_MX53_HCLK_FREQ );Ditto
arch/arm/cpu/arm_cortexa8/mx53/clock.c line 169
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arch/arm/cpu/arm_cortexa8/mx53/clock.c new file +4
-0+ + +static u32 __get_cspi_clk (void ) +{Again
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arch/arm/cpu/arm_cortexa8/mx53/clock.c new file +17
-0+static u32 __get_axi_a_clk (void ) +{ +u32 cbcdr =__raw_readl (&mxc_ccm->cbcdr); +u32 pdf = (cbcdr &MXC_CCM_CBCDR_AXI_A_PODF_MASK ) \ + >>MXC_CCM_CBCDR_AXI_A_PODF_OFFSET ; + +return __get_periph_clk () / (pdf +1 ); } + +static u32 __get_axi_b_clk (void ) +{ +u32 cbcdr =__raw_readl (&mxc_ccm->cbcdr); +u32 pdf = (cbcdr &MXC_CCM_CBCDR_AXI_B_PODF_MASK ) \ + >>MXC_CCM_CBCDR_AXI_B_PODF_OFFSET ; + +return __get_periph_clk () / (pdf +1 ); } + +static u32 __get_ahb_clk (void )
Quoted 8 lines
arch/arm/cpu/arm_cortexa8/mx53/clock.c
Quoted 6 lines
arch/arm/cpu/arm_cortexa8/mx53/clock.c new file +6
-0+{ +u32 cbcdr =__raw_readl (&mxc_ccm->cbcdr); +u32 pdf = (cbcdr &MXC_CCM_CBCDR_AHB_PODF_MASK ) \ + >>MXC_CCM_CBCDR_AHB_PODF_OFFSET ; + +return __get_periph_clk () / (pdf +1 ); }These new function can be used for MX51 as well. It makes more sense to get a single file for all MX5 family.
Yes,
Quoted 32 lines
arch/arm/cpu/arm_cortexa8/mx53/clock.c line 280
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arch/arm/cpu/arm_cortexa8/mx53/clock.c new file +9
-0+static u32 __get_esdhc1_clk (void ) +{ +u32 ret_val =0 , div, pre_pdf, pdf; +u32 cscmr1 =__raw_readl (&mxc_ccm->cscmr1); +u32 cscdr1 =__raw_readl (&mxc_ccm->cscdr1); +u32 esdh1_clk_sel; + + esdh1_clk_sel = (cscmr1 &MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK ) \ + >>MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET ;
__get_esdhc1_clk(void),__get_esdhc2_clk(void)and_get_esdhc3_clk(void)are the same function, they use only a different constant to access the registers. can we factorize them ?arch/arm/cpu/arm_cortexa8/mx53/clock.c line 434
Quoted 12 lines
arch/arm/cpu/arm_cortexa8/mx53/clock.c new file +12
-0+/* +* Dump some core clockes. +*/ +int do_mx53_showclocks (cmd_tbl_t *cmdtp,int flag,int argc,char +*argv[]) { +u32 freq; + freq =__decode_pll (mxc_plls[PLL1_CLOCK ],CONFIG_MX53_HCLK_FREQ ); +printf ("mx53 pll1: %dMHz\n" , freq /1000000 ); + freq =__decode_pll (mxc_plls[PLL2_CLOCK ],CONFIG_MX53_HCLK_FREQ ); +printf ("mx53 pll2: %dMHz\n" , freq /1000000 ); + freq =__decode_pll (mxc_plls[PLL3_CLOCK ],CONFIG_MX53_HCLK_FREQ ); +printf ("mx53 pll3: %dMHz\n" , freq /1000000 );Again, this function must be merged with
do_mx51_showclocks().
Quoted 9 lines
arch/arm/cpu/arm_cortexa8/mx53/iomux.c
Quoted 6 lines
arch/arm/cpu/arm_cortexa8/mx53/iomux.c new file +0
-0This file seems a previous version of
iomux.cfor MX51. There are only a few differences with the MX51 counterparts, and contains some issue that were reported by ML and solved in the actual version. You should usemx51/iomux.cadding your changes.
Yes, I will merge it in.
Quoted 30 lines
arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S
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arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S new file +0
-0Again, we should use only one for both cpus.
Quoted 19 lines
+.macro
setup_pllpll, freqarch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S new file +18
-0+ ldr r0, =\pll + ldr r1, =0x00001232 + str r1, [r0, #PLL_DP_CTL] + mov r1, #0x2 + str r1, [r0, #PLL_DP_CONFIG] + + ldr r1, W_DP_OP_\freq + str r1, [r0, #PLL_DP_OP] + str r1, [r0, #PLL_DP_HFS_OP] + + ldr r1, W_DP_MFD_\freq + str r1, [r0, #PLL_DP_MFD] + str r1, [r0, #PLL_DP_HFS_MFD] + + ldr r1, W_DP_MFN_\freq + str r1, [r0, #PLL_DP_MFN] + str r1, [r0, #PLL_DP_HFS_MFN] +
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arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S line 85
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arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S new file +6
-0+ ldr r1, =0x00001232 + str r1, [r0, #PLL_DP_CTL] +1: ldr r1, [r0, #PLL_DP_CTL] + ands r1, r1, #0x1 + beq 1b +.endmcan we use the same macro for MX51, too ?
In fact, MX53 has some big difference is that it support 400MHz DDR which lead to the ddr clock init part not like MX51, but I will try to do it in one file.
Quoted 14 lines
Quoted 14 lines
+.section ".text.init", "x"
arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S new file +12
-0+ +.globl lowlevel_init +lowlevel_init: + +#ifdef ENABLE_IMPRECISE_ABORT + mrs r1, spsr /* save old spsr */ + mrs r0, cpsr /* read out the cpsr */ + bic r0, r0, #0x100 /* clear the A bit */ + msr spsr, r0 /* update spsr */ + add lr, pc, #0x8 /* update lr */ + movs pc, lr /* update cpsr */ + nop
Quoted 8 lines
arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S line 186
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arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S new file +5
-0+ nop + nop + nop + msr spsr, r1 /* restore old spsr */ +#endifI do not find
ENABLE_IMPRECISE_ABORTat all. It is not defined, and this seems dead code. Can you explain why and if this code is needed ? In this case, you have to defineENABLE_IMPRECISE_ABORTsomewhere.
Yes, It's obsolete. I will remove it.
Quoted 30 lines
arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S line 191
Quoted 6 lines
arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S new file +4
-0+ /* ARM errata ID #468414 */ + mrc 15, 0, r1, c1, c0, 1 + orr r1, r1, #(1 << 5) /* enable L1NEON bit */ + mcr 15, 0, r1, c1, c0, 1This seems useful for MX51, too. It is a pity to get this correction only for one specifical CPU.
Quoted 1 line
+++
b/arch/arm/cpu/arm_cortexa8/mx53/soc.cIt must be merged with
mx51/soc.carch/arm/cpu/arm_cortexa8/mx53/speed.c
Quoted 8 lines
arch/arm/cpu/arm_cortexa8/mx53/speed.c +6
-0+int get_clocks (void ) +{ +DECLARE_GLOBAL_DATA_PTR ; + +#ifdef CONFIG_FSL_ESDHC + gd->sdhc_clk =mxc_get_clock (MXC_ESDHC_CLK );#endif Except for the constant, identical to
mx51/speed.c. It must be merged.arch/arm/cpu/arm_cortexa8/mx53/timer.c
Quoted 2 lines
arch/arm/cpu/arm_cortexa8/mx53/timer.c +0
-0Again, it must be merged with
mx51/timer.c
Quoted 8 lines
arch/arm/cpu/arm_cortexa8/mx53/u-boot.lds line 39
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arch/arm/cpu/arm_cortexa8/mx53/u-boot.lds +2
-0+ { + board/freescale/mx53evk/flash_header.oDuring the review of MX51, it was accepted another solution to link the DCD and generally the boot structure to u-boot code. Check the imximage and doc/README.imximage. The current solution is consistent with other architectures, too, such as Kirchwood. Linking the DCD table with
flash_headeris not accepted.
In fact, MX53 has much change on the flash header which means the flash header for mx51 does not applied to mx53. It will need much change. And later MX5X does not guarantee to be the same as MX53.If link DCD with flash header not accept, then I will change related files such as tools/imximage.c.
Quoted 22 lines
And
u-boot.ldscan be the same for MX51 and MX53.Quoted 19 lines
arch/arm/include/asm/arch-mx53/clock.h new file +13
-0+ +enum mxc_clock { +MXC_ARM_CLK =0 , +MXC_PER_CLK , +MXC_AHB_CLK , +MXC_IPG_CLK , +MXC_IPG_PERCLK , +MXC_UART_CLK , +MXC_CSPI_CLK , +MXC_AXI_A_CLK , +MXC_AXI_B_CLK , +MXC_EMI_SLOW_CLK , +MXC_DDR_CLK ,
Quoted 8 lines
arch/arm/include/asm/arch-mx53/clock.h line 43
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arch/arm/include/asm/arch-mx53/clock.h new file +5
-0+MXC_ESDHC_CLK , +MXC_ESDHC2_CLK , +MXC_ESDHC3_CLK , + MXC_ESDHC4_CLK, +};There are some additional enum as for MX51. Again, we can use only one file for both. And I propose to change
arch/arm/include/asm/arch-mx51toarch/arm/include/asm/arch-mx5.
OK, agree.
Quoted 10 lines
Best regards,
Stefano babic--
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DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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PATCH 1/5 MX53: Add initial support for the Freescale MX53
Quoted 1 line · Jason Liu
Hi, Stefano
Hi Jason,
Quoted 2 lines
MX53 has different flash header structure than mx51/35/25, which
means I need change thetools/imximage.cfiles
I can see something in the patch you have already sent. However, I do not know the details, and the documentation on Freescale's website is not yet released.
Quoted 2 lines
I want to add one
imximage_v2.cand .h file and register theimx_v2format to system. Do you think it's accepted or not.
I do not know, it depends if this is the best solution expressed by the ML ;-).
Is there a way to get a preview about the flash header required by the MX.53 ?
I try to make some assumptions based on the flash_header.S file you delivered in your patchset, just to share some ideas.
It seems that for MX.53 all (or most) values are written with big endianess. This could be managed with a tag in the configuration file, something like:
ENDIAN BIG
If it is not set, values must be written in little endian mode as for MX.51.
Except for the endianess, the DCD table seems to be the same (two integers for each entry, address and value), but with a different magic number as for MX51 (dcd_hdr). Is there any internal name in Freescale to distinguish between the flash header for the MX51 and for the MX53 (or other processors of the family) ? Some version numbers ?
It could be possible to add this information to the configuration file to inform the imximage utility which kind of header must be generated. Feel free to add any kind of additional tags to the configuration file you think can be useful.
I do not know which kind of modifications you plane to do, but I think it would be preferable to have a single utility to manage the IMX header. I mean, you can add additional files, but it would be bad if the parser and some other parts will be duplicated. I think it is better to extend the actual parser to support the MX53 changes.
Some values in your flash header seems to be addresses, as
boot_data: .word 0x77800000
Is it ? Then yes, I think these values should not be hard-coded, and they can be computed by the imximage as it does currently for MX51 (check for example to the app_code_jump_vector and dcd_ptr_ptr in the code).
By the way, I posted your question on the u-boot ML, if someone else would like to contribute to this topic.
Best regards,
Stefano
Signature · 5 lines
===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de =====================================================================
PATCH 2/5 MX53: Add register definitions
In reply to Jason LiuThe patch add header files to support the Freescale i.MX53 processor, setting definitions for internal registers.
--- arch/arm/include/asm/arch-mx53/asm-offsets.h | 52 ++ arch/arm/include/asm/arch-mx53/crm_regs.h | 708 ++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx53/imx-regs.h | 193 +++++++ 3 files changed, 953 insertions(+), 0 deletions(-)
arch/arm/include/asm/arch-mx53/asm-offsets.h new file +52 -0
@@ -0,0 +1,52 @@ +/* +* needed for arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S +* +* These should be auto-generated +*/ +/* CCM */ +#define CLKCTL_CCR 0x00 +#define CLKCTL_CCDR 0x04 +#define CLKCTL_CSR 0x08 +#define CLKCTL_CCSR 0x0C +#define CLKCTL_CACRR 0x10 +#define CLKCTL_CBCDR 0x14 +#define CLKCTL_CBCMR 0x18 +#define CLKCTL_CSCMR1 0x1C +#define CLKCTL_CSCMR2 0x20 +#define CLKCTL_CSCDR1 0x24 +#define CLKCTL_CS1CDR 0x28 +#define CLKCTL_CS2CDR 0x2C +#define CLKCTL_CDCDR 0x30 +#define CLKCTL_CHSCCDR 0x34 +#define CLKCTL_CSCDR2 0x38 +#define CLKCTL_CSCDR3 0x3C +#define CLKCTL_CSCDR4 0x40 +#define CLKCTL_CWDR 0x44 +#define CLKCTL_CDHIPR 0x48 +#define CLKCTL_CDCR 0x4C +#define CLKCTL_CTOR 0x50 +#define CLKCTL_CLPCR 0x54 +#define CLKCTL_CISR 0x58 +#define CLKCTL_CIMR 0x5C +#define CLKCTL_CCOSR 0x60 +#define CLKCTL_CGPR 0x64 +#define CLKCTL_CCGR0 0x68 +#define CLKCTL_CCGR1 0x6C +#define CLKCTL_CCGR2 0x70 +#define CLKCTL_CCGR3 0x74 +#define CLKCTL_CCGR4 0x78 +#define CLKCTL_CCGR5 0x7C +#define CLKCTL_CCGR6 0x80 +#define CLKCTL_CCGR7 0x84 +#define CLKCTL_CMEOR 0x88 + +/* DPLL */ +#define PLL_DP_CTL 0x00 +#define PLL_DP_CONFIG 0x04 +#define PLL_DP_OP 0x08 +#define PLL_DP_MFD 0x0C +#define PLL_DP_MFN 0x10 +#define PLL_DP_HFS_OP 0x1C +#define PLL_DP_HFS_MFD 0x20 +#define PLL_DP_HFS_MFN 0x24 +
arch/arm/include/asm/arch-mx53/crm_regs.h new file +708 -0
708 lines not on this page · raw message
arch/arm/include/asm/arch-mx53/imx-regs.h new file +193 -0
193 lines not on this page · raw message
Signature · 1 line
1.7.0.4
PATCH 2/5 MX53: Add register definitions
arch/arm/include/asm/arch-mx53/asm-offsets.h
Quoted 11 lines · Jason Liu
The patch add header files to support the Freescale i.MX53 processor, setting definitions for internal registers.
Signed-off-by Jason Liu <[email protected]>--- arch/arm/include/asm/arch-mx53/asm-offsets.h | 52 ++ arch/arm/include/asm/arch-mx53/crm_regs.h | 708 ++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx53/imx-regs.h | 193 +++++++ 3 files changed, 953 insertions(+), 0 deletions(-)arch/arm/include/asm/arch-mx53/asm-offsets.h +0
-0
The only difference with arch-mx51/asm-offset.h is:
< #define CLKCTL_CCGR7 0x84
< #define CLKCTL_CMEOR 0x88
---
Quoted 1 line
#define
CLKCTL_CMEOR0x84
We do not need to introduce a newer file.
arch/arm/include/asm/arch-mx53/crm_regs.h line 79
Quoted 5 lines
arch/arm/include/asm/arch-mx53/crm_regs.h new file +2
-0+/* Define the bits in register CCR */ +#define MXC_CCM_CCR_COSC_EN (0x1 << 12)
In mx53 some more bits are defined. However, I have not found grepping the code where they are defined. I do not think we have to introduce constants we do not need.
And this file must be merged with arch-mx51/crm_regs.h
arch/arm/include/asm/arch-mx53/imx-regs.h line 26
Quoted 4 lines
arch/arm/include/asm/arch-mx53/imx-regs.h new file +1
-0+#define IRAM_BASE_ADDR 0xF8000000/* internal ram */
This file must be merged with the mx51 counterparts, splitting values where is needed, as in this case. Something like:
#if defined(CONFIG_MX51)
#define IRAM_BASE_ADDR 0x1FFE8000 /* internal ram */
#elif define (CONFIG_MX53)
#define IRAM_BASE_ADDR 0xF8000000 /* internal ram */
#else
#error "MX5 CPU not supported"
#endif
Signature · 5 lines
===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de =====================================================================
PATCH 3/5 MX53: Add pin and multiplexer definitions.
In reply to Jason LiuThe patch add header files to support the pin multiplexer of the the Freescale i.MX53 processor.
--- arch/arm/include/asm/arch-mx53/iomux.h | 193 +++++++++++++++ arch/arm/include/asm/arch-mx53/mx53_pins.h | 359 ++++++++++++++++++++++++++++ 2 files changed, 552 insertions(+), 0 deletions(-)
arch/arm/include/asm/arch-mx53/iomux.h new file +193 -0
@@ -0,0 +1,193 @@ +/* +* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. + +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. + +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ + +#ifndef __MACH_MX53_IOMUX_H__ +#define __MACH_MX53_IOMUX_H__ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx53_pins.h> + +typedef unsigned int iomux_pin_name_t ; + +/* various IOMUX output functions */ +typedef enum iomux_config { +IOMUX_CONFIG_ALT0 , +IOMUX_CONFIG_ALT1 , +IOMUX_CONFIG_ALT2 , +IOMUX_CONFIG_ALT3 , +IOMUX_CONFIG_ALT4 , +IOMUX_CONFIG_ALT5 , +IOMUX_CONFIG_ALT6 , +IOMUX_CONFIG_ALT7 , +IOMUX_CONFIG_GPIO , +IOMUX_CONFIG_SION =0x1 <<4 , +}iomux_pin_cfg_t ; + +/* various IOMUX pad functions */ +typedef enum iomux_pad_config { +PAD_CTL_SRE_SLOW =0x0 <<0 , +PAD_CTL_SRE_FAST =0x1 <<0 , +PAD_CTL_DRV_LOW =0x0 <<1 , +PAD_CTL_DRV_MEDIUM =0x1 <<1 , +PAD_CTL_DRV_HIGH =0x2 <<1 , +PAD_CTL_DRV_MAX =0x3 <<1 , +PAD_CTL_ODE_OPENDRAIN_NONE =0x0 <<3 , +PAD_CTL_ODE_OPENDRAIN_ENABLE =0x1 <<3 , +PAD_CTL_100K_PD =0x0 <<4 , +PAD_CTL_47K_PU =0x1 <<4 , +PAD_CTL_100K_PU =0x2 <<4 , +PAD_CTL_22K_PU =0x3 <<4 , +PAD_CTL_PUE_KEEPER =0x0 <<6 , +PAD_CTL_PUE_PULL =0x1 <<6 , +PAD_CTL_PKE_NONE =0x0 <<7 , +PAD_CTL_PKE_ENABLE =0x1 <<7 , +PAD_CTL_HYS_NONE =0x0 <<8 , +PAD_CTL_HYS_ENABLE =0x1 <<8 , +PAD_CTL_DDR_INPUT_CMOS =0x0 <<9 , +PAD_CTL_DDR_INPUT_DDR =0x1 <<9 , +PAD_CTL_DRV_VOT_LOW =0x0 <<13 , +PAD_CTL_DRV_VOT_HIGH =0x1 <<13 , +}iomux_pad_config_t ; + +/* various IOMUX input functions */ +typedef enum iomux_input_config { +INPUT_CTL_PATH0 =0x0 , +INPUT_CTL_PATH1 , +INPUT_CTL_PATH2 , +INPUT_CTL_PATH3 , +INPUT_CTL_PATH4 , +INPUT_CTL_PATH5 , +INPUT_CTL_PATH6 , +INPUT_CTL_PATH7 , +}iomux_input_config_t ; + +struct mxc_iomux_pin_cfg { +iomux_pin_name_t pin; +u8 mux_mode; +u16 pad_cfg; +u8 in_select; +u8 in_mode; +}; + +/* various IOMUX input select register index */ +typedef enum iomux_input_select { +MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I =0 , +MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I , +MUX_IN_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT , +MUX_IN_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT , +MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT , +MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT , +MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_I , +MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_I , +MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT , +MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT , +MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT , +MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT , +MUX_IN_CAN1_IPP_IND_CANRX_SELECT_INPUT ,/*0x760*/ +MUX_IN_CAN2_IPP_IND_CANRX_SELECT_INPUT , +MUX_IN_CCM_IPP_ASRC_EXT_SELECT_INPUT , +MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT , +MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT , +MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT , +MUX_IN_CCM_PLL3_BYPASS_CLK_SELECT_INPUT , +MUX_IN_CCM_PLL4_BYPASS_CLK_SELECT_INPUT , +MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT ,/*0x780*/ +MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT , +MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT , +MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT , +MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT , +MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT , +MUX_IN_CSPI_IPP_IND_SS_B_4_SELECT_INPUT , +MUX_IN_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT , +MUX_IN_ECSPI1_IPP_IND_MISO_SELECT_INPUT , +MUX_IN_ECSPI1_IPP_IND_MOSI_SELECT_INPUT , +MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT , +MUX_IN_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT , +MUX_IN_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT ,/*0x7B0*/ +MUX_IN_ECSPI1_IPP_IND_SS_B_4_SELECT_INPUT , +MUX_IN_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT , +MUX_IN_ECSPI2_IPP_IND_MISO_SELECT_INPUT , +MUX_IN_ECSPI2_IPP_IND_MOSI_SELECT_INPUT , +MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT , +MUX_IN_ECSPI2_IPP_IND_SS_B_2_SELECT_INPUT , +MUX_IN_ESAI1_IPP_IND_FSR_SELECT_INPUT , +MUX_IN_ESAI1_IPP_IND_FST_SELECT_INPUT , +MUX_IN_ESAI1_IPP_IND_HCKR_SELECT_INPUT , +MUX_IN_ESAI1_IPP_IND_HCKT_SELECT_INPUT , +MUX_IN_ESAI1_IPP_IND_SCKR_SELECT_INPUT , +MUX_IN_ESAI1_IPP_IND_SCKT_SELECT_INPUT ,/*0x7E0*/ +MUX_IN_ESAI1_IPP_IND_SDO0_SELECT_INPUT , +MUX_IN_ESAI1_IPP_IND_SDO1_SELECT_INPUT , +MUX_IN_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT , +MUX_IN_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT , +MUX_IN_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT , +MUX_IN_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT , +MUX_IN_ESDHC1_IPP_WP_ON_SELECT_INPUT , +MUX_IN_FEC_FEC_COL_SELECT_INPUT ,/*0x800*/ +MUX_IN_FEC_FEC_MDI_SELECT_INPUT , +MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT , +MUX_IN_FIRI_IPP_IND_RXD_SELECT_INPUT , +MUX_IN_GPC_PMIC_RDY_SELECT_INPUT , +MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT , +MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT , +MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT , +MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT , +MUX_IN_I2C3_IPP_SCL_IN_SELECT_INPUT , +MUX_IN_I2C3_IPP_SDA_IN_SELECT_INPUT , +MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT , +MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT , +MUX_IN_IPU_IPP_IND_SENS1_DATA_EN_SELECT_INPUT , +MUX_IN_IPU_IPP_IND_SENS1_HSYNC_SELECT_INPUT , +MUX_IN_IPU_IPP_IND_SENS1_VSYNC_SELECT_INPUT , +MUX_IN_KPP_IPP_IND_COL_5_SELECT_INPUT ,/*0x840*/ +MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT , +MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT , +MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT , +MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT , +MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT , +MUX_IN_MLB_MLBCLK_IN_SELECT_INPUT , +MUX_IN_MLB_MLBDAT_IN_SELECT_INPUT , +MUX_IN_MLB_MLBSIG_IN_SELECT_INPUT , +MUX_IN_OWIRE_BATTERY_LINE_IN_SELECT_INPUT , +MUX_IN_SDMA_EVENTS_14_SELECT_INPUT , +MUX_IN_SDMA_EVENTS_15_SELECT_INPUT , +MUX_IN_SPDIF_SPDIF_IN1_SELECT_INPUT ,/*0x870*/ +MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT , +MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT , +MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT , +MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT , +MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT , +MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT , +MUX_IN_UART4_IPP_UART_RTS_B_SELECT_INPUT , +MUX_IN_UART4_IPP_UART_RXD_MUX_SELECT_INPUT , +MUX_IN_UART5_IPP_UART_RTS_B_SELECT_INPUT , +MUX_IN_UART5_IPP_UART_RXD_MUX_SELECT_INPUT , +MUX_IN_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT , +MUX_IN_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT , +MUX_IN_USBOH3_IPP_IND_UH2_OC_SELECT_INPUT , +}iomux_input_select_t ; + +int mxc_request_iomux (iomux_pin_name_t pin,iomux_pin_cfg_t config); +void mxc_free_iomux (iomux_pin_name_t pin,iomux_pin_cfg_t config); +void mxc_iomux_set_pad (iomux_pin_name_t pin,u32 config); +unsigned int mxc_iomux_get_pad (iomux_pin_name_t pin); +void mxc_iomux_set_input (iomux_input_select_t input,u32 config); + +#endif /* __MACH_MX53_IOMUX_H__ */
arch/arm/include/asm/arch-mx53/mx53_pins.h new file +359 -0
359 lines not on this page · raw message
Signature · 1 line
1.7.0.4
PATCH 3/5 MX53: Add pin and multiplexer definitions.
Quoted 4 lines · Jason Liu
The patch add header files to support the pin multiplexer of the the Freescale i.MX53 processor.
Signed-off-by Jason Liu <[email protected]>
Hi Jason,
arch/arm/include/asm/arch-mx53/iomux.h
Quoted 6 lines
--- arch/arm/include/asm/arch-mx53/iomux.h | 193 +++++++++++++++ arch/arm/include/asm/arch-mx53/mx53_pins.h | 359 ++++++++++++++++++++++++++++ 2 files changed, 552 insertions(+), 0 deletions(-)arch/arm/include/asm/arch-mx53/iomux.h +0
-0
As I said for the previous patches, we must avoid to duplicate files. This file must be merged with mx51 counterpart. As I see, the two files have small differences.
arch/arm/include/asm/arch-mx53/mx53_pins.h
Quoted 2 lines
arch/arm/include/asm/arch-mx53/mx53_pins.h new file +0
-0
Definitions for mx53 are different as for mx51, so probably it is not possible to merge them in a single structure. But we can have a single file (mx5_pins.h, maybe ?), using #ifdef to set the different pins.
arch/arm/include/asm/arch-mx53/mx53_pins.h line 100
Quoted 3 lines
arch/arm/include/asm/arch-mx53/mx53_pins.h new file +3
-0+enum iomux_pins { +MX53_PIN_GPIO_19 =_MXC_BUILD_GPIO_PIN (3 ,5 ,1 ,0x20 ,0x348 ), +MX53_PIN_KEY_COL0 =_MXC_BUILD_GPIO_PIN (3 ,6 ,1 ,0x24 ,0x34C ),
I think the best way should be to get rid of the cpu related names, and use a more general approach. For exammple, we have MX51_PIN_KEY_COL0 defined for the MX51. It should be better to have for example MX5_PIN_KEY_COL0, whose value is different if our target is a MX51 or MX53.
What do you think ?
Best regards,
Stefano Babic
Signature · 5 lines
===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de =====================================================================
PATCH 3/5 MX53: Add pin and multiplexer definitions.
Hi, Stefano,
Quoted 44 lines
-----Original Message-----
From: Stefano Babic [mailto:sbabic at denx.de]
Sent: 2010?6?18? 17:48
To: Liu Hui-R64343
Cc: wd at denx.de; u-boot at lists.denx.de
Subject: Re: [U-Boot] [U-BOOT][PATCH 3/5] MX53: Add pin and multiplexer definitions.Quoted 4 lines · Jason Liu
The patch add header files to support the pin multiplexer of the the Freescale i.MX53 processor.
Signed-off-by Jason Liu <[email protected]>Hi Jason,
arch/arm/include/asm/arch-mx53/iomux.h
Quoted 8 lines
--- arch/arm/include/asm/arch-mx53/iomux.h | 193 +++++++++++++++ arch/arm/include/asm/arch-mx53/mx53_pins.h | 359 ++++++++++++++++++++++++++++ 2 files changed, 552 insertions(+), 0 deletions(-)arch/arm/include/asm/arch-mx53/iomux.h +0
-0As I said for the previous patches, we must avoid to duplicate files.
This file must be merged with mx51 counterpart. As I see, the two files have small differences.arch/arm/include/asm/arch-mx53/mx53_pins.h
Quoted 3 lines
arch/arm/include/asm/arch-mx53/mx53_pins.h new file +0
-0Definitions for mx53 are different as for mx51, so probably it is not possible to merge them in a single structure. But we can have a single file (
mx5_pins.h, maybe ?), using #ifdef to set the different pins.arch/arm/include/asm/arch-mx53/mx53_pins.h line 100
Quoted 3 lines
arch/arm/include/asm/arch-mx53/mx53_pins.h new file +3
-0+enum iomux_pins { +MX53_PIN_GPIO_19 =_MXC_BUILD_GPIO_PIN (3 ,5 ,1 ,0x20 ,0x348 ), +MX53_PIN_KEY_COL0 =_MXC_BUILD_GPIO_PIN (3 ,6 ,1 ,0x24 ,0x34C ),I think the best way should be to get rid of the cpu related names, and use a more general approach. For exammple, we have
MX51_PIN_KEY_COL0defined for the MX51. It should be better to have for exampleMX5_PIN_KEY_COL0, whose value is different if our target is a MX51 or MX53.
Quoted 1 line
What do you think ?
Yes, agree. Thank you.
Quoted 10 lines
Best regards,
Stefano Babic--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
PATCH 4/5 serial_mxc: add support for MX53 processor
In reply to Jason LiuThe patch adds support for the Freescale mx53 processor.
--- drivers/serial/serial_mxc.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-)
drivers/serial/serial_mxc.c +7 -0
@@ -55,6 +55,13 @@#define UART_PHYS UART2_BASE_ADDR#elif defined(CONFIG_SYS_MX51_UART3 )#define UART_PHYS UART3_BASE_ADDR +#elif defined(CONFIG_SYS_MX53_UART1 ) +#define UART_PHYS UART1_BASE_ADDR +#elif defined(CONFIG_SYS_MX53_UART2 ) +#define UART_PHYS UART2_BASE_ADDR +#elif defined(CONFIG_SYS_MX53_UART3 ) +#define UART_PHYS UART3_BASE_ADDR +#else #error "define CONFIG_SYS_MXxx_UARTx to use the MXC UART driver"#endif
Signature · 1 line
1.7.0.4
PATCH 4/5 serial_mxc: add support for MX53 processor
Quoted 4 lines · Jason Liu
The patch adds support for the Freescale mx53 processor.
Signed-off-by Jason Liu <[email protected]>---
Hi Jason,
Quoted 8 lines
drivers/serial/serial_mxc.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-)drivers/serial/serial_mxc.c +0
-0
drivers/serial/serial_mxc.c line 63
Quoted 9 lines
drivers/serial/serial_mxc.c +6
-0@@ -55,6 +55,13 @@#define UART_PHYS UART2_BASE_ADDR#elif defined(CONFIG_SYS_MX51_UART3 )#define UART_PHYS UART3_BASE_ADDR +#elif defined(CONFIG_SYS_MX53_UART1 ) +#define UART_PHYS UART1_BASE_ADDR +#elif defined(CONFIG_SYS_MX53_UART2 ) +#define UART_PHYS UART2_BASE_ADDR +#elif defined(CONFIG_SYS_MX53_UART3 ) +#define UART_PHYS UART3_BASE_ADDR
There are really no difference between MX51 and MX53, both set the same values to UART_PHYS (at least as constant: even if the physical address is different, must be unified at this place). I suggest something like CONFIG_SYS_MX_UART1/2/3, that must be used for both MX51 and MX53.
Best regards,
Stefano Babic
Signature · 5 lines
===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de =====================================================================
PATCH 4/5 serial_mxc: add support for MX53 processor
Hi, Stefano
Quoted 28 lines
-----Original Message-----
From: Stefano Babic [mailto:sbabic at denx.de]
Sent: 2010?6?18? 17:52
To: Liu Hui-R64343
Cc: wd at denx.de; u-boot at lists.denx.de
Subject: Re: [U-Boot] [U-BOOT][PATCH 4/5]serial_mxc: add support for MX53 processorQuoted 4 lines · Jason Liu
The patch adds support for the Freescale mx53 processor.
Signed-off-by Jason Liu <[email protected]>---
Hi Jason,
Quoted 13 lines
drivers/serial/serial_mxc.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-)drivers/serial/serial_mxc.c +2
-0@@ -55,6 +55,13 @@#define UART_PHYS UART2_BASE_ADDR#elif defined(CONFIG_SYS_MX51_UART3 )#define UART_PHYS UART3_BASE_ADDR +#elif defined(CONFIG_SYS_MX53_UART1 ) +#define UART_PHYS UART1_BASE_ADDR
Quoted 8 lines
drivers/serial/serial_mxc.c line 63
Quoted 4 lines
drivers/serial/serial_mxc.c +4
-0+#elif defined(CONFIG_SYS_MX53_UART2 ) +#define UART_PHYS UART2_BASE_ADDR +#elif defined(CONFIG_SYS_MX53_UART3 ) +#define UART_PHYS UART3_BASE_ADDRThere are really no difference between MX51 and MX53, both set the same values to
UART_PHYS(at least as constant: even if the physical address is different, must be unified at this place). I suggest something like CONFIG_SYS_MX_UART1/2/3, that must be used for both MX51 and MX53.
Good idea!
Quoted 10 lines
Best regards,
Stefano Babic--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
PATCH 5/5 Add initial support for Freescale mx53evk board
In reply to Jason LiuThe patch adds initial support for the Freescale mx53evk board. SD/MMC boot is supported
--- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + arch/arm/include/asm/arch-mx53/sys_proto.h | 30 ++ board/freescale/mx53evk/Makefile | 49 ++++ board/freescale/mx53evk/config.mk | 24 ++ board/freescale/mx53evk/flash_header.S | 120 ++++++++ board/freescale/mx53evk/mx53evk.c | 411 ++++++++++++++++++++++++++++ include/configs/mx53evk.h | 186 +++++++++++++ 9 files changed, 828 insertions(+), 0 deletions(-)
MAINTAINERS +4 -0
@@ -152,6 +152,10 @@ Fred Fan <[email protected]> mx51evk i.MX51 +Jason Liu <[email protected]> + + mx53evk i.MX53 + Thomas Frieden <[email protected]> AmigaOneG3SE MPC7xx
MAKEALL +1 -0
@@ -643,6 +643,7 @@ LIST_ARM11=" \ LIST_ARM_CORTEX_A8=" \ devkit8000 \ mx51evk \ + mx53evk \ omap3_beagle \ omap3_overo \ omap3_evm \
Makefile +3 -0
@@ -3301,6 +3301,9 @@ mx31pdk_nand_config : unconfig mx51evk_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx51evk freescale mx51 +mx53evk_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx53evk freescale mx53 + omap2420h4_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 ti omap24xx
arch/arm/include/asm/arch-mx53/sys_proto.h new file +30 -0
@@ -0,0 +1,30 @@ +/* +* (C) Copyright 2009 +* Stefano Babic, DENX Software Engineering, sbabic at denx.de. +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +u32 get_cpu_rev (void ); +#define is_soc_rev (rev) ((get_cpu_rev() & 0xFF) - rev) + +#endif
board/freescale/mx53evk/Makefile new file +49 -0
49 lines not on this page · raw message
board/freescale/mx53evk/config.mk new file +24 -0
@@ -0,0 +1,24 @@ +# +# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +LDSCRIPT = $(CPUDIR)/$(SOC)/u-boot.lds +TEXT_BASE = 0x77800000
board/freescale/mx53evk/flash_header.S new file +120 -0
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board/freescale/mx53evk/mx53evk.c new file +411 -0
411 lines not on this page · raw message
include/configs/mx53evk.h new file +186 -0
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Signature · 1 line
1.7.0.4
PATCH 5/5 Add initial support for Freescale mx53evk board
Dear Jason Liu,
Quoted 4 lines · In message <[email protected]> you wrote:
The patch adds initial support for the Freescale mx53evk board. SD/MMC boot is supported
Signed-off-by Jason Liu <[email protected]>
In addition to Stefano's comments (he is perfectly right: it makes zero sense to create another CPU directory, this needs to be unified with the mx51 support):
Makefile mx31pdk_nand_config : unconfig · line 3308
Quoted 13 lines
Makefile +3
-0@@ -3301,6 +3301,9 @@ mx31pdk_nand_config : unconfig mx51evk_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx51evk freescale mx51 +mx53evk_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx53evk freescale mx53 + omap2420h4_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 ti omap24xx
We don't accept such changes to the Makefile any more. Please add your board to boards.cfg instead. You need to rebase your code against the "next" branch.
Best regards,
Wolfgang Denk
Signature · 8 lines
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
I wrote my name at the top of the page. I wrote down the number of
the question ``1''. After much reflection I put a bracket round it
thus ``(1)''. But thereafter I could not think of anything connected
with it that was either relevant or true.
- Sir Winston Churchill _My Early Life_ ch. 2PATCH 5/5 Add initial support for Freescale mx53evk board
In reply to Jason LiuQuoted 4 lines · Jason Liu
The patch adds initial support for the Freescale mx53evk board. SD/MMC boot is supported
Signed-off-by Jason Liu <[email protected]>
Hi Jason,
arch/arm/include/asm/arch-mx53/sys_proto.h
Quoted 1 line
arch/arm/include/asm/arch-mx53/sys_proto.h +0
-0
Identical to arch-mx51/sys_proto.h Do not add copies of current files.
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board/freescale/mx53evk/Makefile new file +17
-0@@ -0,0 +1,49 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <[email protected]> +# +# (C) Copyright 2009 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software
board/freescale/mx53evk/Makefile line 27
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board/freescale/mx53evk/Makefile new file +10
-0+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := mx53evk.o +SOBJS := flash_header.o
As I said, it was decided to use a different approach to set the DCD table. Linking the table directly to u-boot will not be accepted.
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board/freescale/mx53evk/mx53evk.c new file +32
-0@@ -0,0 +1,411 @@ +/* +* (C) Copyright 2010 Freescale Semiconductor, Inc. +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx53_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/iomux.h> +#include <asm/errno.h> +#include <asm/arch/crm_regs.h> +#include <i2c.h> +#include <mmc.h>
board/freescale/mx53evk/mx53evk.c line 42
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board/freescale/mx53evk/mx53evk.c new file +10
-0+#include <fsl_esdhc.h> + +DECLARE_GLOBAL_DATA_PTR ; + +static u32 system_rev; + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[2 ] = { + {MMC_SDHC1_BASE_ADDR ,1 }, + {MMC_SDHC3_BASE_ADDR, 1},
The structure is not correct. There are changes in fsl_esdhc and the structure contains only one field (the address). Please fix it (check with the code in mx51evk.c)
board/freescale/mx53evk/mx53evk.c line 51
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board/freescale/mx53evk/mx53evk.c new file +6
-0+u32 inline get_board_rev (void ) +{ + +return (system_rev >>8 ) &0xF ; +} +
Can you explain where is the revision coming ? system_rev contains the CPU version, because is is assigne via get_cpu_rev(). Are we assuming boad revision = cpu revision ? On mx51evk only a cpu revision is printed, because I had no idea where I could ge a board version.
board/freescale/mx53evk/mx53evk.c line 55
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board/freescale/mx53evk/mx53evk.c new file +4
-0+inline void set_board_rev (int rev) +{ + system_rev |= (rev &0xF ) <<8 ; +}
This seems dead code. Please drop it.
board/freescale/mx53evk/mx53evk.c line 75
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board/freescale/mx53evk/mx53evk.c new file +6
-0+ +static void setup_iomux_uart (void ) +{ +/* UART1 RXD */ +mxc_request_iomux (MX53_PIN_CSI0_D11 ,IOMUX_CONFIG_ALT2 ); +mxc_iomux_set_pad (MX53_PIN_CSI0_D11 ,0x1E4 );
Could you use or add some constants to better explain what you are doing here ? If I am not wrong, this should be substituted by:
mxc_iomux_set_pad(MX53_PIN_CSI0_D11, PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
Probably I used the wrong constants, but as sure it is easier to understand as simply 0x1E4. Can you fix globally ?
board/freescale/mx53evk/mx53evk.c line 89
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board/freescale/mx53evk/mx53evk.c new file +7
-0+static void setup_iomux_fec (void ) +{ +/*FEC_MDIO*/ +mxc_request_iomux (MX53_PIN_FEC_MDIO ,IOMUX_CONFIG_ALT0 ); +mxc_iomux_set_pad (MX53_PIN_FEC_MDIO ,0x1FC ); +mxc_iomux_set_input (MUX_IN_FEC_FEC_MDI_SELECT_INPUT ,0x1 ); +
Ditto. Please use constants.
board/freescale/mx53evk/mx53evk.c line 127
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board/freescale/mx53evk/mx53evk.c new file +1
-0+#ifdef CONFIG_MXC_SPI
You do not set CONFIG_MXC_SPI, so it seems this is dead code. Drop it if unnecessary, you can introduce it when SPI is required.
Quoted 16 lines
board/freescale/mx53evk/mx53evk.c new file +16
-0+void spi_io_init (struct imx_spi_dev_t *dev) +{ +switch (dev->base) { +case CSPI1_BASE_ADDR : +/* Select mux mode: ALT4 mux port: MOSI of instance: ecspi1 */ +mxc_request_iomux (MX53_PIN_EIM_D18 ,IOMUX_CONFIG_ALT4 ); +mxc_iomux_set_pad (MX53_PIN_EIM_D18 ,0x104 ); +mxc_iomux_set_input ( +MUX_IN_ECSPI1_IPP_IND_MOSI_SELECT_INPUT ,0x3 ); + +/* Select mux mode: ALT4 mux port: MISO of instance: ecspi1. */ +mxc_request_iomux (MX53_PIN_EIM_D17 ,IOMUX_CONFIG_ALT4 ); +mxc_iomux_set_pad (MX53_PIN_EIM_D17 ,0x104 ); +mxc_iomux_set_input ( +MUX_IN_ECSPI1_IPP_IND_MISO_SELECT_INPUT ,0x3 ); +
board/freescale/mx53evk/mx53evk.c line 153
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board/freescale/mx53evk/mx53evk.c new file +10
-0+if (dev->ss ==0 ) { +/* de-select SS1 of instance: ecspi1. */ +mxc_request_iomux (MX53_PIN_EIM_D19 ,IOMUX_CONFIG_ALT1 ); +mxc_iomux_set_pad (MX53_PIN_EIM_D19 ,0x1E4 ); + +/* mux mode: ALT4 mux port: SS0 of instance: ecspi1. */ +mxc_request_iomux (MX53_PIN_EIM_EB2 ,IOMUX_CONFIG_ALT4 ); +mxc_iomux_set_pad (MX53_PIN_EIM_EB2 ,0x104 ); +mxc_iomux_set_input ( +MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT ,0x3 );
Has the MX53 the same errata as the MX51 ? Logically, we do not need to deselect pins in the multiplexer when we are simply changing the chip select to access a different device. However, I know the errata for MX51
and this code is required in case the chip select is active high
instead of low. Really do we need this code for mx53evk ?
Quoted 9 lines
board/freescale/mx53evk/mx53evk.c new file +9
-0+#ifdef CONFIG_I2C_MXC +static void setup_core_voltages (void ) +{ +unsigned char buf[4 ] = {0 }; +i2c_init (CONFIG_SYS_I2C_SPEED ,CONFIG_SYS_I2C_SLAVE ); + +/* Set core voltage VDDGP to 1.1V */ + buf[0 ] =0x45 ; + buf[1 ] =0x4a ;
board/freescale/mx53evk/mx53evk.c line 199
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board/freescale/mx53evk/mx53evk.c new file +10
-0+ buf[2 ] =0x54 ; +if (i2c_write (0x8 ,24 ,1 , buf,3 )) +return ; + +/* Set DDR voltage VDDA to 1.225V */ + buf[0 ] =0 ; + buf[1 ] =0x63 ; + buf[2 ] =0x1a ; +if (i2c_write (0x8 ,26 ,1 , buf,3 )) +return ;
I do not know what is connected on the I2C bus, and I cannot understand the code. I can only suppose there is a Power Controller, as the mx51evk has, but in this case the I2C instead of SPI is used. However, we need an header file to describe the internal register of this chip (at least for the registers you are using !).
board/freescale/mx53evk/mx53evk.c line 211
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board/freescale/mx53evk/mx53evk.c new file +7
-0+#ifdef CONFIG_FSL_ESDHC +int board_mmc_getcd (u8 *cd,struct mmc *mmc) +{ + *cd =0 ; + +return 0 ; +}
I do not understand, the code seems wrong. The function is a weak function, if you do not need, you do not need to implement. It seems you suppose that a SD card is *always* inserted, even if this is not true.
board/freescale/mx53evk/mx53evk.c line 378
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board/freescale/mx53evk/mx53evk.c new file +4
-0+puts ("Boot Device: " ); +switch (get_boot_device ()) { +case WEIM_NOR_BOOT : +printf ("NOR\n" );
Use puts if you do not need to format variables.
board/freescale/mx53evk/mx53evk.c line 126
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board/freescale/mx53evk/mx53evk.c new file +4
-0+/* +* Disabled for now due to build problems under Debian and a significant +* increase in the final file size: 144260 vs. 109536 Bytes. +*/
Comments unclear. What do you have disabled ?
board/freescale/mx53evk/mx53evk.c line 139
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board/freescale/mx53evk/mx53evk.c new file +13
-0+/* +* Hardware drivers +*/ +#define CONFIG_MXC_UART +#define CONFIG_SYS_MX53_UART1 + +/* +* Eth Configs +*/ +#define CONFIG_NET_MULTI +#define CONFIG_MII +#define CONFIG_MII_GASKET +#define CONFIG_DISCOVER_PHY
Why is CONFIG_FEC_MXC not set ? You set network parameters, but I do not see a network driver. And it seems CONFIG_DISCOVER_PHY is obsolete (must be removed from mx51evk, too).
board/freescale/mx53evk/mx53evk.c line 147
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board/freescale/mx53evk/mx53evk.c new file +8
-0+ +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS
Network commands, but no ethernet driver...
Best regards,
Stefano Babic
Signature · 5 lines
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