Series short description
Subsystems (2)
cover Series short description
The following series implements support for Marvell 88F6282 SoC. It should take into account all previously made comments.
---
Benjamin Zores (4):
arch/arm/mach-kirkwood: update MPP definition. arch/arm/mach-kirkwood: add support for 88F6282-A0 revision arch/arm/mach-kirkwood: add support for 2nd PCIe port on 88f6282. arch/arm/mach-kirkwood: add support for 2nd TWSI controller on 88f6282.
arch/arm/mach-kirkwood/addr-map.c | 21 + arch/arm/mach-kirkwood/common.c | 90 +++ arch/arm/mach-kirkwood/common.h | 10 arch/arm/mach-kirkwood/db88f6281-bp-setup.c | 2 arch/arm/mach-kirkwood/include/mach/bridge-regs.h | 3 arch/arm/mach-kirkwood/include/mach/irqs.h | 4 arch/arm/mach-kirkwood/include/mach/kirkwood.h | 43 +- arch/arm/mach-kirkwood/mpp.c | 2 arch/arm/mach-kirkwood/mpp.h | 595 +++++++++++---------- arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c | 2 arch/arm/mach-kirkwood/netspace_v2-setup.c | 6 arch/arm/mach-kirkwood/netxbig_v2-setup.c | 34 + arch/arm/mach-kirkwood/openrd-setup.c | 4 arch/arm/mach-kirkwood/pcie.c | 204 +++++-- arch/arm/mach-kirkwood/rd88f6192-nas-setup.c | 2 arch/arm/mach-kirkwood/rd88f6281-setup.c | 2 arch/arm/mach-kirkwood/ts219-setup.c | 8 arch/arm/mach-kirkwood/ts41x-setup.c | 32 + 18 files changed, 663 insertions(+), 401 deletions(-)
Signature · 1 line
Signature
PATCH 1/4 arch/arm/mach-kirkwood: update MPP definition.
Add MPP definitions for Marvell Kirkwood 88F6282 revision. Update some defines to reflect datasheet's MPP names.
Signed-off-by Benjamin Zores <[email protected]>
--- arch/arm/mach-kirkwood/mpp.h | 595 +++++++++++++++------------- arch/arm/mach-kirkwood/netspace_v2-setup.c | 4 arch/arm/mach-kirkwood/netxbig_v2-setup.c | 32 +- arch/arm/mach-kirkwood/ts219-setup.c | 4 arch/arm/mach-kirkwood/ts41x-setup.c | 28 + 5 files changed, 356 insertions(+), 307 deletions(-)
arch/arm/mach-kirkwood/mpp.h +322 -273
@@ -11,7 +11,7 @@#ifndef __KIRKWOOD_MPP_H#define __KIRKWOOD_MPP_H -#define MPP (_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \ +#define MPP (_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281, _F6282) ( \/* MPP number */ ((_num) &0xff ) | \/* MPP select value */ (((_sel) &0xf ) <<8 ) | \ /* may be input signal */ ((!!(_in)) << 12) | \
@@ -19,282 +19,331 @@ /* available on F6180 */ ((!!(_F6180)) << 14) | \ /* available on F6190 */ ((!!(_F6190)) << 15) | \ /* available on F6192 */ ((!!(_F6192)) << 16) | \ - /* available on F6281 */ ((!!(_F6281)) << 17)) + /* available on F6281 */ ((!!(_F6281)) << 17) | \ + /* available on F6282 */ ((!!(_F6282)) << 18))#define MPP_NUM (x) ((x) & 0xff)#define MPP_SEL (x) (((x) >> 8) & 0xf) -/* num sel i o 6180 6190 6192 6281 */ - -#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0 ) -#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0 ) - -#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0 ) -#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0 ) -#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0 ) -#define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1 ) - -#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1 ) - -#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1 ) - -#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1 ) - -#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1 ) - -#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1 ) -#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1 ) -#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1 ) - -#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1 ) -#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1 ) - -#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1 ) -#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1 ) - -#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1 ) -#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 ) - -#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 ) -#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1 ) -#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1 ) -#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1 ) -#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1 ) - -#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP9_TW_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1 ) -#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1 ) -#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1 ) -#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1 ) -#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1 ) - -#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1 ) -#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1 ) -#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1 ) - -#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1 ) -#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1 ) -#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1 ) -#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1 ) -#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1 ) -#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1 ) - -#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1 ) - -#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1 ) - -#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1 ) -#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1 ) -#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1 ) - -#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1 ) -#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1 ) - -#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1 ) -#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1 ) -#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1 ) -#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1 ) - -#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1 ) - -#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1 ) - -#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1 ) - -#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP20_GE1_0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP20_AUDIO_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1 ) -#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1 ) - -#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP21_GE1_1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP21_AUDIO_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1 ) -#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1 ) - -#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP22_GE1_2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP22_AUDIO_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1 ) -#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1 ) - -#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1 ) -#define MPP23_GE1_3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP23_AUDIO_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1 ) -#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1 ) - -#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP24_TDM_SPI_CS0 DEV( 24, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP24_GE1_4 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP24_AUDIO_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1 ) - -#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP25_GE1_5 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP25_AUDIO_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1 ) - -#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1 ) -#define MPP26_GE1_6 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP26_AUDIO_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1 ) - -#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP27_GE1_7 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP27_AUDIO_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1 ) - -#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1 ) -#define MPP28_GE1_8 MPP( 28, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP28_AUDIO_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1 ) - -#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1 ) -#define MPP29_GE1_9 MPP( 29, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1 ) -#define MPP30_GE1_10 MPP( 30, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1 ) -#define MPP31_GE1_11 MPP( 31, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1 ) -#define MPP32_GE1_12 MPP( 32, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP33_GPIO MPP( 33, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP33_GE1_13 MPP( 33, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP34_GE1_14 MPP( 34, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP35_GE1_15 MPP( 35, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1 ) -#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1 ) - -#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP36_AUDIO_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1 ) - -#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP37_AUDIO_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP38_AUDIO_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP39_AUDIO_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP40_AUDIO_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1 ) -#define MPP41_AUDIO_I2SLRC MPP( 41, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP42_AUDIO_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1 ) -#define MPP43_AUDIO_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1 ) - -#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1 ) -#define MPP44_AUDIO_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1 ) - -#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1 ) -#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1 ) - -#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1 ) -#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1 ) - -#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1 ) -#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1 ) - -#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1 ) -#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1 ) - -#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1 ) -#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1 ) +/* num sel i o 6180 6190 6192 6281 6282 */ + +#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0, 0 ) +#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0, 0 ) + +#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0, 0 ) +#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0, 0 ) +#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0, 0 ) +#define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1, 0 ) +#define MPP_F6282_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1, 1 ) + +#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1, 1 ) + +#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1, 1 ) + +#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1, 1 ) + +#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP4_LCD_VGA_HSYNC MPP( 4, 0xb, 0, 0, 0, 0, 0, 0, 1 ) +#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1, 0 ) + +#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1, 0 ) +#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1, 1 ) +#define MPP5_LCD_VGA_VSYNC MPP( 5, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1, 0 ) + +#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1, 0 ) +#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1, 0 ) +#define MPP7_LCD_PWM MPP( 7, 0xb, 0, 1, 0, 0, 0, 0, 1 ) + +#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP8_TW0_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1, 1 ) +#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1, 0 ) +#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1, 1 ) + +#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP9_TW0_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1, 1 ) +#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1, 0 ) +#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1, 1 ) + +#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1, 0 ) + +#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1, 0 ) +#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1, 0 ) +#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1, 0 ) +#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1, 1 ) + +#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 1, 0, 0, 0, 0, 1 ) +#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 1, 0, 0, 0, 0, 1 ) +#define MPP12_TW1_SDA MPP( 12, 0xd, 1, 0, 0, 0, 0, 0, 1 ) + +#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 1, 0, 0, 0, 0, 1 ) +#define MPP13_LCDPWM MPP( 13, 0xb, 0, 1, 0, 0, 0, 0, 1 ) + +#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP14_AU_SPDIFI MPP( 14, 0xa, 1, 0, 0, 0, 0, 0, 1 ) +#define MPP14_AU_I2SDI MPP( 14, 0xb, 1, 0, 0, 0, 0, 0, 1 ) +#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1, 1 ) + +#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1, 1 ) +#define MPP15_SPI_CSn MPP( 15, 0xb, 0, 1, 0, 0, 0, 0, 1 ) + +#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 1, 0, 0, 0, 0, 0, 1 ) +#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1, 1 ) + +#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1, 1 ) +#define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 1, 0, 0, 0, 0, 1 ) +#define MPP17_TW1_SCK MPP( 17, 0xd, 1, 1, 0, 0, 0, 0, 1 ) + +#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 1, 0, 0, 0, 0, 1 ) + +#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1, 1 ) + +#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP20_GE1_TXD0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP20_AU_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1, 1 ) +#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP20_LCD_D0 MPP( 20, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP21_GE1_TXD1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1, 1 ) +#define MPP21_LCD_D1 MPP( 21, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP22_GE1_TXD2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP22_LCD_D2 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1, 1 ) +#define MPP23_GE1_TXD3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1, 1 ) +#define MPP23_LCD_D3 MPP( 23, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP24_GE1_RXD0 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP24_LCD_D4 MPP( 24, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP25_GE1_RXD1 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP25_LCD_D5 MPP( 25, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1, 1 ) +#define MPP26_GE1_RXD2 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP26_LCD_D6 MPP( 26, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP27_GE1_RXD3 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP27_AU_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1, 1 ) +#define MPP27_LCD_D7 MPP( 27, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP28_GE1_COL MPP( 28, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP28_AU_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1, 1 ) +#define MPP28_LCD_D8 MPP( 28, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP29_GE1_TCLK MPP( 29, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP29_LCD_D9 MPP( 29, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP30_GE1_RXCTL MPP( 30, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP30_LCD_D10 MPP( 30, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP31_GE1_RXCLK MPP( 31, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP31_LCD_D11 MPP( 31, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1, 1 ) +#define MPP32_GE1_TCLKOUT MPP( 32, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP32_LCD_D12 MPP( 32, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP33_GPO MPP( 33, 0x0, 0, 1, 0, 1, 1, 1, 1 ) +#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP33_GE1_TXCTL MPP( 33, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP33_LCD_D13 MPP( 33, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1, 1 ) +#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP34_GE1_TXEN MPP( 34, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP34_LCD_D14 MPP( 34, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP35_GE1_RXERR MPP( 35, 0x3, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1, 1 ) +#define MPP35_LCD_D15 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) +#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1, 1 ) + +#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP36_AU_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1, 1 ) +#define MPP36_TW1_SDA MPP( 36, 0xb, 1, 1, 0, 0, 0, 0, 1 ) + +#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1, 1 ) +#define MPP37_TW1_SCK MPP( 37, 0xb, 1, 1, 0, 0, 0, 0, 1 ) + +#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1, 1 ) +#define MPP38_LCD_D18 MPP( 38, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1, 1 ) +#define MPP39_LCD_D19 MPP( 39, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1, 1 ) +#define MPP40_LCD_D20 MPP( 40, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1, 1 ) +#define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 1, 1, 0, 0, 1, 1 ) +#define MPP41_LCD_D21 MPP( 41, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1, 1 ) +#define MPP42_LCD_D22 MPP( 42, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP43_AU_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1, 1 ) +#define MPP43_LCD_D23 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1, 1 ) +#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP44_AU_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1, 1 ) +#define MPP44_LCD_CLK MPP( 44, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP245_LCD_E MPP( 45, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP46_LCD_HSYNC MPP( 46, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1, 1 ) +#define MPP47_LCD_VSYNC MPP( 47, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP48_LCD_D16 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) + +#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1, 0 ) +#define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 1, 0, 0, 0, 0, 1 ) +#define MPP49_LCD_D17 MPP( 49, 0xb, 0, 0, 0, 0, 0, 0, 1 )#define MPP_MAX 49
arch/arm/mach-kirkwood/netspace_v2-setup.c +2 -2
@@ -249,8 +249,8 @@ static unsigned int netspace_v2_mpp_config[] __initdata = {MPP4_NF_IO6 ,MPP5_NF_IO7 , MPP6_SYSRST_OUTn, -MPP8_TW_SDA , -MPP9_TW_SCK , +MPP8_TW0_SDA , +MPP9_TW0_SCK ,MPP10_UART0_TXD ,MPP11_UART0_RXD , MPP12_GPO, /* Red led */
arch/arm/mach-kirkwood/netxbig_v2-setup.c +16 -16
@@ -270,8 +270,8 @@ static unsigned int net2big_v2_mpp_config[] __initdata = {MPP3_SPI_MISO , MPP6_SYSRST_OUTn,MPP7_GPO ,/* Request power-off */ -MPP8_TW_SDA , -MPP9_TW_SCK , +MPP8_TW0_SDA , +MPP9_TW0_SCK ,MPP10_UART0_TXD ,MPP11_UART0_RXD , MPP13_GPIO, /* Rear power switch (on|auto) */
@@ -306,8 +306,8 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {MPP3_SPI_MISO , MPP6_SYSRST_OUTn,MPP7_GPO ,/* Request power-off */ -MPP8_TW_SDA , -MPP9_TW_SCK , +MPP8_TW0_SDA , +MPP9_TW0_SCK ,MPP10_UART0_TXD ,MPP11_UART0_RXD , MPP13_GPIO, /* Rear power switch (on|auto) */
@@ -315,20 +315,20 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {MPP15_GPIO ,/* Rear power switch (auto|off) */ MPP16_GPIO ,/* SATA HDD1 power */ MPP17_GPIO ,/* SATA HDD2 power */ -MPP20_GE1_0 , -MPP21_GE1_1 , -MPP22_GE1_2 , -MPP23_GE1_3 , -MPP24_GE1_4 , -MPP25_GE1_5 , -MPP26_GE1_6 , -MPP27_GE1_7 , +MPP20_GE1_TXD0 , +MPP21_GE1_TXD1 , +MPP22_GE1_TXD2 , +MPP23_GE1_TXD3 , +MPP24_GE1_RXD0 , +MPP25_GE1_RXD1 , +MPP26_GE1_RXD2 , +MPP27_GE1_RXD3 ,MPP28_GPIO ,/* USB enable host vbus */ MPP29_GPIO ,/* CPLD extension ALE */ -MPP30_GE1_10 , -MPP31_GE1_11 , -MPP32_GE1_12 , -MPP33_GE1_13 , +MPP30_GE1_RXCTL , +MPP31_GE1_RXCLK , +MPP32_GE1_TCLKOUT , +MPP33_GE1_TXCTL ,MPP34_GPIO ,/* Rear Push button */ MPP35_GPIO ,/* Inhibit switch power-off */ MPP36_GPIO, /* SATA HDD1 presence */
arch/arm/mach-kirkwood/ts219-setup.c +2 -2
@@ -74,8 +74,8 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {MPP3_SPI_MISO , MPP4_SATA1_ACTn, MPP5_SATA0_ACTn, -MPP8_TW_SDA , -MPP9_TW_SCK , +MPP8_TW0_SDA , +MPP9_TW0_SCK ,MPP10_UART0_TXD ,MPP11_UART0_RXD , MPP13_UART1_TXD, /* PIC controller */
arch/arm/mach-kirkwood/ts41x-setup.c +14 -14
@@ -78,26 +78,26 @@ static unsigned int qnap_ts41x_mpp_config[] __initdata = {MPP3_SPI_MISO , MPP6_SYSRST_OUTn, MPP7_PEX_RST_OUTn, -MPP8_TW_SDA , -MPP9_TW_SCK , +MPP8_TW0_SDA , +MPP9_TW0_SCK ,MPP10_UART0_TXD ,MPP11_UART0_RXD ,MPP13_UART1_TXD ,/* PIC controller */ MPP14_UART1_RXD ,/* PIC controller */ MPP15_SATA0_ACTn, MPP16_SATA1_ACTn, -MPP20_GE1_0 , -MPP21_GE1_1 , -MPP22_GE1_2 , -MPP23_GE1_3 , -MPP24_GE1_4 , -MPP25_GE1_5 , -MPP26_GE1_6 , -MPP27_GE1_7 , -MPP30_GE1_10 , -MPP31_GE1_11 , -MPP32_GE1_12 , -MPP33_GE1_13 , +MPP20_GE1_TXD0 , +MPP21_GE1_TXD1 , +MPP22_GE1_TXD2 , +MPP23_GE1_TXD3 , +MPP24_GE1_RXD0 , +MPP25_GE1_RXD1 , +MPP26_GE1_RXD2 , +MPP27_GE1_RXD3 , +MPP30_GE1_RXCTL , +MPP31_GE1_RXCLK , +MPP32_GE1_TCLKOUT , +MPP33_GE1_TXCTL ,MPP36_GPIO ,/* RAM: 0: 256 MB, 1: 512 MB */ MPP37_GPIO ,/* Reset button */ MPP43_GPIO, /* USB Copy button */
PATCH 1/4 arch/arm/mach-kirkwood: update MPP definition.
Quoted 3 lines · Benjamin Zores
Add MPP definitions for Marvell Kirkwood 88F6282 revision. Update some defines to reflect datasheet's MPP names.
Marvell published an errata note regarding 6282 MPPs. Attached is a slightly modified patch (for MPP49, others were ok).
Nicolas, Catalin, can you merge the 4 patches to your tree ?
Ben
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PATCH 2/4 arch/arm/mach-kirkwood: add support for 88F6282-A0 revision
In reply to Benjamin ZoresSigned-off-by Benjamin Zores <[email protected]>
--- arch/arm/mach-kirkwood/common.c | 10 +++++++++- arch/arm/mach-kirkwood/include/mach/kirkwood.h | 5 ++++- arch/arm/mach-kirkwood/mpp.c | 2 ++ 3 files changed, 15 insertions(+), 2 deletions(-)
arch/arm/mach-kirkwood/common.c +9 -1
@@ -402,7 +402,7 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)u32 dev, rev;kirkwood_pcie_id (&dev, &rev); -if (rev ==0 )/* catch all Kirkwood Z0's */ +if (rev ==0 && dev !=MV88F6282_DEV_ID )/* catch all Kirkwood Z0's and 6282 */ mvsdio_data->clock =100000000 ;else mvsdio_data->clock =200000000 ;
@@ -851,6 +851,9 @@ int __init kirkwood_find_tclk(void) rev == MV88F6281_REV_A1))return 200000000 ; +if (dev ==MV88F6282_DEV_ID ) +return 200000000 ; +return 166666667 ; }
@@ -886,6 +889,11 @@ static char * __init kirkwood_id(void)return "MV88F6281-A1" ; else return "MV88F6281-Rev-Unsupported"; + }if (dev ==MV88F6282_DEV_ID ) { +if (rev ==MV88F6282_REV_A0 ) +return "MV88F6282-A0" ; +else +return "MV88F6282-Rev-Unsupported" ; }else if (dev ==MV88F6192_DEV_ID ) {if (rev ==MV88F6192_REV_Z0 )return "MV88F6192-Z0" ;
arch/arm/mach-kirkwood/include/mach/kirkwood.h +4 -1
@@ -2,7 +2,7 @@* arch/arm/mach-kirkwood/include/mach/kirkwood.h * * Generic definitions for Marvell Kirkwood SoC flavors: -* 88F6180, 88F6192 and 88F6281. +* 88F6180, 88F6192, 88F6281 and 88F6282. * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any
@@ -104,6 +104,9 @@#define MV88F6281_REV_A0 2#define MV88F6281_REV_A1 3 +#define MV88F6282_DEV_ID 0x6282 +#define MV88F6282_REV_A0 0 +#define MV88F6192_DEV_ID 0x6192#define MV88F6192_REV_Z0 0#define MV88F6192_REV_A0 2
arch/arm/mach-kirkwood/mpp.c +2 -0
@@ -25,6 +25,8 @@ static unsigned int __init kirkwood_variant(void)if (dev ==MV88F6281_DEV_ID && rev >=MV88F6281_REV_A0 )return MPP_F6281_MASK ; +if (dev ==MV88F6282_DEV_ID && rev >=MV88F6282_REV_A0 ) +return MPP_F6282_MASK ;if (dev ==MV88F6192_DEV_ID && rev >=MV88F6192_REV_A0 )return MPP_F6192_MASK ;if (dev ==MV88F6180_DEV_ID )
PATCH 3/4 arch/arm/mach-kirkwood: add support for 2nd PCIe port on 88f6282.
In reply to Benjamin ZoresSigned-off-by Benjamin Zores <[email protected]>
--- arch/arm/mach-kirkwood/addr-map.c | 21 ++ arch/arm/mach-kirkwood/common.c | 28 +++ arch/arm/mach-kirkwood/common.h | 5 - arch/arm/mach-kirkwood/db88f6281-bp-setup.c | 2 arch/arm/mach-kirkwood/include/mach/bridge-regs.h | 3 arch/arm/mach-kirkwood/include/mach/irqs.h | 1 arch/arm/mach-kirkwood/include/mach/kirkwood.h | 35 +++- arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c | 2 arch/arm/mach-kirkwood/openrd-setup.c | 2 arch/arm/mach-kirkwood/pcie.c | 204 ++++++++++++++++----- arch/arm/mach-kirkwood/rd88f6192-nas-setup.c | 2 arch/arm/mach-kirkwood/rd88f6281-setup.c | 2 arch/arm/mach-kirkwood/ts219-setup.c | 2 arch/arm/mach-kirkwood/ts41x-setup.c | 2 14 files changed, 237 insertions(+), 74 deletions(-)
arch/arm/mach-kirkwood/addr-map.c +17 -4
@@ -31,6 +31,8 @@#define ATTR_DEV_CS0 0x3e#define ATTR_PCIE_IO 0xe0#define ATTR_PCIE_MEM 0xe8 +#define ATTR_PCIE1_IO 0xd0 +#define ATTR_PCIE1_MEM 0xd8#define ATTR_SRAM 0x01/*
@@ -84,6 +86,8 @@ void __init kirkwood_setup_cpu_mbus(void)void __iomem *addr;int i;int cs; +int id =0 ; +u32 dev, rev;/* * First, disable and clear windows.
@@ -102,21 +106,30 @@ void __init kirkwood_setup_cpu_mbus(void)/* * Setup windows for PCIe IO+MEM space. */ -setup_cpu_win (0 ,KIRKWOOD_PCIE_IO_PHYS_BASE ,KIRKWOOD_PCIE_IO_SIZE , +setup_cpu_win (id++,KIRKWOOD_PCIE_IO_PHYS_BASE ,KIRKWOOD_PCIE_IO_SIZE ,TARGET_PCIE ,ATTR_PCIE_IO ,KIRKWOOD_PCIE_IO_BUS_BASE ); -setup_cpu_win (1 ,KIRKWOOD_PCIE_MEM_PHYS_BASE ,KIRKWOOD_PCIE_MEM_SIZE , +setup_cpu_win (id++,KIRKWOOD_PCIE_MEM_PHYS_BASE ,KIRKWOOD_PCIE_MEM_SIZE ,TARGET_PCIE ,ATTR_PCIE_MEM ,KIRKWOOD_PCIE_MEM_BUS_BASE ); +kirkwood_pcie_id (&dev, &rev); + +if (dev ==MV88F6282_DEV_ID ) { +setup_cpu_win (id++,KIRKWOOD_PCIE1_IO_PHYS_BASE ,KIRKWOOD_PCIE1_IO_SIZE , +TARGET_PCIE ,ATTR_PCIE1_IO ,KIRKWOOD_PCIE1_IO_BUS_BASE ); +setup_cpu_win (id++,KIRKWOOD_PCIE1_MEM_PHYS_BASE ,KIRKWOOD_PCIE1_MEM_SIZE , +TARGET_PCIE ,ATTR_PCIE1_MEM ,KIRKWOOD_PCIE1_MEM_BUS_BASE ); + } +/* * Setup window for NAND controller. */ -setup_cpu_win (2 ,KIRKWOOD_NAND_MEM_PHYS_BASE ,KIRKWOOD_NAND_MEM_SIZE , +setup_cpu_win (id++,KIRKWOOD_NAND_MEM_PHYS_BASE ,KIRKWOOD_NAND_MEM_SIZE ,TARGET_DEV_BUS ,ATTR_DEV_NAND ,-1 );/* * Setup window for SRAM. */ -setup_cpu_win (3 ,KIRKWOOD_SRAM_PHYS_BASE ,KIRKWOOD_SRAM_SIZE , +setup_cpu_win (id++,KIRKWOOD_SRAM_PHYS_BASE ,KIRKWOOD_SRAM_SIZE ,TARGET_SRAM ,ATTR_SRAM ,-1 );/*
arch/arm/mach-kirkwood/common.c +26 -2
@@ -44,6 +44,11 @@ static struct map_desc kirkwood_io_desc[] __initdata = { .length = KIRKWOOD_PCIE_IO_SIZE, .type = MT_DEVICE, }, { + .virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE, + .pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE), + .length = KIRKWOOD_PCIE1_IO_SIZE, + .type = MT_DEVICE, + }, { .virtual = KIRKWOOD_REGS_VIRT_BASE, .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE), .length = KIRKWOOD_REGS_SIZE,
@@ -957,12 +962,20 @@ void __init kirkwood_init(void)static int __init kirkwood_clock_gate (void ) {unsigned int curr =readl (CLOCK_GATING_CTRL ); +u32 dev, rev; +int flags;printk (KERN_DEBUG "Gating clock of unused units\n" );printk (KERN_DEBUG "before: 0x%08x\n" , curr); +kirkwood_pcie_id (&dev, &rev); +/* Make sure those units are accessible */ -writel (curr |CGC_SATA0 |CGC_SATA1 |CGC_PEX0 ,CLOCK_GATING_CTRL ); + flags = curr |CGC_SATA0 |CGC_SATA1 |CGC_PEX0 ; + +if (dev ==MV88F6282_DEV_ID ) + flags |=CGC_PEX1 ; +writel (flags,CLOCK_GATING_CTRL );/* For SATA: first shutdown the phy */ if (!(kirkwood_clk_ctrl &CGC_SATA0 )) {
@@ -978,7 +991,7 @@ static int __init kirkwood_clock_gate(void)writel (readl (SATA1_IF_CTRL ) |0x200 ,SATA1_IF_CTRL ); } -/* For PCIe: first shutdown the phy */ +/* For PCIe #0: first shutdown the phy */ if (!(kirkwood_clk_ctrl &CGC_PEX0 )) {writel (readl (PCIE_LINK_CTRL ) |0x10 ,PCIE_LINK_CTRL );while (1 )
@@ -987,6 +1000,17 @@ static int __init kirkwood_clock_gate(void)writel (readl (PCIE_LINK_CTRL ) & ~0x10 ,PCIE_LINK_CTRL ); } +/* For PCIe #1: first shutdown the phy */ +if (dev ==MV88F6282_DEV_ID ) { +if (!(kirkwood_clk_ctrl &CGC_PEX1 )) { +writel (readl (PCIE1_LINK_CTRL ) |0x10 ,PCIE1_LINK_CTRL ); +while (1 ) +if (readl (PCIE1_STATUS ) &0x1 ) +break ; +writel (readl (PCIE1_LINK_CTRL ) & ~0x10 ,PCIE1_LINK_CTRL ); + } + } +/* Now gate clock the required units */ writel (kirkwood_clk_ctrl,CLOCK_GATING_CTRL );printk (KERN_DEBUG " after: 0x%08x\n" ,readl (CLOCK_GATING_CTRL ));
arch/arm/mach-kirkwood/common.h +4 -1
@@ -18,6 +18,9 @@ struct mvsdio_platform_data;struct mtd_partition ;struct mtd_info ; +#define KW_PCIE0 (1 << 0) +#define KW_PCIE1 (1 << 1) +/* * Basic Kirkwood init functions used early by machine-setup. */
@@ -34,7 +37,7 @@ void kirkwood_ehci_init(void);void kirkwood_ge00_init (struct mv643xx_eth_platform_data *eth_data);void kirkwood_ge01_init (struct mv643xx_eth_platform_data *eth_data);void kirkwood_ge00_switch_init (struct dsa_platform_data *d,int irq); -void kirkwood_pcie_init (void ); +void kirkwood_pcie_init (unsigned int portmask);void kirkwood_sata_init (struct mv_sata_platform_data *sata_data);void kirkwood_sdio_init (struct mvsdio_platform_data *mvsdio_data);void kirkwood_spi_init (void );
arch/arm/mach-kirkwood/db88f6281-bp-setup.c +1 -1
@@ -75,7 +75,7 @@ static void __init db88f6281_init(void)static int __init db88f6281_pci_init (void ) {if (machine_is_db88f6281_bp ()) -kirkwood_pcie_init (); +kirkwood_pcie_init (KW_PCIE0 );return 0 ; }
arch/arm/mach-kirkwood/include/mach/bridge-regs.h +2 -1
@@ -59,8 +59,9 @@#define CGC_SATA1 (1 << 15)#define CGC_XOR1 (1 << 16)#define CGC_CRYPTO (1 << 17) +#define CGC_PEX1 (1 << 18)#define CGC_GE1 (1 << 19)#define CGC_TDM (1 << 20) -#define CGC_RESERVED ((1 << 18) | (0x6 << 21)) +#define CGC_RESERVED (0x6 << 21)#endif
arch/arm/mach-kirkwood/include/mach/irqs.h +1 -0
@@ -23,6 +23,7 @@#define IRQ_KIRKWOOD_XOR_10 7#define IRQ_KIRKWOOD_XOR_11 8#define IRQ_KIRKWOOD_PCIE 9 +#define IRQ_KIRKWOOD_PCIE1 10#define IRQ_KIRKWOOD_GE00_SUM 11#define IRQ_KIRKWOOD_GE01_SUM 15#define IRQ_KIRKWOOD_USB 19
arch/arm/mach-kirkwood/include/mach/kirkwood.h +25 -10
@@ -16,36 +16,48 @@* Marvell Kirkwood address maps. * * phys -* e0000000 PCIe Memory space +* e0000000 PCIe #0 Memory space +* e8000000 PCIe #1 Memory space * f1000000 on-chip peripheral registers -* f2000000 PCIe I/O space -* f3000000 NAND controller address window -* f4000000 Security Accelerator SRAM +* f2000000 PCIe #0 I/O space +* f3000000 PCIe #1 I/O space +* f4000000 NAND controller address window +* f5000000 Security Accelerator SRAM * * virt phys size -* fee00000 f1000000 1M on-chip peripheral registers -* fef00000 f2000000 1M PCIe I/O space +* fed00000 f1000000 1M on-chip peripheral registers +* fee00000 f2000000 1M PCIe #0 I/O space +* fef00000 f3000000 1M PCIe #1 I/O space */ -#define KIRKWOOD_SRAM_PHYS_BASE 0xf4000000 +#define KIRKWOOD_SRAM_PHYS_BASE 0xf5000000#define KIRKWOOD_SRAM_SIZE SZ_2K -#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf3000000 +#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf4000000#define KIRKWOOD_NAND_MEM_SIZE SZ_1K +#define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000 +#define KIRKWOOD_PCIE1_IO_VIRT_BASE 0xfef00000 +#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00000000 +#define KIRKWOOD_PCIE1_IO_SIZE SZ_1M +#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000 -#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfef00000 +#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfee00000#define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000#define KIRKWOOD_PCIE_IO_SIZE SZ_1M#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000 -#define KIRKWOOD_REGS_VIRT_BASE 0xfee00000 +#define KIRKWOOD_REGS_VIRT_BASE 0xfed00000#define KIRKWOOD_REGS_SIZE SZ_1M#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000#define KIRKWOOD_PCIE_MEM_BUS_BASE 0xe0000000#define KIRKWOOD_PCIE_MEM_SIZE SZ_128M +#define KIRKWOOD_PCIE1_MEM_PHYS_BASE 0xe8000000 +#define KIRKWOOD_PCIE1_MEM_BUS_BASE 0xe8000000 +#define KIRKWOOD_PCIE1_MEM_SIZE SZ_128M +/* * Register Map */
@@ -72,6 +84,9 @@#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000)#define PCIE_LINK_CTRL (PCIE_VIRT_BASE | 0x70)#define PCIE_STATUS (PCIE_VIRT_BASE | 0x1a04) +#define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x44000) +#define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE | 0x70) +#define PCIE1_STATUS (PCIE1_VIRT_BASE | 0x1a04)#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c +1 -1
@@ -155,7 +155,7 @@ static void __init mv88f6281gtw_ge_init(void)static int __init mv88f6281gtw_ge_pci_init (void ) {if (machine_is_mv88f6281gtw_ge ()) -kirkwood_pcie_init (); +kirkwood_pcie_init (KW_PCIE0 );return 0 ; }
arch/arm/mach-kirkwood/openrd-setup.c +1 -1
@@ -85,7 +85,7 @@ static void __init openrd_init(void)static int __init openrd_pci_init (void ) {if (machine_is_openrd_base () ||machine_is_openrd_client ()) -kirkwood_pcie_init (); +kirkwood_pcie_init (KW_PCIE0 );return 0 ; }
arch/arm/mach-kirkwood/pcie.c +155 -49
296 lines not on this page · raw message
arch/arm/mach-kirkwood/rd88f6192-nas-setup.c +1 -1
@@ -71,7 +71,7 @@ static void __init rd88f6192_init(void)static int __init rd88f6192_pci_init (void ) {if (machine_is_rd88f6192_nas ()) -kirkwood_pcie_init (); +kirkwood_pcie_init (KW_PCIE0 );return 0 ; }
arch/arm/mach-kirkwood/rd88f6281-setup.c +1 -1
@@ -107,7 +107,7 @@ static void __init rd88f6281_init(void)static int __init rd88f6281_pci_init (void ) {if (machine_is_rd88f6281 ()) -kirkwood_pcie_init (); +kirkwood_pcie_init (KW_PCIE0 );return 0 ; }
arch/arm/mach-kirkwood/ts219-setup.c +1 -1
@@ -111,7 +111,7 @@ static void __init qnap_ts219_init(void)static int __init ts219_pci_init (void ) {if (machine_is_ts219 ()) -kirkwood_pcie_init (); +kirkwood_pcie_init (KW_PCIE0 );return 0 ; }
arch/arm/mach-kirkwood/ts41x-setup.c +1 -1
@@ -136,7 +136,7 @@ static void __init qnap_ts41x_init(void)static int __init ts41x_pci_init (void ) {if (machine_is_ts41x ()) -kirkwood_pcie_init (); +kirkwood_pcie_init (KW_PCIE0 );return 0 ; }
PATCH 4/4 arch/arm/mach-kirkwood: add support for 2nd TWSI controller on 88f6282.
In reply to Benjamin ZoresSigned-off-by Benjamin Zores <[email protected]>
--- arch/arm/mach-kirkwood/common.c | 52 +++++++++++++++++++----- arch/arm/mach-kirkwood/common.h | 5 ++ arch/arm/mach-kirkwood/include/mach/irqs.h | 3 + arch/arm/mach-kirkwood/include/mach/kirkwood.h | 3 + arch/arm/mach-kirkwood/netspace_v2-setup.c | 2 - arch/arm/mach-kirkwood/netxbig_v2-setup.c | 2 - arch/arm/mach-kirkwood/openrd-setup.c | 2 - arch/arm/mach-kirkwood/ts219-setup.c | 2 - arch/arm/mach-kirkwood/ts41x-setup.c | 2 - 9 files changed, 55 insertions(+), 18 deletions(-)
arch/arm/mach-kirkwood/common.c +42 -10
@@ -458,31 +458,63 @@ static struct mv64xxx_i2c_pdata kirkwood_i2c_pdata = { .timeout = 1000, /* Default timeout of 1 second */ }; -static struct resource kirkwood_i2c_resources[] = { +static struct resource kirkwood_i2c_0_resources[] = { { - .start =I2C_PHYS_BASE , - .end =I2C_PHYS_BASE +0x1f , + .start =I2C_0_PHYS_BASE , + .end =I2C_0_PHYS_BASE +0x1f , .flags =IORESOURCE_MEM , }, { - .start =IRQ_KIRKWOOD_TWSI , - .end =IRQ_KIRKWOOD_TWSI , + .start =IRQ_KIRKWOOD_TWSI0 , + .end =IRQ_KIRKWOOD_TWSI0 , .flags =IORESOURCE_IRQ , }, }; -static struct platform_device kirkwood_i2c = { +static struct resource kirkwood_i2c_1_resources[] = { + { + .start =I2C_1_PHYS_BASE , + .end =I2C_1_PHYS_BASE +0x1f , + .flags =IORESOURCE_MEM , + }, { + .start =IRQ_KIRKWOOD_TWSI1 , + .end =IRQ_KIRKWOOD_TWSI1 , + .flags =IORESOURCE_IRQ , + }, +}; + +static struct platform_device kirkwood_i2c_0 = { + .name =MV64XXX_I2C_CTLR_NAME , + .id =0 , + .num_resources =ARRAY_SIZE (kirkwood_i2c_0_resources), + .resource = kirkwood_i2c_0_resources, + .dev = { + .platform_data = &kirkwood_i2c_pdata, + }, +}; + +static struct platform_device kirkwood_i2c_1 = { .name =MV64XXX_I2C_CTLR_NAME , .id =0 , - .num_resources =ARRAY_SIZE (kirkwood_i2c_resources), - .resource = kirkwood_i2c_resources, + .num_resources =ARRAY_SIZE (kirkwood_i2c_1_resources), + .resource = kirkwood_i2c_1_resources, .dev = { .platform_data = &kirkwood_i2c_pdata, }, }; -void __init kirkwood_i2c_init (void ) +void __init kirkwood_i2c_init (unsigned int mask) { -platform_device_register (&kirkwood_i2c); +if (mask &KW_TWSI0 ) +platform_device_register (&kirkwood_i2c_0); + +if (mask &KW_TWSI1 ) { +u32 dev, rev; + +kirkwood_pcie_id (&dev, &rev); + +if (dev ==MV88F6282_DEV_ID && (rev ==MV88F6282_REV_A0 )) +platform_device_register (&kirkwood_i2c_1); + } }
arch/arm/mach-kirkwood/common.h +4 -1
@@ -21,6 +21,9 @@ struct mtd_info;#define KW_PCIE0 (1 << 0)#define KW_PCIE1 (1 << 1) +#define KW_TWSI0 (1 << 0) +#define KW_TWSI1 (1 << 1) +/* * Basic Kirkwood init functions used early by machine-setup. */
@@ -41,7 +44,7 @@ void kirkwood_pcie_init(unsigned int portmask);void kirkwood_sata_init (struct mv_sata_platform_data *sata_data);void kirkwood_sdio_init (struct mvsdio_platform_data *mvsdio_data);void kirkwood_spi_init (void ); -void kirkwood_i2c_init (void ); +void kirkwood_i2c_init (unsigned int mask);void kirkwood_uart0_init (void );void kirkwood_uart1_init (void );void kirkwood_nand_init (struct mtd_partition *parts,int nr_parts,int delay);
arch/arm/mach-kirkwood/include/mach/irqs.h +2 -1
@@ -33,13 +33,14 @@#define IRQ_KIRKWOOD_I2S 24#define IRQ_KIRKWOOD_TS_0 26#define IRQ_KIRKWOOD_SDIO 28 -#define IRQ_KIRKWOOD_TWSI 29 +#define IRQ_KIRKWOOD_TWSI0 29#define IRQ_KIRKWOOD_AVB 30#define IRQ_KIRKWOOD_TDMI 31/* * High Interrupt Controller */ +#define IRQ_KIRKWOOD_TWSI1 32#define IRQ_KIRKWOOD_UART_0 33#define IRQ_KIRKWOOD_UART_1 34#define IRQ_KIRKWOOD_GPIO_LOW_0_7 35
arch/arm/mach-kirkwood/include/mach/kirkwood.h +2 -1
@@ -71,7 +71,8 @@#define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034)#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300)#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600) -#define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000) +#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000) +#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1100)#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
arch/arm/mach-kirkwood/netspace_v2-setup.c +1 -1
@@ -295,7 +295,7 @@ static void __init netspace_v2_init(void)spi_register_board_info (netspace_v2_spi_slave_info,ARRAY_SIZE (netspace_v2_spi_slave_info));kirkwood_spi_init (); -kirkwood_i2c_init (); +kirkwood_i2c_init (KW_TWSI0 );i2c_register_board_info (0 , netspace_v2_i2c_info,ARRAY_SIZE (netspace_v2_i2c_info));
arch/arm/mach-kirkwood/netxbig_v2-setup.c +1 -1
@@ -377,7 +377,7 @@ static void __init netxbig_v2_init(void)spi_register_board_info (netxbig_v2_spi_slave_info,ARRAY_SIZE (netxbig_v2_spi_slave_info));kirkwood_spi_init (); -kirkwood_i2c_init (); +kirkwood_i2c_init (KW_TWSI0 );i2c_register_board_info (0 , netxbig_v2_i2c_info,ARRAY_SIZE (netxbig_v2_i2c_info));
arch/arm/mach-kirkwood/openrd-setup.c +1 -1
@@ -79,7 +79,7 @@ static void __init openrd_init(void)kirkwood_sata_init (&openrd_sata_data);kirkwood_sdio_init (&openrd_mvsdio_data); -kirkwood_i2c_init (); +kirkwood_i2c_init (KW_TWSI0 ); }static int __init openrd_pci_init (void )
arch/arm/mach-kirkwood/ts219-setup.c +1 -1
@@ -97,7 +97,7 @@ static void __init qnap_ts219_init(void)kirkwood_uart0_init ();kirkwood_uart1_init ();/* A PIC controller is connected here. */ qnap_tsx1x_register_flash (); -kirkwood_i2c_init (); +kirkwood_i2c_init (KW_TWSI0 );i2c_register_board_info (0 , &qnap_ts219_i2c_rtc,1 );kirkwood_ge00_init (&qnap_ts219_ge00_data);kirkwood_sata_init (&qnap_ts219_sata_data);
arch/arm/mach-kirkwood/ts41x-setup.c +1 -1
@@ -121,7 +121,7 @@ static void __init qnap_ts41x_init(void)kirkwood_uart0_init ();kirkwood_uart1_init ();/* A PIC controller is connected here. */ qnap_tsx1x_register_flash (); -kirkwood_i2c_init (); +kirkwood_i2c_init (KW_TWSI0 );i2c_register_board_info (0 , &qnap_ts41x_i2c_rtc,1 );kirkwood_ge00_init (&qnap_ts41x_ge00_data);kirkwood_ge01_init (&qnap_ts41x_ge01_data);