Support for MPC8308ERDB board

This patch adds basic support for Freescale MPC8308 CPU. Serial ports, NOR flash and integrated Ethernet controllers are supported. PCI Express is also supported. eSDHC, NAND and USB may work but aren't tested (using ULPI PHY requires additional patch).

Signed-off-by Ilya Yanok <[email protected]>

Quoted 7 lines

This patch adds basic support for Freescale MPC8308 CPU. Serial ports, NOR flash and integrated Ethernet controllers are supported. PCI Express is also supported. eSDHC, NAND and USB may work but aren't tested (using ULPI PHY requires additional patch).

Signed-off-by Ilya Yanok<[email protected]>

...

arch/powerpc/cpu/mpc83xx/speed.c int get_clocks(void) · line 206

Quoted 4 lines

arch/powerpc/cpu/mpc83xx/speed.c +2 -1

-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) || \
+	defined(CONFIG_MPC8315) || defined(CONFIG_MPC8308)

Please sort this list.

include/mpc83xx.h line 761

Quoted 9 lines

include/mpc83xx.h +8 -0

+#if defined(CONFIG_MPC8308)
+#define SCCR_SDHCCM			0x0c000000
+#define SCCR_SDHCCM_SHIFT		26
+#define SCCR_SDHCCM_0			0x00000000
+#define SCCR_SDHCCM_1			0x04000000
+#define SCCR_SDHCCM_2			0x08000000
+#define SCCR_SDHCCM_3			0x0c000000
+#endif

Would it make sense to write this as:

And: why do we need the #ifdef? Unused defines should not hurt?

	#define SCCR_SDHCCM_MASK	0x0c000000	/* is it a mask? */
	#define SCCR_SDHCCM_SHIFT	26
	#define SCCR_SDHCCM(arg)	((arg)<<SCCR_SDHCCM_SHIFT)

Quoted 4 lines

+#if defined(CONFIG_MPC8315)
#define SCCR_SATA1CM 0x00003000
#define SCCR_SATA1CM_SHIFT 12
#define SCCR_SATACM 0x00003c00

include/mpc83xx.h line 780

Quoted 6 lines

include/mpc83xx.h +1 -0

@@ -765,6 +776,7 @@
  #define SCCR_SATACM_1			0x00001400
  #define SCCR_SATACM_2			0x00002800
  #define SCCR_SATACM_3			0x00003c00
+#endif
 

Do we need that #ifdef? Ok, the #defines don't apply to the 8308, but do they hurt if they are just there, unused?

Quoted 3 lines

Do we need that #ifdef? Ok, the #defines don't apply to the 8308, but do they hurt if they are just there, unused?

Well, it seems to be safer not to have unused defines so that you can't erroneously use some define not applicable for current CPU, but if you wish I'll remove these ifdefs.

This patch adds basic support for Freescale MPC8308 CPU. Serial ports, NOR flash and integrated Ethernet controllers are supported. PCI Express is also supported. eSDHC, NAND and USB may work but aren't tested (using ULPI PHY requires additional patch).

Signed-off-by Ilya Yanok <[email protected]>

---

This patch provides support for MPC8308ERDB development board from Freescale with a minimal set of features:
Dual UART is supported
NOR flash is supported
Both TSEC Ethernet controllers are supported
PCI Express initialization is supported

The following features are enabled in configuration but not fully tested:
I2C (used to get the board revision)
I2C-connected RTC
VSC7385 switch

 MAKEALL                                   |    1 +
 Makefile                                  |    3 +
 board/freescale/mpc8308erdb/Makefile      |   52 +++
 board/freescale/mpc8308erdb/config.mk     |    1 +
 board/freescale/mpc8308erdb/mpc8308erdb.c |  154 ++++++++

 board/freescale/mpc8308erdb/sdram.c       |  126 +++++++
 include/configs/MPC8308ERDB.h             |  572 +++++++++++++++++++++++++++++
 7 files changed, 909 insertions(+), 0 deletions(-)
 create mode 100644 board/freescale/mpc8308erdb/Makefile
 create mode 100644 board/freescale/mpc8308erdb/config.mk
 create mode 100644 board/freescale/mpc8308erdb/mpc8308erdb.c
 create mode 100644 board/freescale/mpc8308erdb/sdram.c
 create mode 100644 include/configs/MPC8308ERDB.h

board/freescale/mpc8308erdb/mpc8308erdb.c new file +43 -0

+/* Fixed sdram init -- doesn't use serial presence detect.
+ *
+ * This is useful for faster booting in configs where the RAM is unlikely
+ * to be changed, or for things like NAND booting where space is tight.
+ */
+static long fixed_sdram(void)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+	u32 msize_log2 = __ilog2(msize);
+
+	out_be32(&im->sysconf.ddrlaw[0].bar,
+			CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000);
+	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
+	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+
+	/*
+	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
+	 * or the DDR2 controller may fail to initialize correctly.
+	 */
+	udelay(50000);
+
+	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
+	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
+
+	/* Currently we use only one CS, so disable the other bank. */
+	out_be32(&im->ddr.cs_config[1], 0);
+
+	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
+	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+	if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF) {
+		out_be32(&im->ddr.sdram_cfg,
+			CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI);
+	} else {
+		out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
+	}
+
+	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
+	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);

board/freescale/mpc8308erdb/mpc8308erdb.c new file +19 -0

+}
+
+phys_size_t initdram(int board_type)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize;
+
+	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM */
+	msize = fixed_sdram();
+
+	if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF)
+		resume_from_sleep();
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return msize;
+}

include/configs/MPC8308ERDB.h new file +74 -0

new file mode 100644
index 0000000..5b7f508
@@ -0,0 +1,572 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok at emcraft.com
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1 /* E300 family */
+#define CONFIG_MPC83xx		1 /* MPC83xx family */
+#define CONFIG_MPC831x		1 /* MPC831x CPU family */
+#define CONFIG_MPC8308		1 /* MPC8308 CPU specific */
+#define CONFIG_MPC8308ERDB	1 /* MPC8308ERDB board specific */
+
+#define CONFIG_MISC_INIT_R
+
+/*
+ * On-board devices
+ *
+ * TSEC1 is SoC TSEC
+ * TSEC2 is VSC switch
+ */
+#define CONFIG_TSEC1
+#define CONFIG_VSC7385_ENET
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN	33333333 /* in Hz */
+#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
+
+/*
+ * Hardware Reset Configuration Word
+ * if CLKIN is 66.66MHz, then
+ * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
+ * We choose the A type silicon as default, so the core is 400Mhz.
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_2X1 |\
+	HRCWL_SVCOD_DIV_2 |\
+	HRCWL_CSB_TO_CLKIN_4X1 |\
+	HRCWL_CORE_TO_CSB_3X1)
+/*
+ * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
+ * in 8308's HRCWH according to the manual, but original Freescale's
+ * code has them and I've expirienced some problems using the board
+ * with BDI3000 attached when I've tried to set these bits to zero
+ * (UART doesn't work after the 'reset run' command).
+ */
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\

Quoted 8 lines

  MAKEALL                                   |    1 +
  Makefile                                  |    3 +
  board/freescale/mpc8308erdb/Makefile      |   52 +++
  board/freescale/mpc8308erdb/config.mk     |    1 +
  board/freescale/mpc8308erdb/mpc8308erdb.c |  154 ++++++++
  board/freescale/mpc8308erdb/sdram.c       |  126 +++++++
  include/configs/MPC8308ERDB.h             |  572 +++++++++++++++++++++++++++++
  7 files changed, 909 insertions(+), 0 deletions(-)

Quoted 6 lines

create mode 100644 board/freescale/mpc8308erdb/Makefile create mode 100644 board/freescale/mpc8308erdb/config.mk create mode 100644 board/freescale/mpc8308erdb/mpc8308erdb.c create mode 100644 board/freescale/mpc8308erdb/sdram.c create mode 100644 include/configs/MPC8308ERDB.h

Entry to MAINTAINERS missing.

Quoted 8 lines

Makefile +0 -0

index 55bb964..0dc2678 100644
@@ -2233,6 +2233,9 @@ TASREG_config :		unconfig
  kmeter1_config: unconfig
  	@$(MKCONFIG) kmeter1 powerpc mpc83xx kmeter1 keymile
 

Makefile TASREG_config : unconfig

Quoted 3 lines

Makefile +2 -0

+MPC8308ERDB_config: unconfig
+	@$(MKCONFIG) -a MPC8308ERDB powerpc mpc83xx mpc8308erdb freescale
 

NAK. Please rebase your code against the "next" branch. We don't accept any board entries to the top level Makefile any more. Please add to boards.cfg instead.

board/freescale/mpc8308erdb/mpc8308erdb.c line 5

Quoted 9 lines

board/freescale/mpc8308erdb/mpc8308erdb.c new file +5 -0

@@ -0,0 +1,154 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok at emcraft.com
+ *
+ * Author: Freescale unknown

Maybe "Initial author" ?

board/freescale/mpc8308erdb/mpc8308erdb.c line 46

Quoted 7 lines

board/freescale/mpc8308erdb/mpc8308erdb.c new file +6 -0

+int board_early_init_f(void)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	if (in_be32(&im->pmc.pmccr1)&  PMCCR1_POWER_OFF)
+		gd->flags |= GD_FLG_SILENT;

What exactly is this good for?

board/freescale/mpc8308erdb/mpc8308erdb.c line 128

Quoted 9 lines

board/freescale/mpc8308erdb/mpc8308erdb.c new file +8 -0

+/*
+ * Miscellaneous late-boot configurations
+ *
+ * If a VSC7385 microcode image is present, then upload it.
+*/
+int misc_init_r(void)
+{
+	int rc = 0;

Please drop the variable.

board/freescale/mpc8308erdb/mpc8308erdb.c line 134

Quoted 6 lines

board/freescale/mpc8308erdb/mpc8308erdb.c new file +5 -0

+#ifdef CONFIG_VSC7385_IMAGE
+	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
+		CONFIG_VSC7385_IMAGE_SIZE)) {
+		puts("Failure uploading VSC7385 microcode.\n");
+		rc = 1;

	return 1;

board/freescale/mpc8308erdb/mpc8308erdb.c line 138

Quoted 5 lines

board/freescale/mpc8308erdb/mpc8308erdb.c new file +4 -0

+	}
+#endif
+
+	return rc;

	return 0;

board/freescale/mpc8308erdb/mpc8308erdb.c line 150

Quoted 4 lines

board/freescale/mpc8308erdb/mpc8308erdb.c new file +3 -0

+int board_eth_init(bd_t *bis)
+{
+	cpu_eth_init(bis);	/* Initialize TSECs first */

I think it's wrong to ignore the return code here.

board/freescale/mpc8308erdb/mpc8308erdb.c line 154

Quoted 5 lines

board/freescale/mpc8308erdb/mpc8308erdb.c new file +4 -0

+	return pci_eth_init(bis);
+}
+
+

Please remove trailing empty lines.

Quoted 47 lines

board/freescale/mpc8308erdb/mpc8308erdb.c new file +47 -0

+/* Fixed sdram init -- doesn't use serial presence detect.
+ *
+ * This is useful for faster booting in configs where the RAM is unlikely
+ * to be changed, or for things like NAND booting where space is tight.
+ */
+static long fixed_sdram(void)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+	u32 msize_log2 = __ilog2(msize);
+
+	out_be32(&im->sysconf.ddrlaw[0].bar,
+			CONFIG_SYS_DDR_SDRAM_BASE&  0xfffff000);
+	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
+	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+
+	/*
+	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
+	 * or the DDR2 controller may fail to initialize correctly.
+	 */
+	udelay(50000);
+
+	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1)>>  24);
+	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
+
+	/* Currently we use only one CS, so disable the other bank. */
+	out_be32(&im->ddr.cs_config[1], 0);
+
+	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
+	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+	if (in_be32(&im->pmc.pmccr1)&  PMCCR1_POWER_OFF) {
+		out_be32(&im->ddr.sdram_cfg,
+			CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI);
+	} else {
+		out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
+	}
+
+	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
+	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
+
+	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	sync();

board/freescale/mpc8308erdb/mpc8308erdb.c line 88

Quoted 7 lines

board/freescale/mpc8308erdb/mpc8308erdb.c new file +6 -0

+
+	/* enable DDR controller */
+	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+	sync();
+
+	return msize;

Please test RAM and verify the size using get_mem_size().

Quoted 23 lines

board/freescale/mpc8308erdb/mpc8308erdb.c new file +22 -0

+
+/*
+ * Hardware Reset Configuration Word
+ * if CLKIN is 66.66MHz, then
+ * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
+ * We choose the A type silicon as default, so the core is 400Mhz.
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_2X1 |\
+	HRCWL_SVCOD_DIV_2 |\
+	HRCWL_CSB_TO_CLKIN_4X1 |\
+	HRCWL_CORE_TO_CSB_3X1)
+/*
+ * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
+ * in 8308's HRCWH according to the manual, but original Freescale's
+ * code has them and I've expirienced some problems using the board
+ * with BDI3000 attached when I've tried to set these bits to zero
+ * (UART doesn't work after the 'reset run' command).
+ */
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\

board/freescale/mpc8308erdb/mpc8308erdb.c line 120

Quoted 10 lines

board/freescale/mpc8308erdb/mpc8308erdb.c new file +10 -0

+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_RL_EXT_LEGACY |\
+	HRCWH_TSEC1M_IN_RGMII |\
+	HRCWH_TSEC2M_IN_RGMII |\
+	HRCWH_BIG_ENDIAN)

Kim, can you please comment?

board/freescale/mpc8308erdb/mpc8308erdb.c line 129

Quoted 10 lines

board/freescale/mpc8308erdb/mpc8308erdb.c new file +9 -0

+#include<config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PCI

Please sort list.

Quoted 2 lines

Entry to MAINTAINERS missing.

Should I add you as a maintainer or myself?

Quoted 5 lines

board/freescale/mpc8308erdb/mpc8308erdb.c line 150

Quoted 4 lines

board/freescale/mpc8308erdb/mpc8308erdb.c new file +3 -0

+int board_eth_init(bd_t *bis)
+{
+	cpu_eth_init(bis);	/* Initialize TSECs first */

I think it's wrong to ignore the return code here.

What makes you think so? What can we do with the return code here? Print warning? If we return error from board_eth_init() calling code will call cpu_eth_init() again which is useless as we have already called it.

Quoted 1 line

board/freescale/mpc8308erdb/mpc8308erdb.c line 151

Quoted 1 line

board/freescale/mpc8308erdb/mpc8308erdb.c new file +1 -0

+	return pci_eth_init(bis);

Dear Ilya Yanok,

Quoted 5 lines · In message<[email protected]> you wrote:

Quoted 3 lines

Entry to MAINTAINERS missing.

Should I add you as a maintainer or myself?

You did the actual work...

Quoted 11 lines

Quoted 7 lines

board/freescale/mpc8308erdb/mpc8308erdb.c line 150

Quoted 5 lines

board/freescale/mpc8308erdb/mpc8308erdb.c new file +3 -0

+int board_eth_init(bd_t *bis)
+{
+	cpu_eth_init(bis);	/* Initialize TSECs first */

I think it's wrong to ignore the return code here.

What makes you think so? What can we do with the return code here? Print warning? If we return error from board_eth_init() calling code will call cpu_eth_init() again which is useless as we have already called it.

Quoted 2 lines

Quoted 2 lines

board/freescale/mpc8308erdb/mpc8308erdb.c line 151

Quoted 2 lines

board/freescale/mpc8308erdb/mpc8308erdb.c new file +1 -0

+	return pci_eth_init(bis);

My understanding is that pci_eth_init() and board_eth_init() return the number of NIC's found - should that number not include the number of successfully initialized TSECs?

Best regards,

Wolfgang Denk

Quoted 10 lines

Quoted 10 lines

Quoted 5 lines

board/freescale/mpc8308erdb/mpc8308erdb.c line 150

Quoted 4 lines

board/freescale/mpc8308erdb/mpc8308erdb.c new file +3 -0

+int board_eth_init(bd_t *bis)
+{
+    cpu_eth_init(bis);    /* Initialize TSECs first */

I think it's wrong to ignore the return code here.

What makes you think so? What can we do with the return code here? Print
warning? If we return error from board_eth_init() calling code will call
cpu_eth_init() again which is useless as we have already called it.

Yes, print a warning if < 0. As you've noticed, returning -1 wouldn't be good. I'm not aware of a U-boot policy for handling hardware problems other than printf.

Quoted 5 lines

Quoted 1 line

Quoted 1 line

Quoted 1 line

+ return pci_eth_init(bis);

My understanding is that pci_eth_init() and board_eth_init() return the number of NIC's found - should that number not include the number of successfully initialized TSECs?

Yes, please. Something like:

int board_eth_init(bd_t *bis)

{
    int rc, num_if = 0;
    if ((rc = cpu_eth_init(bis)) >= 0)
    {
        num_if += rc;
    } else {
        print error message
    }
    if ((rc = pci_eth_init(bis)) >= 0)
    {
        num_if += rc;
    } else {
        print error message
    }
    return num_if;
}

I'm working on changing net/eth.c to be less kludgy, but am having a hard time setting up my test bed. Hopefully in the next few days.

Quoted 4 lines

Quoted 2 lines

Entry to MAINTAINERS missing.

Should I add you as a maintainer or myself?

You did the actual work...

Quoted 2 lines

board/freescale/mpc8308erdb/mpc8308erdb.c line 151

Quoted 2 lines

board/freescale/mpc8308erdb/mpc8308erdb.c new file +1 -0

+	return pci_eth_init(bis);

My understanding is that pci_eth_init() and board_eth_init() return the number of NIC's found - should that number not include the number of successfully initialized TSECs?

This patch provides support for MPC8308ERDB development board from Freescale with a minimal set of features:
Dual UART is supported
NOR flash is supported
Both TSEC Ethernet controllers are supported
PCI Express initialization is supported

The following features are enabled in configuration but not fully tested:
I2C (used to get the board revision)
I2C-connected RTC
VSC7385 switch

Signed-off-by Ilya Yanok <[email protected]>

---

 MAKEALL                                   |    1 +
 Makefile                                  |    3 +
 board/freescale/mpc8308erdb/Makefile      |   52 +++
 board/freescale/mpc8308erdb/config.mk     |    1 +
 board/freescale/mpc8308erdb/mpc8308erdb.c |  154 ++++++++

 board/freescale/mpc8308erdb/sdram.c       |  126 +++++++
 include/configs/MPC8308ERDB.h             |  572 +++++++++++++++++++++++++++++
 7 files changed, 909 insertions(+), 0 deletions(-)
 create mode 100644 board/freescale/mpc8308erdb/Makefile
 create mode 100644 board/freescale/mpc8308erdb/config.mk
 create mode 100644 board/freescale/mpc8308erdb/mpc8308erdb.c
 create mode 100644 board/freescale/mpc8308erdb/sdram.c
 create mode 100644 include/configs/MPC8308ERDB.h

+#define CONFIG_MPC831x 1 /* MPC831x CPU family */

+/*
+ * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
+ * in 8308's HRCWH according to the manual, but original Freescale's
+ * code has them and I've expirienced some problems using the board
+ * with BDI3000 attached when I've tried to set these bits to zero
+ * (UART doesn't work after the 'reset run' command).

Quoted 8 lines

  MAKEALL                                   |    1 +
  Makefile                                  |    3 +
  board/freescale/mpc8308erdb/Makefile      |   52 +++
  board/freescale/mpc8308erdb/config.mk     |    1 +
  board/freescale/mpc8308erdb/mpc8308erdb.c |  154 ++++++++
  board/freescale/mpc8308erdb/sdram.c       |  126 +++++++
  include/configs/MPC8308ERDB.h             |  572 +++++++++++++++++++++++++++++
  7 files changed, 909 insertions(+), 0 deletions(-)

Quoted 6 lines

create mode 100644 board/freescale/mpc8308erdb/Makefile create mode 100644 board/freescale/mpc8308erdb/config.mk create mode 100644 board/freescale/mpc8308erdb/mpc8308erdb.c create mode 100644 board/freescale/mpc8308erdb/sdram.c create mode 100644 include/configs/MPC8308ERDB.h

missing a doc/README.mpc8308erdb file.

Makefile TASREG_config : unconfig · line 2238

Quoted 5 lines

Makefile +3 -0

+MPC8308ERDB_config: unconfig
+	@$(MKCONFIG) -a MPC8308ERDB powerpc mpc83xx mpc8308erdb freescale
+

patch doesn't apply to WD's next branch:

---
Applying: MPC8308ERDB: minimal support for devboard from Freescale
error: patch failed: Makefile:2233
error: Makefile: patch does not apply /home/r1aaha/git/u-boot/.git/rebase-apply/patch:112: new blank line at EOF. +
Patch failed at 0002 MPC8308ERDB: minimal support for devboard from Freescale When you have resolved this problem run "git am --resolved".
If you would prefer to skip this patch, instead run "git am --skip". To restore the original branch and stop patching run "git am --abort".
---

please rebase on top of Wolfgang's next branch, and also fix the new blank line at EOF.

Quoted 2 lines

+#define CONFIG_MPC831x 1 /* MPC831x CPU family */

I don't see the 8308 being a member of the 831x family; e.g., upper spridr bits are 0x810, which don't match those of 831x: 0x80B. Please introduce a new CONFIG_MPC830x.

Quoted 7 lines

+/*
+ * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
+ * in 8308's HRCWH according to the manual, but original Freescale's
+ * code has them and I've expirienced some problems using the board
+ * with BDI3000 attached when I've tried to set these bits to zero
+ * (UART doesn't work after the 'reset run' command).

is the BDI overriding the RCW in this case? it's not clear..

include/configs/MPC8308ERDB.h line 90

Quoted 3 lines

include/configs/MPC8308ERDB.h new file +2 -0

+#define CFG_SICRH		0x01001003
+#define CFG_SICRL		0x00000040 /* 3.3V, no delay */

the CFG_ prefix is no longer - are these even being used anywhere?

include/configs/MPC8308ERDB.h line 442

Quoted 3 lines

include/configs/MPC8308ERDB.h new file +2 -0

+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
+				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)

| HID0_ENABLE_INSTRUCTION_CACHE?

Quoted 2 lines

missing a doc/README.mpc8308erdb file.

Hm.. Wolfgang, do we really need this?

include/configs/MPC8308ERDB.h line 442

Quoted 3 lines

include/configs/MPC8308ERDB.h new file +2 -0

+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
+				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)

| HID0_ENABLE_INSTRUCTION_CACHE?

Quoted 4 lines · Kim Phillips

include/configs/MPC8308ERDB.h line 442

Quoted 3 lines

include/configs/MPC8308ERDB.h new file +2 -0

+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
+				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)

| HID0_ENABLE_INSTRUCTION_CACHE?

I've enabled icache and now the board sometimes resets twice after U-Boot 'reset' command:

(It doesn't always stop at "DRAM:" line but that position is most frequent) Maybe you have some ideas on this subject?

Quoted 7 lines

I've enabled icache and now the board sometimes resets twice after U-Boot 'reset' command:

(It doesn't always stop at "DRAM:" line but that position is most frequent) Maybe you have some ideas on this subject?

hmm, if it's only on soft-resets, can you try adding HID0_ENABLE_INSTRUCTION_CACHE to CONFIG_SYS_HID0_INIT in addition to _FINAL? Some cache state is preserved over a soft-reset...

-----Original Message-----
From: u-boot-bounces at lists.denx.de

On Behalf Of Ilya Yanok
Sent: Friday, June 25, 2010 1:07 AM
To: Phillips Kim-R1AAHA
Cc: u-boot at lists.denx.de
Subject: Re: [U-Boot] [PATCH 2/2] MPC8308ERDB: minimal support for devboard from Freescale

Hi Kim,

Quoted 7 lines · Kim Phillips

Quoted 7 lines

I've enabled icache and now the board sometimes resets twice after U-Boot 'reset' command:

(It doesn't always stop at "DRAM:" line but that position is most frequent) Maybe you have some ideas on this subject?

Quoted 4 lines

hmm, if it's only on soft-resets, can you try adding HID0_ENABLE_INSTRUCTION_CACHE to CONFIG_SYS_HID0_INIT in addition to _FINAL? Some cache state is preserved over a soft-reset...

Thanks for your advice but this doesn't help...

Regards, Ilya.

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Quoted 10 lines · On Thu, 24 Jun 2010 23:36:49 +0400 Ilya Yanok <[email protected]> wrote:

Hi Kim,

Quoted 7 lines · Kim Phillips

Quoted 7 lines

I've enabled icache and now the board sometimes resets twice after U-Boot 'reset' command:

(It doesn't always stop at "DRAM:" line but that position is most frequent) Maybe you have some ideas on this subject?

Quoted 6 lines

Quoted 4 lines

hmm, if it's only on soft-resets, can you try adding HID0_ENABLE_INSTRUCTION_CACHE to CONFIG_SYS_HID0_INIT in addition to _FINAL? Some cache state is preserved over a soft-reset...

Thanks for your advice but this doesn't help...

+++ b/arch/powerpc/cpu/mpc83xx/acr.c

arch/powerpc/cpu/mpc83xx/acr.c new file +19 -0

@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,

Quoted 1 line

Quoted 1 line

Thanks for your advice but this doesn't help...

turning icache on early causes a different pattern of bus accesses when fetching code, and this might trigger bus accesses that interfere with code that sets bus configuration registers, such as the acr. Can you test this patch please?:

turning icache on early causes a different pattern of bus accesses when fetching code, and this might trigger bus accesses that interfere with code that sets bus configuration registers, such as the acr. Can you test this patch please?:

This patch provides support for MPC8308ERDB development board from

Quoted 2 lines

This patch provides support for MPC8308ERDB development board from

so, according to this document:

http://cache.freescale.com/files/32bit/doc/user_guide/MPC8308RDBUG.pdf

the board name is just 'mpc8308rdb', not 'mpc8308erdb'. AFAICT, there is no version of the 8308 that has an 'E'ncryption unit, so the name should probably be changed.

apologies for not seeing this earlier...

This patch provides support for MPC8308RDB development board from Freescale with a minimal set of features:
Dual UART is supported
NOR flash is supported
Both TSEC Ethernet controllers are supported
PCI Express initialization is supported

The following features are enabled in configuration but not fully tested:
I2C (used to get the board revision)
I2C-connected RTC
VSC7385 switch

There is one (hopefully) minor issue: on soft reset the board sometimes resets twice. I've not managed to find the fix for this problem yet. As a workaround instruction cache can be disabled.

Signed-off-by Ilya Yanok <[email protected]>

---